Abstract: One embodiment of the present invention sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, and a lid having a top portion and an end portion and configured to encapsulate the one or more devices. The top portion is thinner than the end portion. One advantage of the disclosed design is that the overall height of an IC package may be reduced without significantly impacting the structural integrity or co-planarity of the IC package.

Abstract: A packaging substrate includes a high reliability via structure that extends through multiple layers of the packaging substrate. The via structure includes an opening formed through multiple layers of the packaging substrate and an electrically conductive layer that is deposited in the opening. The opening is formed in a single material removal process and the conductive layer is formed in a single deposition process. Because the conductive layer is formed in a single deposition process, the conductive layer provides an interface-free conductive path between the multiple layers.

Abstract: A system, method, and computer program product are provided for preparing a substrate post. In use, a first solder mask is applied to a substrate. Additionally, a post is affixed to each of one or more pads of the substrate. Further, a second solder mask is applied to the substrate.

Abstract: A system, method, and computer program product are provided for controlling warping of a substrate. In use, a first solder mask is attached to a top side of a substrate. Additionally, a second solder mask is attached to a bottom side of the substrate, wherein the first solder mask and the second solder mask control warping of the substrate.

Abstract: A system, method, and computer program product are provided for affixing a post to a substrate pad. In use, a post is affixed to each of one or more pads of a substrate, where each post receives a ball of a package during an assembly process.