Abstract: The present invention discloses an array substrate, a liquid crystal display (LCD) and a manufacturing method of the array substrate, wherein, the array substrate comprises insulation layers and an electrode layer densely covered with many pixel electrodes, and has many electric field changing areas; the insulation layers in these areas are not as thick as those in other areas, and the pixel electrodes in the electric field changing areas and in other areas can be conducted. In the present invention, due to the electric field changing areas, the electric field intensities on the surface of the electric field changing areas and on the surface of the electrodes are inconsistent when electrical power is applied, causing the inclination of the power line near these areas, so liquid crystal molecules can deflect in different special directions around these areas, which can expand the display angle.

Abstract: The present invention discloses a pixel matrix, an array substrate, a liquid crystal display device and a driving method. A pixel matrix comprises a plurality of sub-pixels arranged in rows; the sub-pixels are distinguished in colors, and comprise a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels which are respectively corresponding to three primary colors. Each row comprises said sub-pixels of more than two colors. In the present invention, a plurality of sub-pixel electrodes are corresponding to different colors in each row of matrix, so when under solid color drive or two-solid color mixture drive, if the matrix in the current row is under drive, not all the gate lines are needed to open, so that the load of data scanning chip in the same chronology is reduced so as to further reduce the temperature of the data chip and extend the service life of the data chip.

Abstract: The invention discloses a driving circuit, a liquid crystal panel, a liquid crystal display (LCD), and a driving method. A data driving circuit of a liquid crystal panel comprises a plurality of data driving chips. A plurality of first sub-voltage dividing circuits and second controllable sub-voltage dividing circuits are connected in series between said data driving chips and the common electrode of the liquid crystal panel, and each first sub-voltage dividing circuit and each second sub-voltage dividing circuit are connected by a data line of the liquid crystal panel. In the invention, two control voltages can be obtained only by controlling the second sub-voltage dividing circuit, which is only one distortion correction (Gamma) circuit used, thereby simplifying the circuit structure, saving PCB space, and reducing the cost.

Abstract: A pixel structure is disclosed, comprising: a data line; a gate line, located on a first metal layer; a pixel electrode, located on a transparent electrode layer; and an array common line. The array common line extends to form a first shielding metal parallel to the gate line. This invention also relates to a liquid crystal display. The pixel structure of this invention and the accompanying liquid crystal display features the array common line that extends to form a first shielding metal, to settle the drawbacks of low aperture rate and excess side capacitance between the pixel electrode and the gate line of the conventional techniques.

Abstract: The present invention proposes a fan-out design, a method of forming the fan-out design and a liquid crystal display adopting the fan-out design. The fan-out design has at least two metallic layers. The metallic layers, serving as conducting wires, are connected to different chip pins for transmitting signals. The two metallic layers are not overlapped near the chip pins and are overlapped away from the chip pins. The two metallic layers are separated from each other with an insulating layer. The two metallic layers are not overlapped near the chip pins, so the thickness of the chip pins is thinner. This can avoid the thickness of the fan-out design from being too thick. Besides, the two metallic layers are overlapped away from the chip pins, so the gap between every two conducting wires is greater. It makes the design and the manufacturing process easier and improves yield rate as well.