Patents by Inventor Zuo-Chang Ye

Zuo-Chang Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Parasitic effects analysis of circuit structures
    Patent number: 7853910
    Abstract: Method, system, and computer program product for analyzing circuit structures for parasitic effects are provided. Data from a previous parasitic effect analysis of a circuit structure is used to perform parasitic effect analysis on another circuit structure even when the circuit structures are not identical, provided the circuit structures are similar.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: December 14, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Zhenhai Zhu, Joel Phillips, Zuo-Chang Ye