Patents by Inventor ZUOPENG HE
ZUOPENG HE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11538686Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a base, a pattern transfer material layer being formed above the base; performing first ion implantation, to dope first ions into the pattern transfer material layer, to form first doped mask layers arranged in a first direction; forming first trenches in the pattern transfer material layer on two sides of the first doped mask layer in a second direction, to expose side walls of the first doped mask layer; forming mask spacers on side walls of the first trenches; performing second ion implantation, to dope second ions into some regions of the pattern transfer material layer that are exposed from the first doped mask layers and the first trenches, to form second doped mask layers; removing the remaining pattern transfer material layer, to form second trenches; and etching the base along the first trenches and the second trenches, to form a target pattern.Type: GrantFiled: January 22, 2021Date of Patent: December 27, 2022Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Zhu Chen, Yang Ming, Bei Duohui, Zuopeng He, Chao Zhang, Ni Bai Bing
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Patent number: 11373949Abstract: Interconnect structures are provided. An interconnect structure includes a substrate; a first dielectric layer on the substrate and including an opening for a first interconnect layer extending to the substrate; a first metal layer having a first portion in the opening and a second portion in contact with the first portion and on a portion of the first dielectric layer adjacent to the opening; a second dielectric layer on the first dielectric layer and on the first metal layer, the second dielectric layer including a trench for a second interconnect layer, the trench exposing the second portion of the first metal layer; and a second metal layer in the trench, wherein the second portion of the first metal layer forms a lower portion of the second interconnect layer.Type: GrantFiled: January 6, 2020Date of Patent: June 28, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Ningbo Semiconductor International CorporationInventors: Zuopeng He, Ji Guang Zhu
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Publication number: 20210398810Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a base, a pattern transfer material layer being formed above the base; performing first ion implantation, to dope first ions into the pattern transfer material layer, to form first doped mask layers arranged in a first direction; forming first trenches in the pattern transfer material layer on two sides of the first doped mask layer in a second direction, to expose side walls of the first doped mask layer; forming mask spacers on side walls of the first trenches; performing second ion implantation, to dope second ions into some regions of the pattern transfer material layer that are exposed from the first doped mask layers and the first trenches, to form second doped mask layers; removing the remaining pattern transfer material layer, to form second trenches; and etching the base along the first trenches and the second trenches, to form a target pattern.Type: ApplicationFiled: January 22, 2021Publication date: December 23, 2021Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Zhu CHEN, Yang MING, Bei Duohui, Zuopeng HE, Chao Zhang, Ni BAI BING
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Publication number: 20200144175Abstract: Interconnect structures are provided. An interconnect structure includes a substrate; a first dielectric layer on the substrate and including an opening for a first interconnect layer extending to the substrate; a first metal layer having a first portion in the opening and a second portion in contact with the first portion and on a portion of the first dielectric layer adjacent to the opening; a second dielectric layer on the first dielectric layer and on the first metal layer, the second dielectric layer including a trench for a second interconnect layer, the trench exposing the second portion of the first metal layer; and a second metal layer in the trench, wherein the second portion of the first metal layer forms a lower portion of the second interconnect layer.Type: ApplicationFiled: January 6, 2020Publication date: May 7, 2020Inventors: Zuopeng HE, Ji Guang ZHU
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Patent number: 10553536Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a first dielectric layer on the substrate and having an opening for a first interconnect layer extending to the substrate, forming a first mask layer on a portion of the first dielectric layer spaced apart from the opening, forming a first metal layer filling the opening and covering a portion of the first dielectric layer not covered by the first mask layer, removing the first mask layer, forming a second dielectric layer on the first dielectric layer and on the first metal layer and having a trench for a second interconnect layer, the trench exposing a portion of the first metal layer; and forming a second metal layer filling the trench and in contact with the exposed portion of the first metal layer.Type: GrantFiled: September 26, 2017Date of Patent: February 4, 2020Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATIONInventors: Zuopeng He, Ji Guang Zhu
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Publication number: 20180151488Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a first dielectric layer on the substrate and having an opening for a first interconnect layer extending to the substrate, forming a first mask layer on a portion of the first dielectric layer spaced apart from the opening, forming a first metal layer filling the opening and covering a portion of the first dielectric layer not covered by the first mask layer, removing the first mask layer, forming a second dielectric layer on the first dielectric layer and on the first metal layer and having a trench for a second interconnect layer, the trench exposing a portion of the first metal layer; and forming a second metal layer filling the trench and in contact with the exposed portion of the first metal layer.Type: ApplicationFiled: September 26, 2017Publication date: May 31, 2018Inventors: ZUOPENG HE, Ji Guang Zhu
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Patent number: 9754893Abstract: Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy.Type: GrantFiled: September 22, 2015Date of Patent: September 5, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Jingxiu Ding, Zuopeng He
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Patent number: 9607895Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having an upper surface and a bottom surface; and forming a deep hole in the substrate from the upper surface. The method also includes forming an amorphous silicon layer on a side surface and a bottom surface of the deep hole to promote a preferred crystal orientation in subsequently formed layers. Further, the method includes forming a barrier layer having a preferred orientation along the (111) crystal face on the barrier layer. Further, the method also includes forming a metal layer having a preferred orientation along the (111) crystal face on the barrier layer to fill the through hole.Type: GrantFiled: May 27, 2015Date of Patent: March 28, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Zuopeng He, Hongbo Zhao
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Publication number: 20160093601Abstract: Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy.Type: ApplicationFiled: September 22, 2015Publication date: March 31, 2016Inventors: JINGXIU DING, ZUOPENG HE
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Publication number: 20160013135Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having an upper surface and a bottom surface; and forming a deep hole in the substrate from the upper surface. The method also includes forming an amorphous silicon layer on a side surface and a bottom surface of the deep hole to promote a preferred crystal orientation in subsequently formed layers. Further, the method includes forming a barrier layer having a preferred orientation along the (111) crystal face on the barrier layer. Further, the method also includes forming a metal layer having a preferred orientation along the (111) crystal face on the barrier layer to fill the through hole.Type: ApplicationFiled: May 27, 2015Publication date: January 14, 2016Inventors: ZUOPENG HE, HONGBO ZHAO