Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: The present application relates to a supercomputing server including: a case housing defining an accommodating space and provided with a mounting hole allowing communication between the accommodating space and an external environment; and a control unit disposed at an end portion of the case housing corresponding to the mounting hole and configured to be moved into or out of the accommodating space through the mounting hole. After the control unit is disassembled from the case housing, the control unit may be moved out of the accommodating space through the mounting hole at the end portion of the case housing to maintain the control unit. After the maintenance, the control unit is moved into the accommodating space through the mounting hole, and the control unit is fixed at the end portion of the case housing.

Abstract: The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, including: an input terminal, configured to receive input data; an output terminal, configured to provide output data in response to the input data; clock signal terminal(s), configured to receive clock signal(s); a first latch unit, configured to latch the input data from the input terminal and transmit the input data under control of the clock signal(s); and a second latch unit, configured to latch data from the first latch unit and transmit the data latched by the first latch unit under control of the clock signal(s), where the first latch unit and the second latch unit are sequentially connected in series between the input terminal and the output terminal, and where the output terminal is configured to use data from the second latch unit as the output data for outputting.

Abstract: A hashboard, a power supply system of a digital processing device and the digital processing device. The digital processing device comprises: a housing; N (>2) hashboards and a control board both located inside the housing. Each hashboard comprises: a substrate; power positive and power negative terminals respectively mounted on the substrate and adapted to be connected to another hashboard in series; a communication interface mounted on the substrate; and computing chips mounted on the substrate. A signal transfer path of the computing chips has a chain configuration. The N hashboards are connected in series to form a series power supply configuration, a power positive terminal of a first hashboard in the series power supply configuration is connected to a positive terminal of a power supply, and a power negative terminal of a last hashboard in the series power supply configuration is connected to a negative terminal of the power supply.

Abstract: A computing device and a computing system for digital currency are disclosed. The computing system comprises: computing devices (comprising first and second computing devices) each comprising two ports; and a signal transmission path connecting the computing devices in series. Each computing device is connected to the signal transmission path via the two ports. The first computing device is configured to receive, from the signal transmission path through one of the two ports, a signal specific to an address of the first computing device to a local storage device thereof. The second computing device is configured to receive, from the signal transmission path through one of the two ports, a signal to a local storage device thereof, and forward the signal, which is not specific to an address of the second computing device, or an adjusted version of the signal to the signal transmission path through one of the ports.

Abstract: A standard unit (100) for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit (100) includes a first transistor (110) of a first threshold type and a second transistor (120) of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.

Abstract: Disclosed is a method for determining configuration parameters of a data processing device, including: operating the data processing device by using configuration parameters, which are universal optimization configuration parameters obtained according to a universal operating parameter model; during the operating process, changing the configuration parameters to obtain a dedicated operating parameter data set which includes a plurality of groups of operating parameters, and-each of which includes configuration parameters and capability parameters of the data processing device when the data processing device is operating under the configuration parameters; executing model training by using the dedicated operating parameter data set to obtain a dedicated operating parameter model; and obtaining optimal configuration parameters according to the dedicated operating parameter model, and operating the data processing device according to the optimal configuration parameters, where the optimal configuration parameter

Abstract: Embodiments of this application disclose a resonant tank circuit, a power supply using the same, and an electronic device. The resonant tank circuit includes: a number-of-turns variable transformer unit having an output end coil and an input end coil including at least two first connection ends and a second connection end; and a switch switching unit having a control end, a first input end, and at least two first output ends electrically connected to the first connection ends in a one-to-one manner, The number of coil turns between each of the first connection ends and the second connection end is not equal. A quantity of the first output ends is equal to a quantity of the first connection ends. The switch switching unit turns on circuit connection between the first input end and one of the first output ends according to a control signal received by the control end.

Abstract: The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

Abstract: A multi-bit register (200), a chip, and a computing apparatus, the multi-bit register (100) including: a plurality of register units (210-1, 210-2, . . . , 210-N), each of which is configured to store a bit of data, and the plurality of register units (210-1, 210-2, . . . , 210-N) being connected in parallel to each other; a clock buffer configured to provide a clock signal for the plurality of register units (210-1, 210-2, . . . , 210-N), wherein the plurality of register units (210-1, 210-2, . . . , 210-N) is arranged into an array of register units, and the clock buffer is arranged at an intervening position of the array of register units (210-1, 210-2, . . . , 210-N).

Abstract: Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

Abstract: The present disclosure relates to clock circuits, computing chips, hash boards and data processing devices. A clock circuit comprises M stages of clock drive circuits that are connected in series, M being an integer that is no less than 2, wherein N inverters connected in series are arranged between an input port and an output port of each stage of the M stages of clock drive circuits, N being an odd number that is no less than 3. The clock circuit may provide clock signals with excellent performance.

Abstract: A dynamic D flip-flop with an inverted output involves an input end (101) used for receiving input data; an output end (102) used for providing output data to respond to the input data; a clock signal end (103) used for receiving a clock signal; a first latch (104) used for latching the input data from the input end (101) and performing inverting transmission on the input data under the control of the clock signal; a second latch (105) used for latching data from the first latch (104) and performing inverting transmission on the data latched by the first latch (104) under the control of the clock signal; and an inverter (106) used for performing inverting output on the data received from the second latch (105), the first latch (104), the second latch (105), and the inverter (106) being sequentially connected in series between the input end and the output end.

Abstract: A data processing device and a data processing system are provided. The data processing device includes a housing, which is thermally conductive and defines a sealed accommodating cavity; a hashboard, which is arranged in the accommodating cavity and is in fixed connection to the housing; a control board, which is in communicative connection to the hashboard; and a power supply module, which is in electrical connection to the hashboard.

Abstract: An electronic device includes an arithmetic unit layer and a power supply. The arithmetic unit layer comprises at least one arithmetic unit. Each arithmetic unit comprises a first housing in shape of cuboid. The height direction of the first housing extends in a first direction. The width direction extends in a second direction perpendicular to the first direction. The first housing is provided with first and second openings at both ends in the height direction to form a coolant passage extending in the first direction. The power supply and arithmetic unit layer are laminated in the second or a third direction. The height direction of the power supply is aligned with the height direction of each arithmetic unit. The power supply is provided with third and fourth openings at both ends in the height direction to form a coolant passage extending in the height direction of the power supply.

Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Abstract: A standard unit (100) for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit (100) includes a first transistor (110) of a first threshold type and a second transistor (120) of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.