Abstract: The present disclosure relates to a storage device, a system-on-chip including the storage device, and a computing apparatus. The storage device includes a storage module and a clock gating module. The storage module includes latch units each assigned with an address and having an input end for receiving write data. The clock gating module includes first and second stages of clock gating units. The first stage receives an input clock signal and an enable signal obtained based on first address decoding of a write address and output an enable clock signal to a respective clock gating unit of the second stage. The second stage receives an enable clock signal outputted by a respective clock gating unit of the first stage and an enable signal obtained based on second address decoding of the write address and output an enable clock signal to a respective latch unit.

Abstract: A control method and apparatus for a new energy camera device, a camera device, a storage medium, and a program product are provided. The control method includes: determining a current electric quantity of the battery assembly and a predicted duration for full charging the battery assembly by the new energy charging assembly; determining an operation mode to be adopted from N preset operation modes of the new energy camera device based on the current electric quantity and the predicted duration for full charging the battery assembly, wherein N is a positive integer of at least 2; and controlling the new energy camera device to operate in the determined operation mode. In the embodiments of the present application, the operation mode to be adopted is determined from a plurality of operation modes based on the current electric quantity and the predicted duration for full charging the battery assembly, which helps to solve the defect of the continuous operation in a low power consumption mode in the related art.

Abstract: The present disclosure relates to a filter, a filtering method, a data processing system, and a chip. A filter for performing N-dimensional Gaussian filtering on an N-dimensional data set, where N is 2 or 3, the filter including: a calculation factor obtaining module configured to obtain N calculation factors for N dimensions, where the N calculation factors correspond to N one-dimensional Gaussian kernels derived from performing N-dimensional vector decomposition on an N-dimensional Gaussian kernel to be used for the N-dimensional data set; and a calculation module including N calculation sub-modules for N dimensions that are arranged in a cascading manner, where each calculation sub-module is configured to perform, in a respective dimension using a respective calculation factor, one-dimensional Gaussian filtering on an N-dimensional data set input into the calculation module.

Abstract: Embodiments of the present disclosure provide a data transmission method and apparatus, a system, an electronic device, and a storage medium. The method is applied to a relay device in an intelligent collecting system including a host device and the relay device independently deployed within short range; the relay device includes a first network module configured to access a first network and a second network module configured to access a second network; the method includes: receiving from the host device first data including environmental data collected by the host device; selecting the first network or the second network as an access network for accessing a wide area network according to a network quality of the first network and the second network; and transmitting second data to a cloud platform connected with the wide area network through the access network, the second data including the environmental data.

Abstract: The present disclosure relates to a storage device, a system-on-chip including the storage device, and a computing apparatus. The storage device includes a storage module and a clock gating module. The storage module includes latch units each assigned with an address and having an input end for receiving write data. The clock gating module includes first and second stages of clock gating units. The first stage receives an input clock signal and an enable signal obtained based on first address decoding of a write address and output an enable clock signal to a respective clock gating unit of the second stage. The second stage receives an enable clock signal outputted by a respective clock gating unit of the first stage and an enable signal obtained based on second address decoding of the write address and output an enable clock signal to a respective latch unit.

Abstract: The present disclosure relates to an integrated circuit including parallel dynamic registers, an operation chip, and a computing apparatus. The integrated circuit includes a plurality of dynamic registers arranged in one column. The plurality of dynamic registers have respective input data signals and output data signals, and receive a same control signal. The plurality of dynamic registers include a first dynamic register arranged in a first row and a second dynamic register arranged in a second row adjacent to the first row. The first dynamic register includes a first tristate gate, and the second dynamic register includes a second tristate gate. The first tristate gate includes a first field effect transistor (FET), and the second tristate gate includes a second FET with a same polarity as the first FET. The first FET is adjacent to the second FET.

Abstract: The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.

Abstract: The present disclosure relates to a power domain management circuit and a system on chip. The power domain management circuit includes: an enable unit, configured to generate an enable signal with a first preset level in a case of receiving an isolation set signal, or to generate an enable signal with a second preset level in a case of receiving a reset indication signal; and a clamping unit, electrically connected to the enable unit, and configured to clamp an initial signal transmitted from a first power domain to a second power domain to generate a target signal with a third preset level in a case of receiving the enable signal with the first preset level, or to skip clamping the initial signal to generate a target signal with a level that varies with a level of the initial signal in a case of receiving the enable signal with the second preset level.

Abstract: The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, including: an input terminal, configured to receive input data; an output terminal, configured to provide output data in response to the input data; clock signal terminal(s), configured to receive clock signal(s); a first latch unit, configured to latch the input data from the input terminal and transmit the input data under control of the clock signal(s); and a second latch unit, configured to latch data from the first latch unit and transmit the data latched by the first latch unit under control of the clock signal(s), where the first latch unit and the second latch unit are sequentially connected in series between the input terminal and the output terminal, and where the output terminal is configured to use data from the second latch unit as the output data for outputting.

Abstract: Provided in the embodiments of the present application are a brightness measurement method and apparatus, a control method and apparatus for a photographic apparatus, and a medium. In the brightness measurement method, a brightness measurement circuit is used to perform brightness measurement, the brightness measurement circuit comprising: a photosensitive diode, a switch and at least two measurement groups.

Abstract: The present disclosure relates to a battery management method, a battery management apparatus, and an electronic device. The battery management method includes: acquiring a current power level of a battery for the electronic device when the electronic device receives a wake-up signal; determining an operation mode of the electronic device according to the current power level of the battery, wherein a maximum power in the determined operation mode is supportable by the current power level of the battery; and controlling the electronic device to operate in the determined operation mode.

Abstract: Please replace the Abstract with the following: An electronic device and an operating method therefor, and a storage medium are provided. A method of operating an electronic device includes when operating the electronic device in a first operation mode: causing the electronic device to be in a first state in which a pre-roll module captures and records a video; causing the electronic device to enter a second state in response to an event being detected in which a camera module captures and records a video; determining whether a current image frame of the video captured by the camera module contains a target in response to a preset period of time having elapsed since the event is detected; causing the electronic device to be maintained in the second state in response to the target being contained; causing the electronic device to enter the first state in response to the target being not contained.

Abstract: The present disclosure relates to a circuit unit, a logic circuit, a processor, and a computing apparatus. A circuit unit is provided, including: an output terminal (OUT); an output stage (105), configured to provide an output signal to the output terminal; a first node (A), to which an input of the output stage is connected; and a feedback stage (107) that receives the output signal at the output terminal and selectively provides feedback to the node. A logic circuit is further provided, including an input stage that receives a signal input, and the circuit unit. The first node receives a signal based on an output of the input stage.

Abstract: A data interaction method, apparatus and system, an electronic device, and a storage medium are disclosed. The method includes: obtaining, in response to a parameter writing operation signal, a first parameter and storing the first parameter in a downlink buffer; acquiring a second parameter from the downlink buffer and transmitting the second parameter to a data processing circuit unit, for the data processing circuit unit to process data based on the second parameter so as to obtain output data; storing the output data in an uplink buffer; recording the quantity of output data stored in the uplink buffer, and transmitting, when the quantity of the output data stored in the uplink buffer reaches an output quantity threshold, storage state information of the uplink buffer; and outputting the output data stored in the uplink buffer in bulk in response to a data reading operation instruction.

Abstract: An electronic device, a cloud device, a client device, and operating methods therefor are provided. A method of operating an electronic device including a camera module configured to capture a video and having a first state, in which the camera module is activated to capture a video, includes: in response to that an event in one or more types of events is detected, in a case where the electronic device is in the first state, transmitting an alarm message indicating that the event is detected, and transmitting, as an alarm video, a video captured by the camera module after the event is detected; and after the alarm message is transmitted, in response to that an event in the one or more types of events is detected, not transmitting an alarm message indicating that the event is detected but continuing transmitting the video captured by the camera module.

Abstract: This disclosure relates to a method, an apparatus, and a data processing device for controlling a frequency search speed, the method for controlling the frequency search speed including: obtaining parameter information of a frequency search speed regulation gear; obtaining a frequency search parameter based on the parameter information of the frequency search speed regulation gear; and performing frequency search based on the obtained frequency search parameter.

Abstract: The present disclosure relates to a phase-locked loop circuit and a signal processing device.

Abstract: The present application relates to a supercomputing server including: a case housing defining an accommodating space and provided with a mounting hole allowing communication between the accommodating space and an external environment; and a control unit disposed at an end portion of the case housing corresponding to the mounting hole and configured to be moved into or out of the accommodating space through the mounting hole. After the control unit is disassembled from the case housing, the control unit may be moved out of the accommodating space through the mounting hole at the end portion of the case housing to maintain the control unit. After the maintenance, the control unit is moved into the accommodating space through the mounting hole, and the control unit is fixed at the end portion of the case housing.