Abstract: The present disclosure provides a semiconductor structure and a method for preparing it. After planarization of the Cu layer, by means of wet etch process, Cu residues near an edge of a Cu post can be effectively removed, and a first height difference is configured to be between the Cu post and an insulating layer. Further, an Si substrate is then dry etched, so that a second height difference is configured to be between the Si substrate and the insulating layer, and the second height difference is arranged to be greater than the first height difference. In this way, a connection of Cu inside and outside the insulating layer may be further avoided, thereby effectively avoiding an influence on electrical properties of a device.

Abstract: The present disclosure provides a semiconductor structure and a method preparing it. After planarization of the Cu layer, a Si substrate is dry etched, so that a first height difference is configured in between the top surfaces of the the Si substrate and an insulating layer. By means of a wet etch process, Cu residues near an edge of a Cu post may be effectively removed. A second height difference is configured in between the top surfaces of the Cu post and the insulating layer. The first height difference is arranged to be greater than the second height difference. Channeling of Cu trace residues through the insulating layer are thereby avoided, effectively mitigating electrical leakage. Further, the Si substrate may be covered by a passivation layer, to prevent a conductive channel from being formed on the Si substrate, thereby further avoiding negative impact on the electrical properties of the device.

Abstract: The present disclosure provides an adapter board for semiconductor device packaging and a method manufacturing the same. The method includes: providing a stacked structure including a support substrate, a separation layer, and a silicon substrate, a TSV is formed in the silicon substrate, the TSV is filled with a copper conductive pillar, a diffusion barrier is formed between the copper conductive pillar and a side walls of the TSV; grinding a top surface of the silicon substrate; polishing a top surface of the remaining silicon substrate using a chemical mechanical polishing process until the TSV is exposed; etching the copper conductive pillar to form a groove; filling the groove with a protective layer; etching the top surface of the silicon substrate to expose the copper conductive pillar; forming an insulating layer on the top surface of the silicon substrate using a chemical vapor deposition process.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The method at least includes: applying a first wet etching to remove a Ti metal seed layer to expose a dielectric layer; performing a first pretreatment on the dielectric layer; forming a first groove in the dielectric layer to expose an interfacial Ti metal seed layer in the dielectric layer; applying a second wet etching to remove the interfacial Ti metal seed layer; and performing a second pretreatment on the dielectric layer to form a second groove with a depth greater than that of the interfacial Ti metal seed layer, which can effectively remove the interfacial Ti metal seed layer, and results in a depth difference between the bottom of the second groove and the interfacial Ti metal seed layer, thereby avoiding short circuits caused by the interfacial Ti metal seed layer, and improving device reliability.

Abstract: The present disclosure provides a semiconductor structure and a method for preparing it. After planarization of the Cu layer, by means of wet etch process, Cu residues near an edge of a Cu post can be effectively removed, and a first height difference is configured to be between the Cu post and an insulating layer. Further, an Si substrate is then dry etched, so that a second height difference is configured to be between the Si substrate and the insulating layer, and the second height difference is arranged to be greater than the first height difference. In this way, a connection of Cu inside and outside the insulating layer may be further avoided, thereby effectively avoiding an influence on electrical properties of a device.

Abstract: The present disclosure provides a semiconductor structure and a method preparing it. After planarization of the Cu layer, a Si substrate is dry etched, so that a first height difference is configured in between the top surfaces of the the Si substrate and an insulating layer. By means of a wet etch process, Cu residues near an edge of a Cu post may be effectively removed. A second height difference is configured in between the top surfaces of the Cu post and the insulating layer. The first height difference is arranged to be greater than the second height difference. Channeling of Cu trace residues through the insulating layer are thereby avoided, effectively mitigating electrical leakage. Further, the Si substrate may be covered by a passivation layer, to prevent a conductive channel from being formed on the Si substrate, thereby further avoiding negative impact on the electrical properties of the device.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The method at least includes: applying a first wet etching to remove a Ti metal seed layer to expose a dielectric layer; performing a first pretreatment on the dielectric layer; forming a first groove in the dielectric layer to expose an interfacial Ti metal seed layer in the dielectric layer; applying a second wet etching to remove the interfacial Ti metal seed layer; and performing a second pretreatment on the dielectric layer to form a second groove with a depth greater than that of the interfacial Ti metal seed layer, which can effectively remove the interfacial Ti metal seed layer, and results in a depth difference between the bottom of the second groove and the interfacial Ti metal seed layer, thereby avoiding short circuits caused by the interfacial Ti metal seed layer, and improving device reliability.

Abstract: Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate can be provided. A gate structure can be formed on the substrate. A stress layer can be formed in the substrate on both sides of the gate structure. Barrier ions can be doped in the stress layer to form a barrier layer in the stress layer. The barrier layer can have a preset distance from a surface of the stress layer. An electrical contact layer can be formed using a portion of the stress layer on the barrier layer by a salicide process. The electrical contact layer can contain a first metal element. The first metal element can have a resistivity lower than a resistivity of a silicidation metal. The barrier layer can prevent atoms of the first metal element from diffusing to a bottom of the stress layer.

Abstract: Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate can be provided. A gate structure can be formed on the substrate. A stress layer can be formed in the substrate on both sides of the gate structure. Barrier ions can be doped in the stress layer to form a barrier layer in the stress layer. The barrier layer can have a preset distance from a surface of the stress layer. An electrical contact layer can be formed using a portion of the stress layer on the barrier layer by a salicide process. The electrical contact layer can contain a first metal element. The first metal element can have a resistivity lower than a resistivity of a silicidation metal. The barrier layer can prevent atoms of the first metal element from diffusing to a bottom of the stress layer.