Patents by Inventor Zvi Leib SHMILOVICI

Zvi Leib SHMILOVICI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11882041
    Abstract: A network device includes first, second, and third processors. The first processor detects congestion in a packet flow. The packet flow is i) one packet flow among a plurality of packet flows and ii) is formed of a plurality of packets of a same type received from a first device in a network via a first network connection. The packets in the packet flow are destined for a second device in the network. When congestion notification packet generation is enabled for the packet flow, the second processor generates a congestion notification packet by replicating a packet from the packet flow and sends the congestion notification packet to the first device via the first network connection. The congestion notification packet identifies the packet flow for which congestion is detected. The third processor forwards the plurality of packets in the packet flow to the second device via a second network connection.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: January 23, 2024
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Zvi Leib Shmilovici, Gideon Navon
  • Publication number: 20230036088
    Abstract: A network device includes first, second, and third processors. The first processor detects congestion in a packet flow. The packet flow is i) one packet flow among a plurality of packet flows and ii) is formed of a plurality of packets of a same type received from a first device in a network via a first network connection. The packets in the packet flow are destined for a second device in the network. When congestion notification packet generation is enabled for the packet flow, the second processor generates a congestion notification packet by replicating a packet from the packet flow and sends the congestion notification packet to the first device via the first network connection. The congestion notification packet identifies the packet flow for which congestion is detected. The third processor forwards the plurality of packets in the packet flow to the second device via a second network connection.
    Type: Application
    Filed: October 10, 2022
    Publication date: February 2, 2023
    Applicant: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Zvi Leib SHMILOVICI, Gideon NAVON
  • Patent number: 11496401
    Abstract: A system includes first, second, and third processors. The first processor is configured to detect congestion in a packet flow formed of a plurality of packets of a same type received from a first device in a network via a first network connection. The packets in the packet flow being destined for a second device in the network. The second processor is configured to send, when congestion notification packet generation is enabled for the packet flow, a congestion notification packet to the first device via the first network connection. The congestion notification packet identifies the packet flow for which congestion is detected. The third processor is configured to forward the plurality of packets in the packet flow to the second device via a second the network connection.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 8, 2022
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Zvi Leib Shmilovici, Gideon Navon
  • Patent number: 11271857
    Abstract: A method for operating a network device, having data storage with selectably modifiable capacity for storing instructional data for a packet processing operation, includes detecting a need for additional storage for the instructional data, allocating an additional memory block without interrupting operation of the network device, associating with the additional memory block an additional address hashing function, different from each of at least one respective previous address hashing function associated with any previously-allocated memory block. Each respective previous address hashing function transforms a look-up key into a respective addressable location in a previously-allocated memory block, and the additional address hashing function transforms the look-up key into an addressable location in the additional memory block. When a block is deallocated, each unit of instructional data is reprocessed through the hashing function of a different block to which the unit of the instructional data will be moved.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 8, 2022
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Zvi Leib Shmilovici
  • Publication number: 20210083981
    Abstract: A system includes first, second, and third processors. The first processor is configured to detect congestion in a packet flow formed of a plurality of packets of a same type received from a first device in a network via a first network connection. The packets in the packet flow being destined for a second device in the network. The second processor is configured to send, when congestion notification packet generation is enabled for the packet flow, a congestion notification packet to the first device via the first network connection. The congestion notification packet identifies the packet flow for which congestion is detected. The third processor is configured to forward the plurality of packets in the packet flow to the second device via a second the network connection.
    Type: Application
    Filed: November 9, 2020
    Publication date: March 18, 2021
    Applicant: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Zvi Leib SHMILOVICI, Gideon Navon
  • Patent number: 10833998
    Abstract: Aspects of the disclosure provide a network device that includes interface circuitry and packet processing circuitry. The interface circuitry is configured to receive incoming packets from a network and transmit outgoing packets to the network via interfaces. The packet processing circuitry is configured to detect a congestion associated with a packet that is sent from a source device to a destination device in the network and generate a notification packet that is destined to the source device. The notification packet is indicative of a packet flow that the packet belongs to and the presence of the congestion. The packet processing circuitry is configured to send the packet to the destination device via a first interface and send the notification packet to the source device via a second interface.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 10, 2020
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Zvi Leib Shmilovici, Gideon Navon
  • Publication number: 20200287832
    Abstract: A method for operating a network device, having data storage with selectably modifiable capacity for storing instructional data for a packet processing operation, includes detecting a need for additional storage for the instructional data, allocating an additional memory block without interrupting operation of the network device, associating with the additional memory block an additional address hashing function, different from each of at least one respective previous address hashing function associated with any previously-allocated memory block. Each respective previous address hashing function transforms a look-up key into a respective addressable location in a previously-allocated memory block, and the additional address hashing function transforms the look-up key into an addressable location in the additional memory block. When a block is deallocated, each unit of instructional data is reprocessed through the hashing function of a different block to which the unit of the instructional data will be moved.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Inventor: Zvi Leib Shmilovici
  • Patent number: 10700974
    Abstract: A method for operating a network device, having data storage with selectably modifiable capacity for storing instructional data for a packet processing operation, includes detecting a need for additional storage for the instructional data, allocating an additional memory block without interrupting operation of the network device, associating with the additional memory block an additional address hashing function, different from each of at least one respective previous address hashing function associated with any previously-allocated memory block. Each respective previous address hashing function transforms a look-up key into a respective addressable location in a previously-allocated memory block, and the additional address hashing function transforms the look-up key into an addressable location in the additional memory block. When a block is deallocated, each unit of instructional data is reprocessed through the hashing function of a different block to which the unit of the instructional data will be moved.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: June 30, 2020
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Zvi Leib Shmilovici
  • Publication number: 20190238459
    Abstract: A method for operating a network device, having data storage with selectably modifiable capacity for storing instructional data for a packet processing operation, includes detecting a need for additional storage for the instructional data, allocating an additional memory block without interrupting operation of the network device, associating with the additional memory block an additional address hashing function, different from each of at least one respective previous address hashing function associated with any previously-allocated memory block. Each respective previous address hashing function transforms a look-up key into a respective addressable location in a previously-allocated memory block, and the additional address hashing function transforms the look-up key into an addressable location in the additional memory block. When a block is deallocated, each unit of instructional data is reprocessed through the hashing function of a different block to which the unit of the instructional data will be moved.
    Type: Application
    Filed: January 23, 2019
    Publication date: August 1, 2019
    Inventor: Zvi Leib Shmilovici
  • Patent number: 10205586
    Abstract: A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 12, 2019
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Gideon Paul, Erez Reches, Zvi Leib Shmilovici
  • Publication number: 20180198715
    Abstract: Aspects of the disclosure provide a network device that includes interface circuitry and packet processing circuitry. The interface circuitry is configured to receive incoming packets from a network and transmit outgoing packets to the network via interfaces. The packet processing circuitry is configured to detect a congestion associated with a packet that is sent from a source device to a destination device in the network and generate a notification packet that is destined to the source device. The notification packet is indicative of a packet flow that the packet belongs to and the presence of the congestion. The packet processing circuitry is configured to send the packet to the destination device via a first interface and send the notification packet to the source device via a second interface.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 12, 2018
    Applicant: MARVELL ISRAEL (M.l.S.L) LTD.
    Inventors: Zvi Leib Shmilovici, Gideon Navon
  • Patent number: 9847925
    Abstract: Aspects of the disclosure provide a method for collecting distributed counter values in a packet-switched system having multiple distributed packet processors. The method includes receiving a probe packet at a packet processor, storing a counter value corresponding to a flow processed by the packet processor for subsequent delivery to a management controller, and forwarding the probe packet to a next packet processor. The next packet processor stores a counter value of the next packet processor for subsequent delivery to the management controller.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: December 19, 2017
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Tal Mizrahi, Zvi Leib Shmilovici, Gideon Navon
  • Publication number: 20170222792
    Abstract: A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 3, 2017
    Applicant: MARVELL WORLD TRADE LTD
    Inventors: Gideon Paul, Erez Reches, Zvi Leib Shmilovici
  • Publication number: 20150188798
    Abstract: Aspects of the disclosure provide a method for collecting distributed counter values in a packet-switched system having multiple distributed packet processors. The method includes receiving a probe packet at a packet processor, storing a counter value corresponding to a flow processed by the packet processor for subsequent delivery to a management controller, and forwarding the probe packet to a next packet processor. The next packet processor stores a counter value of the next packet processor for subsequent delivery to the management controller.
    Type: Application
    Filed: January 2, 2015
    Publication date: July 2, 2015
    Applicant: MARVELL WORLD TRADE LTD.
    Inventors: Tal MIZRAHI, Zvi Leib SHMILOVICI, Gideon NAVON