Patents by Inventor Zvi Or-Bach

Zvi Or-Bach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220189990
    Abstract: A 3D memory device, the device comprising: a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of bit-line pillars, wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain, wherein said bit-line pillars are vertically oriented, wherein said channel is horizontally oriented, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain, and wherein said plurality of bit-line pillars comprise a thermally conductive path from said plurality of memory cells to an external surface of said device.
    Type: Application
    Filed: February 26, 2022
    Publication date: June 16, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Publication number: 20220181186
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least two metal layers; a plurality of logic gates including the at least two metal layers interconnecting the plurality of first transistors; a plurality of second transistors disposed atop the at least two metal layers; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least two rows by two columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, and where at least one of the second transistors include a metal gate.
    Type: Application
    Filed: February 20, 2022
    Publication date: June 9, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220181304
    Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the first level thickness is less than two microns.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20220181187
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first single crystal transistors; a first metal layer; a second metal layer disposed atop the first metal layer; second transistors disposed atop of the second metal layer; third transistors disposed atop of the second transistors, where at least one of the third transistors includes at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate, and where a distance from at least one of the third transistors to at least one of the second transistors is less than 1 micron.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11355380
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and on the first level, where the control circuits include first single crystal transistors, where the control circuits include at least two metal layers; forming at least one second level disposed on top of the first level; performing a first etch step within the second level; forming at least one third level disposed on top of the at least one second level; performing a second etch step within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the first memory cells include second transistors, and where the second memory cells include third transistors.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 7, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11355381
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: June 7, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220165602
    Abstract: A method for producing a 3D memory device, including: providing a first level including a single crystal layer and control circuits, the control circuits include a plurality of first single crystal transistors; forming at least one second level disposed above the first level; processing to form a plurality of second transistors, where the processing includes forming a plurality of memory cells, each of the plurality of memory cells includes at least one of the plurality of second transistors, where the control circuits control the plurality of memory cells, where at least one of the plurality of memory cells is at least partially atop a portion of the control circuits, where processing the control circuits accounts for a thermal budget associated with processing of the second transistors by adjusting annealing of the first transistors accordingly; processing to replace gate material of at least one of the plurality of second transistors.
    Type: Application
    Filed: February 12, 2022
    Publication date: May 26, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11341309
    Abstract: A method of designing a 3D Integrated Circuit, including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer includes a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the logic and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit connected so to write data to the first memory array, where the first placement includes placement of the first memory array, and where the second placement includes placement of the first logic circuit based on the placement of the first memory array.
    Type: Grant
    Filed: January 22, 2022
    Date of Patent: May 24, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 11342214
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming a plurality of first transistors each including a single crystal channel; forming a first metal layer and a second metal layer, where the first level includes the plurality of first transistors, the first metal layer, and the second metal layer; forming at least one second level disposed above the second metal layer; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where memory cells each include one memory transistor.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: May 24, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220157983
    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes a plurality of capacitors.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 19, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11335731
    Abstract: A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: May 17, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Publication number: 20220149012
    Abstract: A 3D device comprising: a first level comprising first transistors, said first level comprising a first interconnect; a second level comprising second transistors, said second level overlaying said first level; a third level comprising third transistors, said third level overlaying said second level; a plurality of electronic circuit units (ECUs), wherein each of said plurality of ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors, wherein each of said plurality of ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors, wherein each of said plurality of ECUs comprises a third circuit, said third circuit comprising a portion of said third transistors, wherein each of said ECUs comprises a vertical bus, wherein said vertical bus comprises greater than eight pillars and less than three hundred pillars and provides electrical connections between said first circuit and said second circuit.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20220142059
    Abstract: A system for enabling plant growth in an automatic manner, the system including a system growing chamber; automatic transport mechanism; and a cooling sub-chamber, where an inner portion of the cooling sub-chamber is thermally insulated from an outside environment of the cooling sub-chamber, and where the cooling sub-chamber includes a refrigerating mechanism and temperature control electronics.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 12, 2022
    Inventors: Michael Maman, Zvi Or-Bach
  • Publication number: 20220144242
    Abstract: An electrical passenger car, the electrical passenger car comprising: at least two electrically driven motors; motor control electronics; sensors; and wheels, wherein said wheels comprise a first front wheel and a first back wheel, wherein said first back wheel has a radius at least 9% greater than a radius of said first front wheel, and wherein said motor control electronics control said at least two electrically driven motors to provide a greater torque to said front wheel than to said back wheel, or wherein said motor control electronics control said at least two electrically driven motors to provide a greater torque to said back wheel than to said front wheel.
    Type: Application
    Filed: January 26, 2022
    Publication date: May 12, 2022
    Applicant: Or-Ment LLC
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20220147689
    Abstract: A method of designing a 3D Integrated Circuit, including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer includes a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the logic and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit connected so to write data to the first memory array, where the first placement includes placement of the first memory array, and where the second placement includes placement of the first logic circuit based on the placement of the first memory array.
    Type: Application
    Filed: January 22, 2022
    Publication date: May 12, 2022
    Applicant: Monolithic 3D Inc
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 11327227
    Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.
    Type: Grant
    Filed: October 3, 2021
    Date of Patent: May 10, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11329059
    Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: May 10, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20220130684
    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the device includes a plurality of capacitors.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Publication number: 20220130847
    Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.
    Type: Application
    Filed: December 31, 2021
    Publication date: April 28, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20220130905
    Abstract: A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach