Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

Abstract: A method to operate a 3D semiconductor charge trap memory device, the method comprising; executing a memory set-up operation, wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then executing a memory operation on said memory cells, wherein each memory cell of said plurality of memory cells comprises a charge trap layer, wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state. Various 3D devices, processing flows and methods are also disclosed.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an optical waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

Abstract: An electrical passenger car, the electrical passenger car including: at least two electrically driven motors; speed control electronics; and wheels, where the wheels include a front wheel and a back wheel, where the back wheel radius is at least 20% greater than the front wheel radius, where the speed control electronics control the at least two electrically driven motors to provide a greater torque to the front wheel than to the back wheel, and where the speed control electronics control the at least two electrically driven motors to provide a greater torque to the back wheel than to the front wheel.

Abstract: A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring and then bonding the second level on top of the first level; and then thinning the second level to a thickness of less than ten microns, where the bonding includes oxide to oxide bonds.

Abstract: A 3D semiconductor device, the device including: a first die including first transistors and first interconnect; and a second die including second transistors and second interconnect, where the first die is overlaid by the second die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is pretested, where the second die includes an array of memory cells, where the first die includes control logic to control reads and writes to the array of memory cells, where the second die is bonded to the first die, and where the bonded includes hybrid bonding.

Abstract: A server system, the server system including: a memory processor; and a communication link, where the server system includes a program designed to construct a user interface experience graph from a plurality of prior user experience interfacing with a specific software application, and where the prior user experience interfacing had been received into a memory of the memory processor by the communication link.

Abstract: A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.

Abstract: An electrical passenger car, the electrical passenger car including: at least two electrically driven motors; speed control electronics; and wheels, where the wheels include a first front wheel, a second front wheel, a first back wheel, and a second back wheel, where the first back wheel radius is at least 20% greater than the first front wheel radius, where the speed control electronics control the at least two electrically driven motors to provide a greater torque to the first front wheel than to the first back wheel, and where the electrical passenger car is designed to travel for a greater distance for the same axial to wheel friction energy loss than a similar electrical passenger car having wheels of a smaller radius.

Abstract: A 3D semiconductor device, the device including: a first level overlaid by a second level overlaid by a third level overlaid by a fourth level, where the second level includes an array of first memory cells, the first memory cells including first transistors, the first transistors including first sources, first gates, and first drains, where each of the first transistors includes a single the first source, a single the first gate, and a single the first drain, where the third level includes an array of second memory cells, the second memory cells including second transistors, the second transistors including second sources, second gates, and second drains, where each of the second transistors includes a single the second source, a single the second gate, and a single the second drain, where at least one of the first memory cells is self-aligned to at least one of the second memory cells, being processed following the same lithography step; vertically oriented word-lines adapted to control a plurality of the f

Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding; and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.

Abstract: A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a trap-rich layer disposed between the first level and the second level; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the plurality of connection paths includes vertical connections connecting from the first interconnections to the second interconnections, where the third layer includes crystalline silicon, and where the second level is bonded to the first level.

Abstract: A 3D integrated circuit device, including: a first layer including first transistors, overlaid by a second layer including second transistors, overlaid by a third layer including third transistors, where the first layer, the second layer and the third layer are each thinner than 2 microns, where the first layer includes first circuits including at least one of the first transistors, where the second layer includes second circuits including at least one of the second transistors, and where the third layer includes a charge pump circuit and control circuits to control the first circuits and the second circuits.

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer is on top of the first single crystal layer, where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the 3D micro display includes an oxide to oxide bonding structure.

Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.

Abstract: A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.

Abstract: A 3D semiconductor device including: a first level including first single crystal silicon and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors; a second level on top of the first metal layer, the second level including a plurality of second transistors; a third level on top of the second level, the third level including a plurality of third transistors; an oxide layer on top of the third level; a fourth level on top of the oxide layer, the fourth level including second single crystal silicon and many fourth transistors, where at least one of the plurality of second transistors is at least partially self-aligned to at least one of the plurality of third transistors, both being formed following the same lithography step, the fourth level is bonded to the oxide layer, the bonded includes many metal to metal bonded structures.