Abstract: An embedded memory unit includes a memory array having a design size given by an integer n, the array including a matrix of memory cells arranged in n+1 lines, and selection circuitry, coupled to select n of the n+1 lines to which data are to be written and from which the data are to be read. A built-in self-test (BIST) circuit is coupled to test the memory array and to generate a binary pass/fail output. A repair machine is coupled to receive the binary output of the BIST circuit and to drive the selection circuitry to select different sets of n of the lines while driving the BIST circuit to test the memory array, so as to find one of the different sets for which the binary output indicates that the array has passed the self-test.

Abstract: An embedded memory unit includes a memory array having a design size given by an integer n, the array including a matrix of memory cells arranged in n+1 lines, and selection circuitry, coupled to select n of the n+1 lines to which data are to be written and from which the data are to be read. A built-in self-test (BIST) circuit is coupled to test the memory array and to generate a binary pass/fail output. A repair machine is coupled to receive the binary output of the BIST circuit and to drive the selection circuitry to select different sets of n of the lines while driving the BIST circuit to test the memory array, so as to find one of the different sets for which the binary output indicates that the array has passed the self-test.