Patents by Inventor ZVIKA GREENFIELD
ZVIKA GREENFIELD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160225433Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.Type: ApplicationFiled: November 30, 2015Publication date: August 4, 2016Inventors: Kuljit S Bains, John B Halbert, Christopher P Mozak, Theodore Z Schoenborn, Zvika Greenfield
-
Patent number: 9251885Abstract: Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate.Type: GrantFiled: December 28, 2012Date of Patent: February 2, 2016Assignee: Intel CorporationInventors: Zvika Greenfield, Tomer Levy
-
Patent number: 9236110Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.Type: GrantFiled: June 30, 2012Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Kuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn, Zvika Greenfield
-
Publication number: 20150378919Abstract: A memory subsystem includes memory hierarchy that performs selective prefetching based on prefetch hints. A lower level memory detects a cache miss for a requested cache line that is part of a superline. The lower level memory generates a request vector for the cache line that triggered the cache miss, including a field for each cache line of the superline. The request vector includes a demand request for the cache line that caused the cache miss, and the lower level memory modifies the request vector with prefetch hint information. The prefetch hint information can indicate a prefetch request for one or more other cache lines in the superline. The lower level memory sends the request vector to the higher level memory with the prefetch hint information, and the higher level memory services the demand request and selectively either services a prefetch hint or drops the prefetch hint.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: ARAVINDH V. ANANTARAMAN, ZVIKA GREENFIELD, ANANT V. NORI, JULIUS YULI MANDELBLAT
-
Patent number: 9117544Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.Type: GrantFiled: October 31, 2013Date of Patent: August 25, 2015Assignee: Intel CorporationInventors: Kuljit Bains, John Halbert, Christopher Mozak, Theodore Schoenborn, Zvika Greenfield
-
Patent number: 9076019Abstract: A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a “time stamp” indicator associated with the cache line. The “time stamp indicator” is stored in a processor.Type: GrantFiled: June 29, 2011Date of Patent: July 7, 2015Assignee: Intel CorporationInventors: Shay Gueron, Uday Savagaonkar, Francis X. McKeen, Carlos V. Rozas, David M. Durham, Jacob Doweck, Ofir Mulla, Ittai Anati, Zvika Greenfield, Moshe Maor
-
Patent number: 9030903Abstract: A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.Type: GrantFiled: September 24, 2012Date of Patent: May 12, 2015Assignee: Intel CorporationInventors: Kuljit S. Bains, John B. Halbert, Suneeta Sah, Zvika Greenfield
-
Patent number: 9026725Abstract: Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping.Type: GrantFiled: December 27, 2012Date of Patent: May 5, 2015Assignee: Intel CorporationInventors: Alexey Kostinsky, Zvika Greenfield, Christopher P. Mozak, Pavel Konev, Olga Fomenko
-
Patent number: 9009540Abstract: A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.Type: GrantFiled: December 5, 2012Date of Patent: April 14, 2015Assignee: Intel CorporationInventors: Christopher P. Mozak, Theodore Z. Schoenborn, James M. Shehadi, David G. Ellis, Tomer Levy, Zvika Greenfield
-
Patent number: 8959266Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.Type: GrantFiled: August 2, 2013Date of Patent: February 17, 2015Assignee: Intel CorporationInventors: Nadav Bonen, Todd M. Witter, Eran Shifer, Tomer Levy, Zvika Greenfield, Anant V. Nori
-
Publication number: 20150039790Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Inventors: Nadav Bonen, Todd M. Witter, Eran Shifer, Tomer Levy, Zvika Greenfield, Anant V. Nori
-
Patent number: 8938573Abstract: A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.Type: GrantFiled: June 30, 2012Date of Patent: January 20, 2015Assignee: Intel CorporationInventors: Zvika Greenfield, Kuljit S. Bains, Theodore Z. Schoenborn, Christopher P. Mozak, John B. Halbert
-
Publication number: 20150006805Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: DANNIE G. FEEKES, SHLOMO RAIKIN, BLAISE FANNING, JOYDEEP RAY, JULIUS MANDELBLAT, ARIEL BERKOVITS, ERAN SHIFER, ZVIKA GREENFIELD, EVGENY BOLOTIN
-
Patent number: 8868992Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.Type: GrantFiled: December 31, 2009Date of Patent: October 21, 2014Assignee: Intel CorporationInventors: Bryan L. Spry, Theodore Z. Schoenborn, Philip Abraham, Christopher P. Mozak, David G. Ellis, Jay J. Nejedlo, Bruce Querbach, Zvika Greenfield, Rony Ghattas, Jayasekhar Tholiyil, Charles D. Lucas, Christopher E. Yunker
-
Publication number: 20140223197Abstract: A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a “time stamp” indicator associated with the cache line. The “time stamp indicator” is stored in a processor.Type: ApplicationFiled: June 29, 2011Publication date: August 7, 2014Inventors: Shay Gueron, Uday Savagaonkar, Francis X. McKeen, Carlos V. Rozas, David M. Durham, Jacob Doweck, Ofir Mulla, Ittai Anati, Zvika Greenfield, Moshe Maor
-
Publication number: 20140189224Abstract: Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Inventors: ALEXEY KOSTINSKY, ZVIKA GREENFIELD, CHRISTOPHER P. MOZAK, PAVEL KONEV, OLGA FOMENKO
-
Publication number: 20140156935Abstract: In one embodiment, a processor includes at least one execution unit, a near memory, and memory management logic. The memory management logic may be to manage the near memory and a far memory as a unified exclusive memory, where the far memory is external to the processor. Other embodiments are described and claimed.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Inventors: Shlomo Raikin, Zvika Greenfield
-
Publication number: 20140157055Abstract: A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Inventors: CHRISTOPHER P. MOZAK, Thoedore Z. Schoenborn, James M. Shehadi, David G. Ellis, Tomer Levy, Zvika Greenfield
-
Publication number: 20140089576Abstract: A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.Type: ApplicationFiled: September 24, 2012Publication date: March 27, 2014Inventors: Kuljit S. Bains, John B. Halbert, Suneeta Sah, Zvika Greenfield
-
Publication number: 20140085995Abstract: Techniques and mechanisms for determining a count of accesses to a row of a memory device. In an embodiment, the memory device includes a counter comprising circuitry to increment a value of the count in response to detecting a command to activate the row. Circuitry of counter may further set a value of the count to a baseline value in response to detecting a command to refresh the row. In another embodiment, the memory device includes evaluation logic to compare a value of the count to a threshold value. A signal is generated based on the comparison to indicate whether a row hammer event for the row is indicated.Type: ApplicationFiled: September 25, 2012Publication date: March 27, 2014Inventors: Zvika Greenfield, John B. Halbert, Kuljit S. Bains