Abstract: A fast transmission, integrated circuit switching device responsive to at least one external on/off control signal, and including a first input/output node, and a second input/output node, the switching device operative to pass or block the bidirectional transmission of external data signals between the first node and the second node, the switching device comprising a bidirectional field-effect transistor; a first scan cell; and a second scan cell; whereby input and output data signals of the switching device may be sensed and stored.

Abstract: A priority encoder for receiving input request signals at a number of input request terminals and for providing an N-bit output binary code word indicating the binary identification number of the highest-priority, currently-active input request terminal. Each output bit of the output binary code word is provided from a respective logic circuit. Whenever any one of a first group of input request terminals, which are identified as having a logical TRUE value in a particular bit position of the N-bit output binary code word, is active, all of a second group of input request terminals, having a logical FALSE value for the particular bit position, are disabled. Sequential operation of the logic circuits for each output bit is obtained by successively delaying enablement of a logic circuit until high-order logic circuits have completed operation.

Abstract: In a data processing system, a DRAM controller which is incorporated on a single semiconductor chip employs multiple column address strobe input signals that drive multiple column address strobe output signals respectively. The multiple signal channels for the column address strobe input signal and the column address strobe output signals are independent of each other and are each connected to a plurality of memory banks, but to different byte sections of the memory. Direct access to an individual byte of word-wide data is made possible.