Patents by Inventor Zyunya Tanaka
Zyunya Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9640460Abstract: A semiconductor device of the present invention includes: a first substrate (1) on which a power semiconductor element (2) is mounted; a heat-dissipating plate (12); an insulating layer (11) disposed between the first substrate (1) and the heat-dissipating plate (12); and molding resin (4) that molds the first substrate (1), the heat-dissipating plate (12), and the insulating layer (11). The heat-dissipating plate (12) has a first surface opposite to the insulating layer (12), the first surface being exposed from the molding resin (4). The insulating layer (11) has a curved area (11a) that is curved to the first surface and an end that is located in the molding resin (4).Type: GrantFiled: February 3, 2014Date of Patent: May 2, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Zyunya Tanaka
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Patent number: 9437508Abstract: In a method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 2(A), a case (2) including a first terminal (1) is placed on a working table (3) with an opening (30) formed at the bottom of the case (2). Subsequently, as shown in FIG. 2(B), a plurality of packages (6,6,6) including second terminals (4) are placed on the working table (3) through the opening (30) of the case (2), forming a clearance (31) between the first terminal (1) and the second terminal (4). As shown in FIG. 2(C), a bonding material (7) is disposed in the clearance (31) so as to electrically connect the first terminal (1) and the second terminal (4). Thus, the exposed surfaces of the packages (6,6,6) in the opening (30) of the case (2) are aligned at the same height, thereby reducing variations in thermal resistance among the packages (6,6,6).Type: GrantFiled: March 6, 2013Date of Patent: September 6, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Zyunya Tanaka, Masanori Minamio
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Publication number: 20150371921Abstract: A semiconductor device of the present invention includes: a first substrate (1) on which a power semiconductor element (2) is mounted; a heat-dissipating plate (12); an insulating layer (11) disposed between the first substrate (1) and the heat-dissipating plate (12); and molding resin (4) that molds the first substrate (1), the heat-dissipating plate (12), and the insulating layer (11). The heat-dissipating plate (12) has a first surface opposite to the insulating layer (12), the first surface being exposed from the molding resin (4). The insulating layer (11) has a curved area (11a) that is curved to the first surface and an end that is located in the molding resin (4).Type: ApplicationFiled: February 3, 2014Publication date: December 24, 2015Inventor: Zyunya TANAKA
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Patent number: 9136193Abstract: A semiconductor device includes a package 1, a block-module 2, and a control board 3 for controlling power semiconductor elements 11a. The block-module 2 has embedded power semiconductor elements 11a and second leads 4b and first leads 4a that are drawn from the block-module 2. The package 1 has external connection terminals 6a in contact with the first leads 4a of the block-module 2. The second leads 4b are connected to the control board 3 while the first leads 4a are joined to the external connection terminals 6a.Type: GrantFiled: December 10, 2012Date of Patent: September 15, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Masanori Minamio, Zyunya Tanaka
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Patent number: 8987877Abstract: A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package.Type: GrantFiled: May 16, 2014Date of Patent: March 24, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Masanori Minamio, Zyunya Tanaka, Shin-ichi Ijima
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Publication number: 20150035132Abstract: In a method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 2(A), a case (2) including a first terminal (1) is placed on a working table (3) with an opening (30) formed at the bottom of the case (2). Subsequently, as shown in FIG. 2(B), a plurality of packages (6,6,6) including second terminals (4) are placed on the working table (3) through the opening (30) of the case (2), forming a clearance (31) between the first terminal (1) and the second terminal (4). As shown in FIG. 2(C), a bonding material (7) is disposed in the clearance (31) so as to electrically connect the first terminal (1) and the second terminal (4). Thus, the exposed surfaces of the packages (6,6,6) in the opening (30) of the case (2) are aligned at the same height, thereby reducing variations in thermal resistance among the packages (6,6,6).Type: ApplicationFiled: March 6, 2013Publication date: February 5, 2015Inventors: Zyunya Tanaka, Masanori Minamio
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Publication number: 20140299982Abstract: A semiconductor device includes a package 1, a block-module 2, and a control board 3 for controlling power semiconductor elements 11a. The block-module 2 has embedded power semiconductor elements 11a and second leads 4b and first leads 4a that are drawn from the block-module 2. The package 1 has external connection terminals 6a in contact with the first leads 4a of the block-module 2. The second leads 4b are connected to the control board 3 while the first leads 4a are joined to the external connection terminals 6a.Type: ApplicationFiled: December 10, 2012Publication date: October 9, 2014Applicant: Panasonic CorporationInventors: Masanori Minamio, Zyunya Tanaka
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Publication number: 20140264801Abstract: A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package.Type: ApplicationFiled: May 16, 2014Publication date: September 18, 2014Applicant: Panasonic CorporationInventors: Masanori MINAMIO, Zyunya TANAKA, Shin-ichi IJIMA
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Patent number: 8754510Abstract: A conduction path includes a first conduction path forming plate (11) made of a first metal and having a through hole (13), and a second conduction path forming plate (15) made of a second metal and having a press-fit portion (17) press-fitted into the through hole. A wall surface of the through hole and a side surface of the press-fit portion forms an inclined bonding surface (18) inclined relative to a normal line of an overlap surface of the first conduction path forming plate and the second conduction path forming plate, and a bonding portion (25) formed by metal flow is formed in a region located in a periphery of the inclined bonding surface.Type: GrantFiled: November 30, 2011Date of Patent: June 17, 2014Assignee: Panasonic CorporationInventors: Masanori Minamio, Zyunya Tanaka, Ryoutarou Imura
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Publication number: 20130015567Abstract: A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package.Type: ApplicationFiled: October 20, 2010Publication date: January 17, 2013Applicant: PANASONIC CORPORATIONInventors: Masanori Minamio, Zyunya Tanaka, Shin-ichi Ijima
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Publication number: 20120299166Abstract: A conduction path includes a first conduction path forming plate (11) made of a first metal and having a through hole (13), and a second conduction path forming plate (15) made of a second metal and having a press-fit portion (17) press-fitted into the through hole. A wall surface of the through hole and a side surface of the press-fit portion forms an inclined bonding surface (18) inclined relative to a normal line of an overlap surface of the first conduction path forming plate and the second conduction path forming plate, and a bonding portion (25) formed by metal flow is formed in a region located in a periphery of the inclined bonding surface.Type: ApplicationFiled: November 30, 2011Publication date: November 29, 2012Inventors: Masanori Minamio, Zyunya Tanaka, Ryoutarou Imura