Power amplifier system having amplifier failure compensation

Abstract

In accordance with one aspect of the present invention, a power amplifier system is provided for amplifying an RF input signal. The system includes a signal modulator that receives and modifies an input signal and provides therefrom a modified input signal. The system further includes a plurality of M sub-power amplifiers connected together in parallel with each receiving and amplifying a portion of the modified input signal. A combiner combines the amplified portions to provide a combined output signal. A power detector receives the combined output signal and provides therefrom an average output power signal representative of the average output power thereof. A controller monitors the operation of the M sub-power amplifiers to determine if any have failed and adjusts the magnitude of the output power signal to compensate for any failure. The controller controls the modulator in accordance with a function of the magnitude of the output power signal.

Description

RELATED APPLICATION

[0001] This is a continuation-in-part of our co-pending U.S. patent application Ser. No. 09/137,643, which was filed on Aug. 19, 1998.

TECHNICAL FIELD

[0002] The present invention is generally directed to an RF power amplifier system with an automatic gain control for use in amplifying an RF input signal and is more particularly directed toward amplifier failure compensation.

BACKGROUND OF THE INVENTION

[0003] RF power amplifier systems are known in the art for use in amplifying RF signals for broadcasting purposes, including radio and television. Such power amplifiers may be employed in the broadcasting of either analog television signals, known as the NTSC, PAL, SECAM format, or digital signals, sometimes known as DTV format. When employed in television broadcasting, the frequency bandwidth for the television signals is 6 MHz. The television channels will be in the UHF signal range from approximately 470 to 860 MHz.

[0004] The RF input signal to such a power amplifier is obtained from an RF exciter and, for example, this may take the form of a modulated RF carrier within a frequency band of 470 to 860 MHz with the bandwidth of any one channel being on the order of 6 MHz. This RF input signal may have a magnitude on the order of 20 milliwatts. This input signal is increased in magnitude to a much higher level such as on the order of 400 watts which represents a gain on the order of 43 dB.

[0005] These power amplifier systems are expected in many situations to be constantly operating so that a radio or television station employing such a power amplifier system may continuously broadcast.

[0006] Broad band RF power amplifiers are often required to have a flat gain over the specified frequency range. Usually, an automatic gain control (AGC) closed-loop system is used to control the gain of an amplifier. Most AGC closed-loop controllers are analog, however, the AGC can be digital by using a microprocessor for complex algorithms. A proportional integral derivative (PID) algorithm based AGC closed-loop controller can be used to control the gain of a power amplifier. A PID controller for AGC, which includes both analog and digital components, can automatically adjust the gain, compensating for the variations caused by the temperature changes or a power supply voltage change. It has been widely used in industrial control.

[0007] The regular closed-loop AGC control system of a RF power amplifier operating at nominal frequency can be described in the block diagram of FIG. 10 and Equation A. 1 P out ⁡ ( j ⁢   ⁢ ω ) P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) 1 + G O · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) Equation ⁢   ⁢ A

[0008] The ideal RF sensor characteristics are:

Vin=GI*Pin  Expression (1)

Vout=GO*Pout  Expression (2)

[0009] Here,

[0010] &ohgr;: Frequency (&ohgr;=2&pgr;f)

[0011] Pin(j&ohgr;): Input power signal at nominal frequency

[0012] Pout=(j&ohgr;): Output power signal from amplifier 602 at nominal frequency

[0013] Vin: Voltage signal from input power sensor 600 at nominal frequency

[0014] Vout: Voltage signal from output power sensor 620 at nominal frequency

[0015] GI=GI(j&ohgr;N): Transfer Function of input power sensor at nominal frequency

[0016] GO=GO(j&ohgr;N): Transfer Function of output power sensor at nominal frequency

[0017] GC(j&ohgr;): Transfer function of PID controller

[0018] GP(j&ohgr;): Transfer function for plant (controlled object)

[0019] &ohgr;N: Nominal frequency

[0020] The amplifier itself can contain several sub-amplifiers, which work in parallel. The failure of one of them changes the overall gain. A simple AGC controller would restore the gain level by increasing the RF drive level. That would overdrive the working sub-amplifiers and sacrifice the overall performance. The degradation in performance can not be adjusted nor compensated by the AGC, since the amplifier is driven into a non-linear working region.

[0021] A cancellation technique can be used to correct gain variations by correcting for variations caused by sub-amplifier failure.

SUMMARY OF THE INVENTION

[0022] In accordance with one aspect of the present invention, a power amplifier system is provided for amplifying an RF input signal. The system includes a signal modulator that receives and modifies an input signal and provides therefrom a modified input signal. The system further includes a plurality of M sub-power amplifiers connected together in parallel with each receiving and amplifying a portion of the modified input signal. A combiner combines the amplified portions to provide a combined output signal. A power detector receives the combined output signal and provides therefrom an average output power signal representative of the average output power thereof. A controller monitors the operation of the M sub-power amplifiers to determine if any have failed and adjusts the magnitude of the output power signal to compensate for any failure. The controller controls the modulator in accordance with a function of the magnitude of the output power signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The foregoing and other advantages of the invention will become more readily apparent from the following description of the preferred embodiment of the invention as taken in conjunction with the accompanying drawings, which are a part hereof, and wherein:

[0024] FIG. 1 is a schematic-block diagram illustration of apparatus employed in one embodiment of the invention;

[0025] FIG. 2 is a block diagram of a detector in accordance with the invention;

[0026] FIG. 3 is a schematic-block diagram of an integrator in accordance with the invention;

[0027] FIG. 4 is a flow diagram of one routine involved in the invention;

[0028] FIG. 5 is a flow diagram of another routine involved in the invention;

[0029] FIG. 6 is a flow diagram of another routine involved in the invention;

[0030] FIG. 7 is a flow diagram of another routine involved in the invention;

[0031] FIG. 8 is a flow diagram of another routine involved in the invention;

[0032] FIG. 9 is a flow diagram of another routine involved in the invention;

[0033] FIG. 10 is a block diagram of a prior art closed-loop automatic gain control (AGC) control system for a power amplifier;

[0034] FIG. 11 is a block diagram similar to that of FIG. 10, but illustrating the manner in which the closed-loop gain is affected by the frequency dependent characteristics of sensors 600 and 620;

[0035] FIG. 12 is a block diagram based on FIG. 1 herein showing frequency compensation for the input power sensor 60 as well as for the output power sensor 62;

[0036] FIG. 13 is a flow diagram of another routine involved in the invention;

[0037] FIG. 14 is a flow diagram of another routine involved in the invention;

[0038] FIG. 15 is a block diagram of a prior art amplifier system similar to that as shown in FIG. 10, but additionally illustrating power reduction factor F1 caused by the failure of one or more sub-amplifiers;

[0039] FIG. 16 is a block diagram based on the block diagram herein of FIG. 1 and illustrating that the power amplifier which is comprised of a plurality of parallel sub-power amplifiers PA-1 to PA-M and exhibits a power reduction factor F1; and,

[0040] FIG. 17 is a block diagram similar to that of FIG. 16 but showing both frequency compensation and sub-power amplifier compensation.

DESCRIPTION OF A PREFERRED EMBODIMENT

[0041] Reference is now made to FIG. 1 which illustrates a power amplifier system which receives a modulated RF input signal at an input terminal 10 and amplifies the signal and supplies it to a load L, which may take the form of a transmitting antenna and associated equipment. As an example only, the RF input signal may have a magnitude on the order of 20 milliwatts and have a frequency within the UHF frequency range between 470 and 860 MHz with a 6 MHz bandwidth for the television channel involved. The signal may be increased by the amplifier with a gain on the order of 43 dB so that the output signal as applied to the load L may be on the order of 400 watts.

[0042] The RF input signal is applied to the input terminal 10 and, thence, to a vector modulator. The vector modulator changes the magnitude and the phase of the RF signal. The vector modulator is controlled by the vector signals IVECTOR and QVECTOR 90 and 91, which are generated by a microcontroller MC. The modified RF signal from the vector modulator is then amplified by a driver DR to a higher level, such as 20 watts. The output, as taken from the driver DR, is then supplied to a power divider DV, sometimes referred to as a signal or power splitter, which divides the amplified signal by a factor of M. M signals are then applied to M sub-power amplifiers PA-1 through PA-M, where M, for example, may be 12. The signals from the sub-power amplifiers PA-1 through PA-M are then combined in a signal combiner CB to provide an output signal which is applied to the load L.

[0043] The input signal is applied to a vector modulator 16 when the RF input switch 20 is closed. The RF switch 20 is controlled by a microcontroller MC, as will be explained in greater detail hereinafter.

[0044] The driver DR amplifies the signal with a gain of approximately 14 dB to deliver an RF signal of approximately 20 watts to a divider DV. This divider serves as a power splitter and splits the applied RF signal into N portions. The divider applies N equal portions of the RF signal to respective sub-power amplifiers PA-1 through PA-M. Each sub-power amplifier may include a field effect transistor having its drain electrode connected through a suitable resistor, such as resistor R1 or R2 or RM, to a DC switch 40. When this switch is closed, it connects each drain electrode with a DC voltage source VDD. This voltage source may, for example, be on the order of 32 volts.

[0045] The outputs from the power amplifiers PA-1 through PA-M are combined at the power combiner CB. The output signal at the output circuit 50 is on the order of 400 watts.

[0046] The microcontroller MC, together with input power detector 60, output power detector 62 and vector modulator 16, and driver DR, DV, and power amplifier PA-1 to PA-M and combiner CB, forms a closed-loop control system. The microcontroller MC uses proportional-integral-derivative algorithm based automatic gain control to adjust the gain of the power amplifier. Also, the microcontroller MC will adjust the phase of the output power based on the phase reference from external source. The vector signals IVECTOR and QVECTOR 90 and 91, generated through the procedure FIG. 9B, control vector modulator 16, which thereafter controls the magnitude and phase of the output power of the power amplifier.

[0047] The microcontroller MC monitors the operation of the amplifier system and controls the operation of the RF switch 20 and the DC switch 40.

[0048] When the DC switch 40 is closed, current will flow in the power amplifiers PA-1 through PA-M. This current will flow through the associated resistors R1 through Rm. A voltage is developed across each resistor. These voltages are supplied as current samples to the microprocessor MC which then determines whether the current levels are too high or too low and takes appropriate action. Also, when the switch 40 is closed current flows through resistor R0 and the driver DR. The voltage developed across this resistor is also supplied to the microcontroller MC for analysis.

[0049] In addition to monitoring the current flowing through the various power amplifiers, the microcontroller also monitors peak and average power levels with the use of power detectors. These detectors include an input power detector 60 and output power detectors 62 and 64. The power detector 60 is connected to an input signal divider 70 and serves to provide DC output signals VP1 and VA1 respectively representative of the input peak power and the input average power. The signal representative of the input peak power VP1 is compared with a reference VR1 at comparator 72. If the peak power VP1 exceeds the reference then an interrupt signal is supplied to the microprocessor MC which interrupts the routine being processed and enters a fault process to turn the power amplifier system off.

[0050] Detector 62 is connected to a incident signal coupler 80 coupled to the output transmission line 50. This detector 62 provides a DC voltage signal VP2 representative of the peak output power as well as a DC voltage VA2 which represents the average output power in the forward direction at the output transmission line 50. Signal VP2 is compared with a reference VR2 at comparator 74. If signal VP2 exceeds reference VR2 then an interrupt signal is supplied to microcontroller MC which then enters a fault process routine to turn the power amplifier off.

[0051] A coupler 82 is employed for sensing the reflected power and this coupler is connected to detector 64. This detector 64 serves to provide DC voltage signals including a signal VP3 representative of the peak reflected power and VA3 representative of the average reflected power. If signal VP3 exceeds a reference VR3, then comparator 76 applies an interrupt signal to the microcontroller MC which then enters a fault process routine to turn the power amplifier off. The monitored average power signals VA1, VA2 and VA3 are supplied to the microcontroller MC which uses PID based automatic gain control to vary the gain and/or phase of the RF signal as needed.

Power Detector

[0052] Each of the power detectors is constructed in the same fashion as detector 60 which is described in detail with reference to FIG. 2. This detector includes an envelope demodulator 61 which receives a sample of an RF signal from correspondingly input or output transmission lines. The carrier signal may, for example, be on the order of 600 MHz and the baseband for the television signal has a bandwidth of 6 MHz. The demodulator 61 effectively strips off the carrier signal (600 MHz) leaving only the demodulated baseband signal. This signal may be viewed as an analog positive signal and which is applied to the integrator 63 and a peak power detector 65.

[0053] The integrator 63 provides an output signal in the form of voltage VA1 representative of the average input power whereas the peak detector 65 provides an output signal in the form of a voltage VP1 representative of the peak input power. The demodulator 61 and the integrator 63 form an RMS detector.

Integrator

[0054] The integrator 63 located in each of the detectors 60, 62 and 64 may take the form as illustrated in FIG. 3 to be described below.

[0055] As will be recalled, the digital 8-VSB format refers to an 8 level vestigial sideband signal. The baseband of this signal is 6 MHz wide. It is desired to provide efficient power level control of the power amplifier system illustrated in FIG. 1. To achieve this, it is desirous to provide a power detector that provides an output signal, Vout, which is proportional to the corresponding average power. In the past, circuit designers have typically employed true RMS detectors for converting an input baseband signal into a DC level proportional to the RMS power. This is done in accordance with the equation noted below. 2 V RMS = ∫ T ⁢ V m 2 ⁢   ⁢ ⅆ t T

[0056] A significant problem in a power amplifier system as shown in FIG. 1 is the complexity and expense of the circuitry to perform the above equation. At present, commercially available integrated circuits that perform this type of an equation are only suitable for use at low frequencies, such as up to 10 kHz. As such, they are not able to provide an RMS signal representative of a baseband signal that is of a substantially higher frequency, such as being 6 MHz wide as in the case of digital television signals. There is a need to provide a circuit that will deliver an output voltage Vout which is proportional to the RMS value of the input voltage Vin without employing multiplication (such as Vin times Vin to obtain Vin2). This is achieved with the circuit shown in FIG. 3 as described below.

[0057] The input voltage Vin is applied to an input terminal 100 and the output voltage Vout is obtained at an output terminal 102. A wideband operational amplifier 104 is provided having an RC charge path connected to its positive or non-inverting input 106 and an RC discharge path is connected to its inverting or negative input 108. The charge path includes a resistor R1 and a capacitor C1 having their junction point connected to input 106 of amplifier 104. The other side of capacitor C1 is connected to circuit ground. The discharge path includes a resistor R2 and a capacitor C2 having their junction point connected to input 108 of the operational amplifier 104. The other side of capacitor C2 is connected to circuit ground. A diode D1 is connected between the output 105 of amplifier 104 and the circuit output 102. The circuit output 102 is connected to the negative input 108 of the amplifier 104 by way of a circuit path 110.

[0058] The circuit in FIG. 3 has separate RC circuits that define the charge and discharge time constants and thereby provides independently controlled charge and discharge times. The circuit may be tuned by changing the value of resistors R1 and R2 so that the ratio of the charge and discharge time constants allows the detector to deliver an output voltage Vout proportional to the RMS value of Vin. The manner of operation involved is presented below.

[0059] Consider a situation wherein the diode D1 is connected between output 105 and circuit output 102 and that R2*C2≧R1*C1.

[0060] In this situation, the voltages Vout and V− will follow voltage V+ as voltage V+ increases. The moment voltage V+ decreases, voltage Vout follows the discharge time R2*C2 until V+ increases again and the operation repeats. Since voltage V+ follows voltage Vin with a charge time constant R1*C1, then voltage Vout follows voltage Vin with the C1*R1 time constant on the rise and the C2*R2 time constant on the voltage Vin fall.

[0061] When the R2*C2 time constant is long enough 3 ( 1 C2 * R2 < f low

[0062] where flow is the lowest frequency in the spectrum of the envelope demodulated signal) this allows creation of the voltage Vout anywhere in the range from voltage Vin max. to voltage Vin average by manipulating the C1*R1 time constant from C1*R1=0 to C1*R1=C2*R2.

[0063] If the diode D1 is replaced by diode D2 (as shown by the broken line) the condition R1*C1≧R2*C2 results. If R1*C1 is long enough 4 ( 1 C1 * R1 < f low )

[0064] then this allows creation of voltage Vout anywhere in the range from Vin average to Vin minimum, varying C2*R2 from=C1*R1 to zero.

[0065] In the power amplifier system of FIG. 1, it is contemplated that an 8-VSB baseband signal is involved. It's spectrum looks like white noise with a frequency range from 0 to 6 MHz and almost even distribution of power within the range. The goal is to tune the ratio of charge and discharge time constants for the detector to deliver voltage Vout proportional to the RMS value of voltage Vin without going through a multiplication (Vin*Vin), which would require circuit complication.

[0066] This is achieved by referencing voltage Vout originated by 8-VSB modulated RF to voltage Vout originated by CW. Since the modulation baseband of the nonmodulated (CW)RF signal is equal to zero, voltage Vin is a DC voltage. The RMS value for the DC voltage is equal to the voltage itself. Applied as voltage Vin, it will appear as Vout=Vin on the output of the detector. The level of this voltage Vout can be used as a reference of RMS voltage for a given average power of RF and, after switching from CW to 8-VSB signal with the same average power level, tune the time constants so that the voltage Vout shows the same value.

[0067] The way to tune the time constants is to adjust the values of resistors R1 and R2 to achieve a certain voltage Vout. Thus, the RMS detector delivers true RMS value for two kinds of RF modulations: CW (no modulation) and 8-VSB.

[0068] Another explanation that may be employed for understanding the circuitry of FIG. 3 is now presented. A non-modulated continuous wave (CW) signal of a known power level Pr may be applied to the RF input terminal 10 (see FIG. 1). The value of voltage Vout is observed. The continuous wave may then be replaced with an 8-VSB source of the same known power level Pr. Again, the output voltage Vout is observed. Since the input power levels were the same Pr, the value of voltage Vout should be the same for both cases. If it is not the same, then the values of resistor R1 and R2 in the charge and discharge paths, are varied to change the ratio of the charge and discharge time constants. Once the output voltages are the same then the values of the resistors are fixed and thus they have been optimized to achieve the same voltage Vout for both CW and 8-VSB baseband signals.

Flow Diagrams

[0069] Reference is now made to the flow diagrams of FIG. 4 through FIG. 9 which illustrate the manner in which the microcontroller MC is programmed to accomplish various functions herein.

[0070] Attention is specifically directed to FIG. 4 which illustrates the flow diagram for the fault process routine 200 which is employed for turning off the power amplifier when a fault condition has been determined. In step 202, a “module off” indication has been made because a condition (to be discussed in greater detail hereinafter) has been determined to be a fault and the module (i.e. the power amplifier of FIG. 1) is to be turned off. This may be accomplished by the microcontroller MC controlling the RF switch 20 and the DC switch 40 by opening the switches and by adjusting the modulator 16 for minimum gain.

[0071] The procedure then steps to a three-strike process 204 during which the power amplifier is turned on and the conditions are again monitored to determine if there is a fault condition. In this case, the power amplifier is turned on up to three times over a 10 second interval to determine whether the fault condition is still present.

[0072] Thereafter, the procedure advances to step 206 which determines whether the power amplifier has been successfully turned on during the three-strike process. If it has been successful, then the procedure advances to step 209 and continues monitoring. If the attempt to restart the power amplifier is not successful, then the procedure advances to step 208 during which the power amplifier is shut down and not restarted. This shut down procedure involves the microcontroller commanding the RF switch 20 to open and commanding the DC switch 40 to open as well as turning down the gain of the vector modulator 16.

[0073] Reference is now made to FIG. 5 which illustrates an emergency process routine 250 which is employed by the microcontroller in the event that emergency level faults have been detected. This routine includes step 252 during which the microcontroller responds to an interrupt signal received from one of the peak power comparators 72, 74 or 76 to interrupt the microcontroller and enter into the fault process routine 200, described above with reference to FIG. 4, for purposes of turning off the power amplifier module of FIG. 1. As will be recalled, comparator 72 provides such an interrupt signal when the input peak power signal VP1 is greater than a reference signal VR1. Similarly, comparator 74 provides such an interrupt signal when the output forward peak power signal VP2 exceeds a reference VR2. Also comparator 76 provides such an interrupt signal when the reflected peak power signal VP3 exceeds a reference VR3 (representative of a VSWR excessive condition).

[0074] Reference is now made to FIG. 6 which illustrates a fast monitor process routine 300. In this routine, a determination is made at step 302 as to whether any of the pallets or sub-power amplifiers PA-1 through PA-M have an overloaded current condition. If so, then the procedure advances to the fault process 200 (see FIG. 4). If not, the procedure advances to step 304.

[0075] Before proceeding with step 304 attention is now directed to FIG. 7 which illustrates a routine for determining whether one of the sub-power amplifiers PA-1 through PA-M has an over-current condition. This routine commences with a start step 303 and, in the monitoring operation, a current sample IS1 representative of the current flowing in the sub-power amplifier PA-1 is obtained in step 305. In step 307, the current sample IS1 is compared with a reference sample IH representative of a high level of acceptance. If the current sample exceeds this high level, the procedure advances to the fault process 200 discussed hereinbefore with reference to FIG. 4. This type of routine may be practiced for monitoring each of the sub-power amplifiers PA-1 through PA-M.

[0076] Attention is again directed to routine 300 in FIG. 6. If none of the power amplifiers are current overloaded, as determined in step 302, the procedure advances to step 304 wherein a determination is made as to whether the input power is overloaded. In this step, a signal representative of the average input power is signal VA, and this is compared with a reference of an acceptable level in the microcontroller MC. If an overload condition is determined, the procedure advances to the fault process 200.

[0077] If the input power is not overloaded, the procedure advances to step 308 at which a determination is made as to whether the output power is overloaded. This is accomplished by comparing the signal VA2, representative of the average output power, with an acceptable reference level. If signal VA2 exceeds the reference level, the procedure advances to the fault process routine 200. If not, then the procedure advances to step 310.

[0078] In step 310 a determination is made as to whether the reflected power is overloaded. This is determined by comparing the average reflected power signal VA3 with a reference level and if the reflected power is overloaded, the procedure advances to the fault process routine 200.

[0079] Reference is now made to FIG. 8 which illustrates a slow monitor process routine 350. In this routine, a determination is made at step 352 as to whether the DC voltage (VDD) is too high. This is accomplished by comparing the voltage with a reference level. If the voltage VDD is too high, the procedure advances to the fault process 200. If not, the procedure advances to step 354.

[0080] In step 354, a determination is made as to whether the heat sink temperature is too high. This is obtained by comparing a signal representative of the heat sink temperature from a suitable source 81 with a reference. If the heat sink is overloaded, the procedure advances to the fault process routine 200. Otherwise, the procedure advances to step 356.

[0081] In step 356, a determination is made as to whether there has been an automatic gain control failure (AGC failure). If so, the procedure advances to the fault process routine 200. Otherwise, the monitoring operation continues.

[0082] Reference is now made to FIG. 9 which illustrates the automatic gain control (AGC) routine 400. This procedure includes step 401 during which the average sub-PA current Iave. is determined for each sub-PA; that is determine the value of Ii for from i=1 to i=M and then divide the sum by M, the total number of Sub-PA. The procedure then advances to step 403.

[0083] In step 403, a determination is made as to how many of the sub-PA (PA-1 through PA-M) failed. This is done by determining if the current Ii at each sub power amplifier is equal to or less than I0, where I0 is a threshold for “zero” current and is set to a value on the order of 10% to 20% of Iave. Step 403 then sets K to the number of failed sub-PAs. The procedure then advances to step 405.

[0084] In step 405, a determination is made as to whether K exceeds X, where X is the maximum allowed number of failed sub-PAs. If “yes”, the procedure advances to the fault process step 200. If the determination at step 405 is “no”, the procedure advances to step 407.

[0085] In step 407, the value of the output power signal Pout(N) is re-calculated by multiplying the measured value of the output power signal by the factor of 5 [ M M - K ] 2 .

[0086] The procedure then advances to step 408.

[0087] In step 408, the control output signal variation &Dgr;V is generated as presented in the block bearing the label 408.

[0088] The procedure then advances to step 410 at which a determination is made as to whether the absolute value of &Dgr;V is greater than &Dgr;MAX (i.e. is |&Dgr;V|>&Dgr;MAX). If so, the absolute value of &Dgr;V (i.e. |&Dgr;V|) is made equal to the value of &Dgr;MAX in step 412.

[0089] The procedure then advances to step 414 wherein the magnitude of the control voltage vector VM is updated so that it is equal to VM+&Dgr;V.

[0090] The procedure then advances to step 416 wherein a check is made that the control voltage vector VM is greater than 0 but is less than the full scale value of VM which is used herein as VMF.

[0091] The procedure then advances to step 418 wherein the microcomputer reads the phase signals which are referred to as &phgr;, and &phgr;2 from the external source (FIG. 1). These signals are used in the following. The procedure advances to step 420 wherein a determination is made that &phgr; is greater than 0 but less than 6 π 2 ⁢   ⁢ ( i . e .   ⁢ 0 < φ < π 2 ) .

[0092] The procedure then advances to step 422 wherein the vectors to be supplied to the vector modulator 16 are generated. This includes the Ivector which is equal to VM cos &phgr; and the Qvector which is equal to VM sin &phgr;.

[0093] The procedure now advances to step 424 wherein the Ivector and the Qvector are supplied to the vector modulator 16 to vary the phase and gain of the signal being processed by the vector modulator 16.

[0094] Thereafter, the procedure advances to step 426 during which a suitable time, such as 20 milliseconds, is waited. Then, the procedure advances to step 428 during which a determination is made as to whether or not the AGC control has failed. If so, the procedure advances to the fault process procedure 200 (see FIG. 4).

Cancellation of the frequency response

[0095] To maintain the gain of the power amplifier constant at different operational frequencies, the cancellation technique employs compensation factors to correct the input and output power, then the PID AGC algorithm will use corrected data to generate control signals.

[0096] The closed-loop AGC control system, without using the cancellation technique for input and output power sensors can be described by the block diagram FIG. 11 and Equation B. Thus, the system closed-loop gain will be affected by the frequency characteristics of the sensors. 7 P out ⁡ ( j ⁢   ⁢ ω ) P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) ( 1 + G O · G out ⁡ ( j ⁢   ⁢ ω ) · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) ) Equation ⁢   ⁢ B

[0097] The real RF sensor characteristics are:

Vin(j&ohgr;)=Gin(j&ohgr;)*GI*Pin  Expression (3)

Vout(j&ohgr;)=Gout(j&ohgr;)*GO*Pout  Expression (4)

[0098] Here,

[0099]

[0100] Pin(j&ohgr;): Input power signal as a function of frequency

[0101] Pout(j&ohgr;): Output power signal as a function of frequency

[0102] GI=GI(j&ohgr;N): Transfer Function of input power sensor at nominal frequency

[0103] GO=GO(j&ohgr;N): Transfer Function of output power sensor at nominal frequency

[0104] Gin(j&ohgr;): Gain factor of input power sensor due to frequency-dependency

[0105] Gout(j&ohgr;): Gain factor of output power sensor due to frequency-dependency

[0106] GI*Gin(j&ohgr;): Transfer Function of input power sensor with frequency-dependence

[0107] GO*Gout(j&ohgr;): Transfer Function of output power sensor with frequency-dependence

[0108] Vin(j&ohgr;): Voltage signal from input power sensor with frequency-dependence

[0109] Vout(j&ohgr;): Voltage signal from output power sensor with frequency-dependence

[0110] Since Equations A and B are different closed-loop transfer functions, a regular PID algorithm based AGC controller can not generate the same gain for the RF amplifier if it is operated at any frequency other than nominal frequency.

[0111] The closed-loop AGC control system using the cancellation technique for input and output power sensors can be described in the block diagram of FIG. 12 and Equation C. 8 P out ⁡ ( j ⁢   ⁢ ω ) P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) · F i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) ( 1 + G O · G out ⁡ ( j ⁢   ⁢ ω ) · F out ⁡ ( j ⁢   ⁢ ω ) · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) ) Equation ⁢   ⁢ C

[0112] After compensation, the signals will be:

V′in(j&ohgr;)=Fin(j&ohgr;)*Vin(j&ohgr;)=Fin(j&ohgr;)*Gin(j&ohgr;)*GI*Pin  Expression (5)

V′out(j&ohgr;)=Fout(j&ohgr;)*Vout(j&ohgr;)=Fout(j&ohgr;)*Gout(j&ohgr;)*GO*Pout  Expression (6)

[0113] Here,

[0114]

[0115] Gin(j&ohgr;): Gain factor of input power sensor due to frequency-dependency

[0116] Gout(j&ohgr;): Gain factor of output power sensor due to frequency-dependency

[0117] GI=GI(j&ohgr;N): Transfer Function of input power sensor at nominal frequency

[0118] GO=GO(j&ohgr;N): Transfer Function of output power sensor at nominal frequency

[0119] Fin(j&ohgr;): Compensation factor function for input power sensor

[0120] Fout(j&ohgr;): Compensation factor function for output power

[0121] Pin=Pin(j&ohgr;N): Input power signal at nominal frequency

[0122] Pout=Pout(j&ohgr;N): Output power signal at nominal frequency

[0123] Vin=Vin(j&ohgr;N): Voltage signal from input power sensor at nominal frequency

[0124] V′in(j&ohgr;): Corrected voltage signal from input power sensor

[0125] Vout=Vout(j&ohgr;N): Voltage signal from output power sensor at nominal frequency

[0126] V′out(j&ohgr;): Corrected voltage signal from output power sensor

[0127] &ohgr;N: Nominal frequency

[0128]

[0129] If,

Fin(j&ohgr;)*Gin(j&ohgr;)=1  Expression (7)

Fout(j&ohgr;)*Gout(j&ohgr;)=1  Expression (8)

[0130] Then,

V′in(j&ohgr;)=Fin(j&ohgr;)*Vin(j&ohgr;)=Fin(j&ohgr;)*Gin(j&ohgr;)*GI*Pin=GI*Pin=Vin  Expression (9)

V′out(j&ohgr;)=Fout(j&ohgr;)*Vout(j&ohgr;)=Fout(j&ohgr;)*Gout(j&ohgr;)*GO*Pout=GO*Pout=Vout  Expression (10)

[0131] Expressions 9 and 10 mean that any variations in the RF sensors' output due to frequency dependency will be canceled by a compensation factor function. After cancellation, the RF sensors seem working at nominal frequency all the time. Thus the RF sensors will be frequency-independent within the specified frequency range, this means the PID AGC algorithm and the RF power sensors can be used in a broad bandwidth.

[0132] From Expressions 7 and 8, the following conclusions can be drawn:

Fin(j&ohgr;)=1/Gin(j&ohgr;)   Expression (11)

Fout(j&ohgr;)=1/Gout(j&ohgr;)   Expression (12)

[0133] The inverse of the transfer function of the RF sensors is the compensation factors for the cancellation of the variation of input and output power caused by the sensors.

[0134] Thus, after cancellation Equation C can be rearranged as follows: 9 P out ⁡ ( j ⁢   ⁢ ω ) P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) 1 + G O · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) Equation ⁢   ⁢ C ′

[0135] This equation Equation C|is identical to equation A. This means the compensated system operating at any given frequency will have the same closed-loop transfer function as a system operating at nominal frequency and these two systems will have the same gain under Automatic Gain Control.

[0136] In practice, the RF power amplifier will operate at a fixed frequency &ohgr;0 or f0 the operational frequency is set. Thus Expressions 7 and 8 can be modified as:

Fin(j&ohgr;0)=1/Gin(j&ohgr;)  Expression (13)

Fout(j&ohgr;0)=1/Gout(j&ohgr;0)  Expression (14)

[0137] The characteristics of frequency response of RF sensors, Gin(j&ohgr;) and Gout(j&ohgr;), can be obtained through measurement. Since the frequency response of the RF sensors can not be described by simple closed-form formula they are presented in the format of data look-up table. Also, since the look-up table has non-continued discrete data points, an interpolation algorithm will be used to generate the correct factor at the exact frequency, even it may not be obtained directly from look-up table. Once the look-up tables of response vs. frequency are obtained, for any given frequency, the variation caused by the frequency dependency of the RF sensor can be compensated using this technique. Since the look-up tables are stored in non-volatile memory, they can be used to correct the frequency-dependent input power and output power sensors for any given operating frequency as long as the frequency is within the bandwidth.

Operating frequency set

[0138] To use the cancellation technique to compensate the frequency dependence of RF sensors, the operating frequency has to be set. The controller can use the cancellation technique to compensate the variation caused by the frequency via look-up table or equation. The operating frequency of the RF amplifier will be set via data communication from a PC or main controller to the micro-controller MC, in which a digital PID algorithm based AGC controller resides.

[0139] Once the operating frequency f0 or &ohgr;0 is set or updated, the micro-controller calculates the frequency compensation factor Fin(j&ohgr;0) and Fout(j&ohgr;0). The setting frequency f0 or &ohgr;0 is stored in non-volatile memory EEPROM. Every time the micro-controller restarts, the compensation factors Fin(j&ohgr;0) and Fout(j&ohgr;0) will be calculated at initialization time. During normal operation, the micro-controller uses the factors to compensate the input and output power for the iteration of the PID algorithm.

[0140] The microcontroller MC (FIG. 1) is also connected to a central or main controller CC by way of a serial bus that may take the form of a controller area network (CAN) serial bus. Additionally, the microcontroller MC could be connected by a serial communications network with a personal computer PC. The microcontroller is provided with memories including a EEPROM memory EM and a flash memory FM. These memories may be located externally of the microcontroller or internally thereof. The memory EM stores configuration information including the operational frequency f0 for the power amplifier PA. The changes to be made in the frequency may be supplied from either the main controller CC or from the personal computer PC to the controller MC which then stores the new operating frequency f0 in memory EM. The flash memory FM stores software codes as well as the look-up table LUT.

[0141] The look-up table LUT stores the frequency compensation correction factors employed for correcting the measured values of the input power signal PIN and output power POUT as measured by the detectors 60 and 62. These correction factors are employed in Equation C herein. An example of the look-up table is presented in Table 1 below. 1 TABLE 1 (Look-up table LUT) f(f = &ohgr;/2&pgr; MHz Gin(j&ohgr;) Fin (j&ohgr;) Gout(j&ohgr;) Fout(j&ohgr;) 470 0.9925 1.0075 0.9193 1.0878 480 0.9883 1.0118 0.9323 1.0726 490 0.9899 1.0102 0.9452 1.0580 500 0.9943 1.0057 0.9469 1.0560 510 1.0005 0.9995 0.9577 1.0442 520 1.0092 0.9909 0.9720 1.0288 530 1.0166 0.9837 0.9824 1.0179 540 1.0168 0.9835 0.9937 1.0063 550 1.0101 0.9900 1.0000 1.0000 560 1.0000 1.0000 0.9933 1.0012 570 0.9889 1.1122 0.9950 1.0050 580 0.9797 1.0207 0.9985 1.0015 590 0.9740 1.0267 1.0073 0.9928 600 0.9691 1.0319 1.0150 0.9852 610 0.9675 1.0334 1.0219 0.9786 620 0.9664 1.0348 1.0219 0.9786 630 0.9704 1.0305 1.0133 0.9869 640 0.9776 1.0229 1.0030 0.9970 650 0.9872 1.0130 0.9990 1.0010 660 1.0170 0.9833 0.9410 1.0627 670 1.0220 0.9785 0.9480 1.0548 680 1.0220 0.9785 0.9620 1.0395 690 1.0170 0.9833 0.9720 1.0288 700 1.0090 0.9911 0.9840 1.0163 710 1.0030 0.9970 0.9970 1.0030 720 0.9990 1.0010 1.0100 0.9900 730 0.9970 1.0030 1.0230 0.9775 740 0.9950 1.0050 1.0340 0.9671 750 0.9960 1.0040 1.0460 0.9560 760 0.9990 1.0010 1.0580 0.9452 770 1.0010 0.9990 1.0640 0.9398 780 1.0020 0.9980 1.0760 0.9294 790 0.9950 1.0050 1.0820 0.9242 800 0.9790 1.0215 1.0800 0.9259 810 0.9680 1.0331 1.0780 0.9276

[0142] It is noted that the look-up table LUT in Table 1 provides correction factors for frequencies in the frequency range from 470 MHz to 810 MHz. Additionally, the frequencies shown are increased in value by 10 MHz at each step. It is to be appreciated that such a look-up table may include several more frequencies. With the frequency correction factors for the frequencies shown, it will be appreciated that for any frequency located between those shown in the Table, the value of the correction factors may be obtained through an interpolation algorithm, common in the art.

[0143] Reference is now made to the frequency update process routine 500 illustrated in FIG. 13. This process includes a step 502 during which the microcontroller determines whether a frequency update has taken place through a serial communications port from either the main controller CC or from the personal computer PC. If not, the process loops back to make another determination. If the determination in step 502 is affirmative, then the process advances to step 504.

[0144] In step 504, a determination is made as to whether the new frequency is equal to the old frequency. If so, then the procedure loops back to step 502. If the determination at step 504 is that the new frequency is not equal to the old frequency, then the procedure advances to step 506.

[0145] In step 506, the procedure stores the new frequency f0 into the non-volatile memory (EEPROM) EM (FIG. 1). Based on the frequency f0 in the look-up table LUT and a suitable interpolation algorithm, if needed, the correction factors are obtained for the input power sensor 60 and the output power sensor 62 and then the procedure loops back to step 502.

[0146] Reference is now made to FIG. 14 which illustrates a power correction process routine 600. This routine includes step 602 wherein the input power signal Pin(N) is adjusted by multiplying the signal with the correction factor obtained from the look-up table (and further adjusted by interpolation if needed). Also, the output power signal Pout(N) is corrected in a similar fashion by obtaining the correction factor at the operating frequency f0. Now that the input and output power signals have been corrected to cancel the effects of frequency, the automatic gain control procedure at step 400 (FIG. 9A) is employed.

Cancellation of the failed sub-amplifier

[0147] For a power amplifier with many sub-amplifiers, the failure of some sub-amplifiers should not prevent the power amplifier from continuous operation and it should not prevent the AGC controller from working. Since the partial power loss of the power amplifier is a function of the number of failed sub-amplifiers, the total power reduction factor F1 can be calculated from the total number of sub-amplifiers and the number of failed sub-amplifiers, which could be realized based on the sub-amplifiers' working conditions. Also, the power reduction factor is determined by the power combined scheme, it may be different if a different combined scheme is used.

[0148] The regular closed-loop AGC control system with failed sub-amplifiers can be described by the block diagram of FIG. 15 and Equation D. 10 P out ⁡ ( j ⁢   ⁢ ω ) P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) · F I ( 1 + G O · F I · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) ) Equation ⁢   ⁢ D

[0149] By comparing Equation D with Equation A, it is seen that these two transfer functions have different forms, thus they will not have the same gain under same PID based AGC controller. Since the PID algorithm based AGC can not compensate for the gain errors caused by the sub-amplifiers failure to maintain the proper operation of the amplifier, the cancellation technique is used to correct either the input or output power for the PID algorithm.

[0150] A compensation factor is added to provide the block diagram of FIG. 16 and equation E: 11 P out ⁡ ( j ⁢   ⁢ ω ) P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) · F 1 ( 1 + G O · F 1 · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) · F 2 ) Equation ⁢   ⁢ E

[0151] Here,

[0152]

[0153] F1=[(M−K)/M]2: Power reduction factor caused by the failure of a number sub-amplifiers PA-1 to PA-M (FIG. 1)

[0154] F2: Power compensation factor

[0155] M: Total number of sub-amplifiers

[0156] K: Number of failed sub-amplifiers

[0157] Thus, if we let F1·F2=1, or 12 F 2 = 1 / F 1 = [ M M - K ] 2 ,

[0158] Equation E can be modified as: 13 P out ⁡ ( j ⁢   ⁢ ω ) ⁢ F 2 P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) 1 + G O · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) Equation ⁢   ⁢ E ′

[0159] By comparing Equation E|with Equation A, it is seen that the right sides of the two equations are identical, this means the system with failed sub-PA will have the same transfer function as that of a normal system after the compensation. Thus the PID algorithm could still be used for Auto Gain Control. And the power amplifier can still operate normally at reduced power without any signal distortion or without the amplifier being over-driven.

Conclusion

[0160] Overall compensated system can be described in block diagram FIG. 17 and Equation F. 14 P out ⁡ ( j ⁢   ⁢ ω ) P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) · F i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) · F 1 ( 1 + G O · G out ⁡ ( j ⁢   ⁢ ω ) · F out ⁡ ( j ⁢   ⁢ ω ) · F 1 · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) · F 2 ) Equation ⁢   ⁢ F

[0161] After cancellation, we have 15 P out ⁡ ( j ⁢   ⁢ ω ) · F 2 P i ⁢   ⁢ n ⁡ ( j ⁢   ⁢ ω ) = G I · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) 1 + G O · G C ⁡ ( j ⁢   ⁢ ω ) · G P ⁡ ( j ⁢   ⁢ ω ) Equation ⁢   ⁢ F

[0162] If there is no failed sub-amplifier, which means K=0, F2=1, the equation will be identical to Equation A.

[0163] Although the invention has been described in conjunction with a preferred embodiment, it is to be appreciated that various modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A power amplifier system for use in amplifying an RF input signal comprising:

a signal modulator that receives and modifies said input signal and provides therefrom a modified input signal;

M sub-power amplifiers connected together in parallel with each receiving and amplifying a portion of said modified input signal;

a combiner that combines said amplified portions of said modified input signal to provide a combined output signal;

a power detector that receives said combined output signal and provides therefrom an average output power signal representative of the average output power thereof;

a controller that monitors the operation of said M sub-amplifiers to determine if any have failed and adjusts the magnitude of said output power signal to compensate for any such failure and wherein said controller controls said modulator in accordance with a function of the magnitude of said output power signal.

2. A system as set forth in

claim 1 wherein the number of sub-power amplifiers that have failed is K.

3. A system as set forth in

claim 2 wherein the magnitude of the average output power signal is adjusted as a function of the number K.

4. A system as set forth in

claim 2 wherein the average output power signal is adjusted by multiplying it by the factor 16 [ M M - K ] 2.

5. A system as set forth in

claim 1 wherein said controller determines that a said sub-amplifier has failed when the magnitude of any current flowing therein is less than a threshold level.

6. A system as set forth in

claim 5 wherein the number of sub-amplifiers that have failed is K.

7. A system as set forth in

claim 6 wherein the average output power signal is adjusted as a function of the number K.

8. A system as set forth in

claim 6 wherein the average output power signal is adjusted by multiplying it by the factor of 17 [ M M - K ] 2.

9. A system as set forth in

claim 5 wherein said threshold level is related to the average of the magnitudes of all currents flowing in all of the operating ones of said M sub-amplifiers.

10. A system as set forth in

claim 6 wherein said controller turns the amplifier system off if K exceeds a number representing the maximum allowable number of failed sub-amplifiers.

11. A system as set forth in

claim 6 wherein said threshold level is related to the average of the magnitudes of all currents flowing in all of the operating ones of said M sub-amplifiers.

12. A system as set forth in

claim 10 wherein the average output power signal is adjusted as a function of the number K.

13. A system as set forth in

claim 12 wherein said the average output power signal is adjusted by multiplying it by the factor of 18 [ M M - K ] 2.