Antifuse programming circuit

Abstract

An antifuse programming circuit for performing a programming operation without causing any stress to an antifuse element is provided. The antifuse programming circuit includes: an antifuse element which is programmable according to a voltage difference between both terminals thereof; a control logic circuit for generating a control signal in response to internal address signals and an external address signal; a negative voltage generator, coupled to the antifuse element, for generating a negative voltage signal; and a power connection controller, in response to the control signal, for coupling the negative voltage signal to a ground terminal when the antifuse element is in an unprogrammed state.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor device; and, more particularly, to an antifuse programming circuit for performing a programming operation without causing any stress to an antifuse element.

DESCRIPTION OF THE PRIOR ART

[0002] In FIG. 1, there is shown a schematic diagram of a conventional antifuse programming circuit.

[0003] The conventional antifuse programming circuit 10 includes a program signal generator 11, an antifuse element 12 and a diode-connected NMOS transistor 13. The program signal generator 11 provides a negative voltage signal used for programming the antifuse element 12. In an unprogrammed state, a node N between the antifuse element 12 and the diode-connected NMOS transistor 13 is set to a floating state.

[0004] When the negative voltage signal is provided to the node N, a voltage difference between two terminals of the antifuse element 12 is greatly large so that an insulating material used to form the antifuse element 12 is broken down. In the floating state, a negative threshold voltage, i.e., −Vt, is provided to the node N. Thus, the voltage difference between both terminals of the antifuse element 12 becomes very small, so that the insulating material is not broken down.

[0005] However, a successive stress is caused to the antifuse element 12 due to the negative threshold voltage. As a result, there is a problem that a life span of the antifuse element 12 is shortened.

SUMMARY OF THE INVENTION

[0006] It is, therefore, an object of the present invention to provide an antifuse programming circuit for performing a programming operation without causing any stress to an antifuse element.

[0007] In accordance with an aspect of the present invention, there is provided an antifuse programming circuit, comprising: an antifuse element, the antifuse element being programmable according to a voltage difference between both terminals thereof; a control logic means for generating a control signal in response to internal address signals and an external address signal; a negative voltage generation means, coupled to the antifuse element, for generating a negative voltage signal; and a power connection control means, in response to the control signal, for coupling the negative voltage signal to a ground terminal when the antifuse element is in an unprogrammed state.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:

[0009] FIG. 1 is a schematic diagram showing a conventional antifuse programming circuit; and

[0010] FIG. 2 is a schematic diagram illustrating an antifuse programming circuit in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIG. 2 is a schematic diagram illustrating an antifuse programming circuit in accordance with the present invention.

[0012] Referring to FIG. 2, the antifuse programming circuit 20 in accordance with the present invention includes a control logic circuit 21, a power connection controller 22, a negative voltage generator 23 and an antifuse element 24.

[0013] The power connection controller 22 and the negative voltage generator 23 are operated under a control of the control logic circuit 21. That is, in an unprogrammed state, an output of the negative voltage generator 23 is electrically coupled to a ground terminal GND via the power connection controller 22.

[0014] The control logic circuit 21 receives internal address signals REPAIR_X_ADD and REPAIR_Y_ADD and an external address signal PGM_ACT_DLY to generate a control signal for controlling an output of the negative voltage generator 23. The control logic circuit 21 includes a NOR gate 211 for NORing the internal address signals REPAIR_X_ADD and REPAIR_Y_ADD, an inverter 212 for inverting an output of the NOR gate 211, and a NAND gate 213 for NANDing the external address signal PGM_ACT_DLY and an output of the inverter 212.

[0015] The power connection controller 22 includes a pull down unit 220 for pulling down a power potential VCC, a first inversion unit 221, which is coupled to the pull down unit 220, for inverting the control signal, a second inversion unit 222, which is coupled to the pull down unit 220, for inverting an output of the first inversion unit 221, and a switching unit 223 for coupling the output of the negative voltage generator 23 in response to an output of the second inversion unit 222.

[0016] The pull down unit 220 is implemented with a plurality of diode-connected PMOS transistors P3 and P4 that are serially coupled between a power terminal VCC and the first inversion unit 221.

[0017] The switching unit 223 is implemented with an NMOS transistor M3, coupled between the power terminal VCC and the antifuse element 24, whose gate receives an output of the second inversion unit 222.

[0018] In case where the control logic circuit 21 provides the control signal of a high level, the first inversion unit 221 outputs a low level signal via an output node N2 so that a PMOS transistor P2 contained in the second inversion unit 222 is turned on. As a result, a voltage level of a node N3 is transferred to an output node N3 of the second inversion unit 222 via a turned-on PMOS transistor P2.

[0019] At this time, if an external power potential is directly applied to a gate of the NMOS transistor M3 contained in the switching unit 223 and the negative voltage signal is applied to a source of the NMOS transistor M3, a voltage difference between the gate and the source becomes greatly large so that the NMOS transistor M3 is broken down. This phenomenon can be prevented by employing the pull down unit 220.

[0020] The voltage level of the node N3 is reduced in proportion to the number of diode-connected PMOS transistors. As a result, a reduced voltage level is applied to the gate of the NMOS transistor M3 so that the NMOS transistor M3 is correctly operated.

[0021] That is, the NMOS transistor M3 is turned on in response to the output of the second inversion unit 222 so that the output of the negative voltage generator 23 is electrically coupled to the ground terminal GND. Therefore, an undesired stress caused due to the negative threshold voltage can be prevented.

[0022] In case where the control logic circuit 21 provides the control of a low level, an NMOS transistor M1 and a PMOS transistor P1 contained in the first inversion unit 221 are turned off and on, respectively. Thus, a voltage level of the node N3 is transferred to the output node N2 of the first inversion unit 221.

[0023] Then, a voltage level that is pulled down through the pull down unit 220 is applied to the gate of the NMOS transistor M2 so that the NMOS transistor M2 is turned on. Since the negative voltage signal is applied to the gate of the NMOS transistor M3 via a turned-on NMOS transistor M2, the negative voltage signal is isolated from the ground terminal GND and the antifuse element 24 is programmed.

[0024] As described above, the antifuse programming circuit 20 in accordance with the present invention can prevent the stress to the antifuse element by coupling the negative voltage signal to the ground terminal in an unprogrammed state, thereby increasing a lift span of the antifuse element.

[0025] Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

1. An antifuse programming circuit, comprising:

an antifuse element being programmable according to a voltage difference between both terminals thereof;

a control logic means for generating a control signal in response to internal address signals and an external address signal;

a negative voltage generation means, coupled to the antifuse element, for generating a negative voltage signal; and

a power connection control means, in response to the control signal, for coupling the negative voltage signal to a ground terminal when the antifuse element is in an unprogrammed state.

2. The antifuse programming circuit as recited in

claim 1, wherein the power connection control means includes:

a pull down means for pulling down a power potential;

a first inversion means, coupled to the pull down means, for inverting the control signal;

a second inversion means, coupled to the pull down means, for inverting an output of the first inversion means; and

a switching means for performing a switching operation in response to an output of the second inversion means to couple the negative voltage signal to the ground terminal.

3. The antifuse programming circuit as recited in

claim 2, wherein the pull down means includes a plurality of diode-connected transistors that are serially coupled between a power terminal and the first inversion means.

4. The antifuse programming circuit as recited in

claim 3, wherein the diode-connected transistors are PMOS transistors.

5. The antifuse programming circuit as recited in

claim 4, wherein the switching means is an NMOS transistor, coupled between the power terminal and the antifuse element, whose gate receives an output of the second inversion means.

6. The antifuse programming circuit as recited in

claim 2, wherein the control logic means includes:

a NOR gate for NORing the internal address signals;

an inverter for inverting an output of the NOR gate; and

a NAND gate for NANDing an output of the inverter and the external address signal to generate the control signal.