Semiconductor memory devices having offset transistors and methods of fabricating the same
Semiconductor memory devices are provided that comprise unit memory cells. The unit memory cells include a first planar transistor in a semiconductor substrate, a vertical transistor disposed on the first planar transistor and a second planar transistor in series with the first planar transistor. The first planar transistor and the second planar transistor may have different threshold voltages. The semiconductor memory device may further include word lines. One of these word lines may form the gate of the second planar transistor a unit memory cell.
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2002-66086, filed Oct. 29, 2002, the contents of which are incorporated herein in its entirety by reference.
FIELD OF THE INVENTIONThe present invention generally relates to semiconductor devices and more specifically, to semiconductor memory devices and associated methods of fabrication.
BACKGROUND OF THE INVENTIONDRAM semiconductor memory devices generally have a higher density of integration than do SRAM semiconductor memory devices. However, DRAM memory devices require that a refresh operation be periodically performed in order to prevent data loss and thus DRAM memory devices consume power even when in a stand-by mode. It is not necessary to perform a refresh process with nonvolatile memory devices such as a flash memory devices. However, nonvolatile memory devices may require a higher voltage to perform a write operation.
In order to overcome the drawbacks of DRAM memory devices and nonvolatile memory devices, semiconductor memory devices using multi-tunnel junction patterns are suggested as disclosed, for example, in U.S. Pat. No. 5,952,692, entitled “Memory Device With Improved Charge Storage Barrier Structure” and U.S. Pat. No. 6,169,308, entitled “Semiconductor Memory Device And Manufacturing Method Thereof.” An example of a semiconductor memory device that uses multi-tunnel junction patterns is shown
Referring to
As shown in
As is also shown in
The semiconductor memory cell depicted in
Next, for reading data stored in the storage node 6, a reading voltage is applied to the storage node 6 and a suitable voltage, for example the ground voltage, is applied to the source region 39s. If the threshold voltage of the planar transistor TR2 is higher than the reading voltage, the planar transistor TR2 enters a turn-off state, and no current flows through the drain region 39d. On the contrary, if the threshold voltage of the planar transistor TR2 is lower than the reading voltage, the planar transistor TR2 enters a turn-on state and current flows through the drain region 39d. The storage node 6 acts as the gate of the planar transistor TR2 during the reading operation, and the reading voltage applied to the storage node 6 depends on a voltage applied to the word line 42 and a coupling ratio.
According to the above-described prior art, during the writing operation, the threshold voltage of the planar transistor TR2 changes depending on the quantity of electric charges stored in the storage node 6. Meanwhile, the reading operation comprises sensing a quantity of electric charges flowing through the channel region of the planar transistor TR2, where the quantity of electric charges flowing through the channel region of the planar transistor TR2 changes depending upon the threshold voltage of the planar transistor TR2. However, if electric charges stored in the storage node 6 are insufficient, a higher voltage may be needed for the word line in the reading operation. If the voltage applied to the word line is higher, a channel region may be formed in the vertical transistor which may result in leakage of the electric charges stored in the storage node 6.
SUMMARY OF THE INVENTIONPursuant to embodiments of the present invention, semiconductor memory devices are provided that comprise a plurality of unit memory cells. The unit memory cells may include a first planar transistor in a semiconductor substrate, a vertical transistor disposed on the first planar transistor and a second planar transistor in series with the first planar transistor. The first planar transistor and the second planar transistor may have different threshold voltages. The semiconductor memory device may further include a plurality of word lines. One of these word lines may form the gate of the second planar transistor in a plurality of unit memory cells.
A unit memory cell may also include a storage node. This storage node may act as the gate of the first planar transistor and may also act as the source and/or drain of the vertical transistor. A first planar transistor may include a first conductive region and a second conductive region that define a channel therebetween. The storage node may be on only a first portion of the channel region and not on a second portion of the channel region. In embodiments of the present invention, the portion of the first conductive region adjacent the channel may be only lightly doped as compared to the portion of the second conductive region adjacent the channel. The vertical transistor may comprise the storage node, a multi-junction storage pattern on the storage node, a portion of a data line that is on the multi-junction storage pattern, and a portion of the word line that is on the data line. A capping insulation pattern may also be provided between the data line and the word line.
Pursuant to additional embodiments of the present invention, unit cell semiconductor memory devices are provided. A unit cell is provided on a substrate in which a first conductive region and a second conductive region are formed that are separated by a channel region. The portion of the first conductive region adjacent the channel may be lightly doped while the portion of the second conductive region adjacent the channel may be heavily doped. The unit cells may further include a storage node that is formed solely on a first portion of the channel region, a multi-tunnel junction pattern on the storage node, a data line on the multi-tunnel junction pattern and a word line that covers the data line, the sidewalls of the multi-tunnel junction pattern and the storage node and a second portion of the channel region. The unit cell may also include a gate insulation pattern that is between the storage node and the semiconductor substrate and/or a capping insulation pattern between the data line and the word line.
Pursuant to further embodiments of the present invention, methods of manufacturing a semiconductor memory device are provided. Pursuant to these methods, a storage node and a multi-tunnel junction pattern may be sequentially formed on a first portion of a channel region defined in a semiconductor substrate to form a stacked multi-layered pattern. A data line may be formed on the multi-layered pattern, a gate interlayer insulating layer may be formed on the data line and a word line may be formed on the gate interlayer insulating layer. A capping insulation layer may also be formed on the data line prior to forming the word line, and a gate insulation pattern may be formed on the first portion of the channel region prior to forming the storage node. The word line may also be formed on a second portion of the channel region, and first and second conductive regions may be formed in the semiconductor substrate.
Pursuant to still further embodiments of the present invention, methods of manufacturing semiconductor memory devices are provided in which a first planar transistor and a second planar transistor are formed in series in a semiconductor substrate and a a vertical transistor is formed on the first planar transistor. The step of forming the first planar transistor in the semiconductor substrate may comprise forming a first conductive region and a second conductive region in the substrate to define a channel region and forming a storage node that comprises the gate of the first planar transistor on a portion, but not the entirety, of the channel region. This storage node may also act as either the source and/or the drain of the vertical transistor. A word line of the semiconductor memory device may act as the gate of the second planar transistor.
The semiconductor memory devices according to some embodiments of the present invention may allow performing read operations at relatively low operating voltages and/or may help minimize leakage of charges stored in the storage node.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will now be described more fully with reference to the accompanying drawings, in which typical embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer, element or substrate, or intervening layers and/or elements may also be present. In contrast, when a layer/element is referred to as being “directly on” another layer/element, there are no intervening layers or elements present. Likewise, when an element is described as being “between” two other elements it may be the only element between the two other elements or additional elements may also be present. Like reference numerals refer to like elements throughout.
Referring to
As shown in
A data line 127 is disposed on the multi-tunnel junction pattern 116 and on the isolation pattern 124 interposed between adjacent multi-tunnel junction patterns 116. Thus, the data line 127 is disposed between the first and second conductive regions 139d and 139s. A capping insulation pattern 128 may be disposed in the data line 127. A plurality of parallel word lines 142 cross over the data line 127. As shown in
A semiconductor memory device having the above mentioned structure comprises one vertical transistor TR1 and two planar transistors TR2a and TR2b (see
Referring to
Referring to
Referring to
An interconnecting layer and a capping insulation layer may then be sequentially formed on the resultant structure having the exposed upper conductive layer 118. The interconnecting layer may be, for example, a metal layer, a polycide layer and/or a doped silicon layer, and the capping insulation layer may be, for example, a silicon oxide layer and/or a silicon nitride layer. The capping insulation layer, the interconnecting layer and the upper conductive layer 118 are sequentially patterned to form a plurality of capping insulation patterns 128 and a plurality of data lines 127. Here, the capping insulation patterns 128 are parallel to the row direction and the data lines 127 are disposed beneath the capping insulation patterns 128.
The data lines 127 may cover a predetermined region of the isolating patterns 124 which are placed on row direction lines. As shown in
Referring to
An ion implantation process using the stack-type multi-patterns as a mask may be performed in order to adjust a threshold voltage of the second planar transistor TR2b.
A first mask pattern 132 defining a second channel region may then be formed after the ion implantation process (if any) for adjusting a threshold voltage of the second planar transistor TR2b has been performed. Another ion implantation process using the first mask pattern 132 as a mask may then be performed to form a lightly doped region 134 in the semiconductor substrate 102. As shown in
Referring to
Referring to
Referring to
According to some embodiments of the present invention, due to the offset transistor, the operation voltage of a semiconductor memory device can be decreased during a reading procedure. As noted above, the storage node may act as the gate electrode of the first planar transistor and as the source region of the vertical transistor. During a reading operation, the voltage of the word line is adjusted by a coupling ratio and is applied to the first planar transistor as a read voltage, while the voltage of the word line is directly applied to the second planar transistor. Therefore, leakage of electric charges in a storage node may be reduced, because a relatively low voltage may be applied to the word line. Additionally, the reading procedure of the semiconductor memory device can be effectively performed by controlling the threshold voltages of two planar transistors.
While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and equivalents.
Claims
1. A semiconductor memory device, comprising:
- a plurality of unit memory cells, wherein a unit memory cell comprises: a first planar transistor in a semiconductor substrate; and a vertical transistor disposed on the first planar transistor; a second planar transistor in the semiconductor substrate in series with the first planar transistor.
2. The semiconductor memory device of claim 1, wherein the semiconductor memory device further comprises a plurality of word lines.
3. The semiconductor memory device of claim 2, wherein one of the word lines comprises a gate of the second planar transistor.
4. The semiconductor memory device of claim 1, wherein the first planar transistor includes a storage node, and wherein the storage node comprises the gate of the first planar transistor.
5. The semiconductor memory device of claim 4, wherein the storage node further comprises the source of the vertical transistor.
6. The semiconductor memory device of claim 4, wherein the first planar transistor further comprises a first conductive region and a second conductive region.
7. The semiconductor memory device of claim 6, wherein the first planar transistor further comprises a channel region disposed between the first conductive region and the second conductive region, and wherein the storage node is disposed only on a first portion of the channel region.
8. The semiconductor memory device of claim 7, wherein a portion of the first conductive region adjacent the channel is lightly doped as compared to a portion of the second conductive region adjacent the channel.
9. The semiconductor memory device of claim 8, wherein the vertical transistor further comprises a multi-junction storage pattern on the storage node, a data line on the multi-junction storage pattern, and a word line that is on the data line.
10. The semiconductor memory device of claim 9, wherein the word line is also on the second channel region.
11. The semiconductor memory device of claim 9, further comprising a capping insulation pattern between the data line and the word line.
12. The semiconductor memory device of claim 1, wherein the first planar transistor and the second planar transistor have different threshold voltages.
13. A unit cell of a semiconductor memory device, comprising:
- a substrate having a first conductive region and a second conductive region separated by a channel region;
- a storage node disposed solely on a first portion of the channel region;
- a multi-tunnel junction pattern on the storage node;
- a data line on the multi-tunnel junction pattern; and
- a word line on the data line, on sidewalls of the multi-tunnel junction pattern and the storage node and on a second portion of the channel region.
14. The unit cell of claim 13, further comprising a gate insulation pattern between the storage node and the semiconductor substrate.
15. The unit cell of claim 13, wherein a portion of the first conductive region adjacent the channel is only lightly doped while a portion of the second conductive region adjacent the channel is heavily doped.
16. The unit cell of claim 13, further comprising a capping insulation pattern between the data line and the word line.
17. The unit cell of claim 13, wherein the first and second conductive regions, the channel region and the storage node comprise a first transistor.
18. The unit cell of claim 17, wherein the storage node, the multi-junction pattern, the data line and the word line comprise a second transistor that is disposed in a perpendicular orientation with respect to the first transistor.
19. The unit cell of claim 18, wherein the word line and the second portion of the channel region comprise a third transistor.
20. The unit cell of claim 19, wherein the first transistor and the third transistor have different threshold voltages.
21. The unit cell of claim 13, wherein the first portion of the channel region and the second portion of the channel region have different doping concentrations.
22. A method of manufacturing a semiconductor memory device, the method comprising:
- sequentially forming a storage node and a multi-tunnel junction pattern on a first portion of a channel region defined in a semiconductor substrate to form a stacked multi-layered pattern on the first portion of the channel region;
- forming a data line on the multi-layered pattern;
- forming a first conductive region adjacent the multi-layer pattern and forming a second conductive region adjacent a second portion of the channel region;
- forming a gate interlayer insulating layer on the data line; and
- forming a word line on the gate interlayer insulating layer and on the second portion of the channel region.
23. The method of claim 22, further comprising forming a capping insulation layer on the data line prior to forming the word line.
24. The method of claim 22, further comprising forming a gate insulation pattern on the first portion of the channel region prior to forming the storage node.
25. The method of claim 22, wherein forming the first conductive region adjacent the multi-layer pattern and forming the second conductive region adjacent the second portion of the channel region comprises:
- forming a mask pattern defining the second portion of the channel region;
- forming the first conductive region and the second conductive region in the semiconductor substrate using the mask pattern and the multi-layered pattern as an ion implantation mask; and
- removing the mask pattern.
26. The method of claim 25, further comprising performing an ion implantation process for adjusting a threshold voltage prior to forming the mask pattern.
27. The method of claim 22, wherein forming the first conductive region adjacent the multi-layer pattern and forming the second conductive region adjacent the second portion of the channel region comprises:
- forming a first mask pattern over at least the second channel region;
- forming a first lightly doped region and a second lightly doped region in the semiconductor substrate via ion implantation using the first mask pattern and the multi-layered pattern as an ion implantation mask;
- removing the first mask pattern;
- forming a spacer on the sidewalls of the multi-layered pattern;
- forming a second mask pattern over at least the second channel region;
- forming a first heavily doped region and a second heavily doped region in the semiconductor substrate via ion implantation using the second mask pattern, the multi-layered pattern and the spacer as an ion implantation mask; and
- removing the second mask pattern.
28. The method of claim 22, further comprising forming an upper conductive pattern between the multi-layered pattern and the data line.
29. A method of manufacturing a semiconductor memory device, comprising:
- forming a first planar transistor and a second planar transistor in a semiconductor substrate; and
- forming a vertical transistor on the first planar transistor;
- wherein the second planar transistor is in series with the first planar transistor and wherein a word line of the semiconductor memory device comprises the gate of the second planar transistor.
30. The method of claim 29, wherein forming a first planar transistor in a semiconductor substrate comprises forming a first conductive region and a second conductive region in the semiconductor substrate to define a channel region therebetween and forming a storage node that comprises the gate of the first planar transistor on only a portion of the channel region.
31. The method of claim 30, wherein the storage node further comprises the source or the drain of the vertical transistor.
32. The method of claim 31, wherein forming a first conductive region and a second conductive region in the semiconductor substrate to define a channel region therebetween comprises forming a lightly doped conductive region adjacent one side of the channel and forming a heavily doped conductive region adjacent the other side of the channel.
33. A semiconductor memory device, comprising:
- a first planar transistor comprising a storage node, a first conductive region and a second conductive region in a semiconductor substrate, wherein the first conductive region and the second conductive region define a channel region therebetween, and wherein the storage node is only on a first portion of the channel region;
- a vertical transistor comprising the storage node, a multi-tunnel junction pattern stacked on the storage node, a data line stacked on the multi-tunnel junction pattern, and a word line that is on the data line and on sidewalls of the storage node and the multi-tunnel junction pattern; and
- a second planar transistor comprising the first and second conductive regions and a portion of the word line that is on a second portion of the channel region.
34. The semiconductor memory device of claim 33, further comprising a gate insulating pattern between the storage node and the first portion of the channel region.
35. The semiconductor memory device of claim 33, wherein a first threshold voltage associated with the first planar transistor is different than a second threshold voltage associated with the second planar transistor.
36. The semiconductor memory device of claim 33, further comprising a gate interlayer insulator between the word line and sidewalls of the storage node, between the word line and sidewalls of the multi-tunnel junction pattern and between the word line and the second portion of the channel region.
37. The semiconductor memory device of claim 33, further comprising a capping insulation pattern between the data line and the word line.
38. A semiconductor memory device, comprising:
- a source region and a drain region in a semiconductor substrate;
- a gate that is laterally offset from at least one of the source region and the drain region and provided on the substrate between the source region and the drain region;
- a vertical transistor on the gate.
39. The semiconductor memory device of claim 38, wherein the gate comprises a storage node.
40. The semiconductor memory device of claim 39, wherein the storage node comprises a source/drain region of the vertical transistor.
41. A method of manufacturing a semiconductor memory device, comprising:
- forming a source region and a drain region of a first planar transistor in a semiconductor substrate;
- forming a gate of the first planar transistor on the semiconductor substrate;
- forming a vertical transistor on the gate of the first planar transistor such that the gate of the first planar transistor defines a first channel region beneath the gate of the first planar transistor and a second channel region outside the gate of the first planar transistor;
- forming a word line on the second channel region.
42. The method of claim 41, wherein the gate of the first planar transistor is on only a portion of the channel region.
43. The method of claim 42, wherein the gate of the first planar transistor further comprises the source or the drain of the vertical transistor.
44. The method of claim 41, further comprising forming a second planar transistor at the second channel region.
Type: Application
Filed: Oct 28, 2003
Publication Date: Feb 10, 2005
Patent Grant number: 7282761
Inventors: Se-Jin Ahn (Seoul), Se-Ho Lee (Gyeonggi-do)
Application Number: 10/696,615