Semiconductor device structured to prevent oxide damage during HDP CVD
A semiconductor device includes a patterned conductive layer on which an initial dielectric film is deposited by a non-etching deposition process. A second dielectric film is then deposited on the initial dielectric film by high-density plasma chemical vapor deposition (HDP CVD). The HDP CVD process etches the second dielectric film as it is being deposited, thereby smoothing the surface of the second dielectric film. The initial dielectric film insulates the patterned conductive layer from the plasma used in the HDP CVD process, so that plasma charge is not conducted to underlying oxide films, such as gate oxide films, and does not cause oxide damage.
1. Field of the Invention
The present invention relates to a semiconductor device structure and semiconductor device fabrication process.
2. Description of the Related Art
Integrated circuits are generally fabricated by forming circuit elements in a semiconductor substrate, then forming one or more metal interconnection layers above the substrate. Often the circuit elements are field-effect transistors having gate electrodes insulated from the substrate by a thin oxide film referred to as a gate oxide. The metal interconnection layers are insulated from one another, and from the semiconductor substrate, by insulating films referred to as interlayer dielectric films, or simply as interlayer dielectrics. The uppermost metal interconnection layer is covered by a surface passivation film.
The interlayer dielectrics and surface passivation film are often formed by chemical vapor deposition (CVD), a technique in which the substrate is heated, and source gases react near the surface the substrate to form a desired material that is deposited on the substrate. Various types of CVD are known, including low-pressure CVD (LP CVD), atmospheric-pressure CVD (AP CVD), plasma-enhanced CVD (PE CVD) and high-density plasma CVD (HDP CVD). The plasma types of CVD (PE CVD and HDP CVD) have the advantage of being performable at a lower temperature than the other types of CVD (LP. CVD and AP CVD). Since the mid-1990s, HDP CVD, which can effectively fill the narrow spaces between adjacent gate electrodes and adjacent interconnecting lines without creating bread-loaf shapes or cusps, has come into widespread use in fabrication processes with half-micrometer and smaller design rules. The reason for the effectiveness of HDP CVD is that the substrate is not only heated but also electrically charged, drawing the plasma down to etch unwanted parts of the deposited film.
This feature of HDP CVD leads to a problem however. During the HDP CVD process, the charge of the plasma is conducted through the metal interconnecting lines and gate electrodes to the gate oxide. In recent devices, the gate oxide is extremely thin, and is vulnerable to damage from the plasma charge. Although the damage mechanism is not completely understood, the damage is thought to result from the trapping of charge in the gate oxide film. Electron microscope studies by the inventor have confirmed that gate oxide damage occurs as a result of HDP CVD.
Such damage can lead to failure of devices in factory tests, thus reducing the yield of the fabrication process, or failure in the field, reducing the reliability of the fabricated devices. Accordingly, there is a need for a fabrication process that retains the advantages of HDP CVD while avoiding damage to thin gate oxide films.
SUMMARY OF THE INVENTIONAn object of the present invention is to avoid damage to gate oxide films during HDP CVD.
In the invented method of fabricating a semiconductor device, a patterned conductive layer is formed on a substrate. An initial dielectric film is then deposited by a non-etching deposition process, covering the exposed surfaces of the patterned conductive layer and the substrate. Next, a second dielectric film is deposited on the initial dielectric film by HDP CVD.
The initial dielectric film is preferably less than one hundred nanometers thick. A thin initial dielectric film can be formed without creating cusps or bread-loaf shapes, even though a non-etching deposition process is used, and without damaging the patterned conductive layer, even if a comparatively high-temperature deposition process is used.
Since the initial dielectric film covers the exposed surfaces of the patterned conductive layer, when HDP CVD is used to deposit the second dielectric film, the plasma charge is not conducted to the patterned conductive layer, and accordingly is not conducted to any gate oxide films present in the semiconductor device. Gate oxide damage is thereby avoided during HDP CVD.
The invention also provides a semiconductor device fabricated by the process described above.
BRIEF DESCRIPTION OF THE DRAWINGSIn the attached drawings:
Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters. The drawings illustrate the formation of one part of a semiconductor integrated circuit. More specifically, the drawings illustrate the formation of one field-effect transistor.
FIGS. 1 to 3 illustrate three stages in the fabrication of a semiconductor device according to a first embodiment of the invention. In
Following formation of the gate electrode 8, an initial dielectric film 16 of silicon nitride (Si3N4) a few nanometers or a few tens of nanometers thick is deposited by low-pressure chemical vapor deposition (LP CVD). The initial dielectric film 16 covers the exposed surfaces of the gate oxide film 2, field oxide 4, substrate 6, and gate electrode 8. Since LP CVD is a thermal reaction process, the thickness of the initial dielectric film 16 should be less than one hundred nanometers (100 nm), so that the process does not continue for an extended time.
The first embodiment is not limited to the use of silicon nitride or LP CVD. The initial dielectric film 16 may be deposited by another non-etching type of CVD, such as plasma-enhanced CVD (PE CVD) or atmospheric-pressure CVD (AP CVD). In PE CVD, plasma is released from a so-called shower head above the substrate, but chemical reactions take place before the plasma reaches the substrate surface, so the film deposited on the substrate surface is not etched by the plasma. In AP CVD, no plasma is released from the shower head, and no etching takes place. The same is true of LP CVD. For AP CVD, the silicon source gas is preferably tetraethylorthosilicate (TEOS).
Referring to
The first embodiment is not limited to the use of silicon dioxide for the interlayer dielectric film 18. The interlayer dielectric film 18 may be formed from another dielectric material, such as fluorinated silicon oxide (SiOF).
Referring to
Next, the interconnecting lines 22 may be covered by a surface passivation film (not shown), or a further interlayer dielectric film (not shown) may be deposited and a further layer of interconnections (not shown) may be formed.
During the HDP CVD process that deposits the interlayer dielectric film 18, the conductive material of the gate electrode is not directly exposed to the plasma, so the electrical charge of the plasma is not conducted to the underlying gate oxide film 2. Electrical damage to the gate oxide film 2 is thereby avoided, reducing the rate of failures in factory tests and in the field.
FIGS. 4 to 7 illustrate four stages in the fabrication of a semiconductor device according to a second embodiment of the invention. The second embodiment is similar to the first embodiment but has self-aligned contacts.
In
In
The second embodiment is not limited to the use of silicon nitride and LP CVD for the initial dielectric film 16; other materials and other non-etching deposition processes may be used instead, as described in the first embodiment.
Referring to
Referring to
During the HDP CVD process that deposits the interlayer dielectric film 18, the window 28 in the dielectric film 24 on the gate electrode 8 is protected by the initial dielectric film 16, as shown in
FIGS. 8 to 10 illustrate three stages in the fabrication of a semiconductor device according to a third embodiment of the invention. The third embodiment protects the gate oxide film 2 from electrical damage during the formation of a surface passivation film above the metal interconnecting layer.
In
In
The third embodiment is not limited to the use of silicon nitride for the initial dielectric film 30; other dielectric materials may be used instead.
Referring to
During the HDP CVD process that forms the surface passivation film 32, since the metal interconnecting lines 22 are covered by the initial dielectric film 30, the electrical charge of the plasma is not conducted through them and through the gate electrode 8 to the gate oxide film 2, which is thereby protected from electrical damage. Fabrication process yields and device reliability are improved accordingly.
In a variation of the third embodiment, the same technique is used to protect the gate oxide film 2 from damage during the formation of interlayer dielectric films between multiple metal wiring layers, by depositing an initial dielectric layer below each interlayer dielectric film to cover any exposed electrically conductive surfaces before HDP CVD is carried out.
For comparison with the preceding embodiments,
Although the invention has been described as preventing damage to a gate oxide film, the invention may also be used to prevent electrical damage to other oxide films, such as capacitor oxide films, during HDP CVD.
Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.
Claims
1. A method of fabricating a semiconductor device, comprising:
- forming an insulating film on a surface of a substrate;
- forming a patterned conductive layer on a the insulating film;
- forming a sidewall on the patterned conductive layer;
- depositing a first dielectric film covering exposed surfaces of the patterned conductive layer and the insulating film by a non-etching deposition process; and
- depositing a second dielectric film on the first dielectric film by high-density plasma chemical vapor deposition (CVD), the first dielectric film preventing plasma charge from being conducted through the patterned conductive layer to the insulating film.
2. The method of claim 1, wherein the first dielectric film is deposited by low-pressure CVD.
3. The method of claim 1, wherein the first dielectric film is deposited by atmospheric-pressure CVD using tetraethylorthosilicate.
4. The method of claim 1, wherein the first dielectric film is deposited by plasma-enhanced CVD.
5. The method of claim 1, wherein the first dielectric film comprises silicon nitride.
6. The method of claim 1, wherein the first dielectric film is less than one hundred nanometers thick.
7. The method of claim 1, wherein the patterned conductive layer includes a gate electrode.
8. The method of claim 1, wherein the patterned conductive layer is a metal interconnection layer.
9. The method of claim 1, wherein the second dielectric film is an interlayer dielectric film.
10. The method of claim 1, wherein the second dielectric film is a surface passivation film.
11. A semiconductor device comprising:
- a substrate;
- an insulating film disposed on a surface of the substrate;
- a patterned conductive layer disposed on the insulating film;
- a sidewall making contact with a side of the patterned conductive layer;
- a first dielectric film disposed on exposed surfaces of the patterned conductive layer and the insulating film, the first dielectric film being deposited by a non-etching deposition process; and
- a high-density plasma CVD dielectric film disposed on the first dielectric film.
12. The semiconductor device of claim 11, wherein the first dielectric film is deposited by low-pressure CVD.
13. The semiconductor device of claim 11, wherein the first dielectric film is deposited by atmospheric-pressure CVD using tetraethylorthosilicate.
14. The semiconductor device of claim 11, wherein the first dielectric film is deposited by plasma-enhanced CVD.
15. The semiconductor device of claim 11, wherein the first dielectric film comprises silicon nitride.
16. The semiconductor device of claim 11, wherein the first dielectric film is less than one hundred nanometers thick.
17. The semiconductor device of claim 11, wherein the patterned conductive layer includes a gate electrode.
18. The semiconductor device of claim 11, wherein the patterned conductive layer is a metal interconnection layer.
19. The semiconductor device of claim 11, wherein the high-density plasma CVD dielectric film is an interlayer dielectric film.
20. The semiconductor device of claim 11, wherein the high-density plasma CVD dielectric film is a surface passivation film.
Type: Application
Filed: Sep 17, 2004
Publication Date: Feb 17, 2005
Inventor: Minoru Saito (Tokyo)
Application Number: 10/942,786