Semiconductor integrated circuit
A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.
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The present invention relates to a semiconductor integrated circuit device, or in particular to a technique for mounting a large-capacity memory and a logic circuit on the same chip.
The references cited in this specification are listed below and will be referred to with the reference numbers attached thereto: Reference 1, “Very Large Scale Integration Memory” by Kiyoo Itoh, published by Baifukan Co., Ltd., 1994, pp. 13, and Reference 2, JP-A-62-226494 (corresponding to U.S. Pat. No. 4,803,664).
In recent years, the importance of a system-on-chip LSI having mounted thereon both a dynamic random access memory (DRAM) and a logic circuit at the same time has increased for multimedia applications. In the future, it will become necessary to mount a DRAM, a static random access memory (SRAM) and a processor or the like on a single chip. With the conventional DRAM memory cell configured with a transistor and a special large-capacity capacitor, however, the process for fabricating the capacitor is so complicated that it is difficult to fabricate the DRAM through the same process as the logic circuit in a system-on-chip LSI. The result is a limited cost reduction. Thus a DRAM memory cell free of a capacitor is required.
Candidates are the 4.5, 3.5, 3.5 and 2.5 line-type 3-transistor cells shown in FIGS. 1.0(a) to (d) on page 13 of Reference 1, for example, which the present inventors have begun to re-evaulate. The 3-transistor cell comprises a storage MOSFET for storing an information voltage in the gate thereof, a write MOSFET for writing the information voltage in the aforementioned gate, and a read MOSFET for reading the state of the aforementioned gate voltage. The 3-transistor cell, which can be easily fabricated with substantially the same process as the logic circuit, may be fabricated at low cost. Also, this cell itself has an amplification function, and therefore the operation is stable as a large read signal voltage is read on a data line. Further, this cell is suitably operated at low voltage and therefore can be implemented with low power consumption constituting a suitable application to multimedia. These features have been discovered by the present inventors.
The DRAM comprising the 3-transistor cell is described also in Reference 2. This memory has a pair of data lines and is accessible for write and read operation at high speed. In view of the fact that the information stored in the memory cell is detected and amplified by a sense amplifier, however, a dummy cell is required for each pair of the data lines, thereby requiring a correspondingly increased space. Also, the dummy cell disclosed in the cited Reference 2 has an amplification function, and therefore the reference voltage appearing on the data lines undesirably changes with time. As a result, it is difficult to set the start timing of the sense amplifier and in some cases, the read information cannot be detected by the sense amplifier. This is by reason of the fact that an excessively slow setting of the start timing of the sense amplifier reduces the differential voltage between the pair of the lines and makes unstable the operation.
SUMMARY OF THE INVENTIONAccordingly, an object of the present invention is to provide a memory not including a dummy cell.
A typical example of the present invention will be described. The dummy cell is eliminated by setting a different precharge voltage for each of the data lines making up the data line pair connected to memory cells having the amplification function. Also, the stable operation is secured by setting the reference voltage appearing on the data lines to a predetermined value. A specific example of the memory cell having the amplification function is so-called the 3-transistor cell including three transistors.
BRIEF DESCRIPTION CF THE DRAWINGS
[Embodiment 1]
The basic operation of the invention will be explained with reference to
The write operation into the memory cell can be performed by setting the word line selectively to the write level (a high voltage such as VDH) (“WLW on” in
As described above, according to this invention, the precharge level of the data line DLB can be used as a reference voltage for amplification. Thus, the dummy cell is not required, and no space increase is required unlike in the prior art. Also, since the reference voltage is constant with time, the sense operation can be stabilized.
In the memory cell shown in
[Embodiment 2]
According to this embodiment, the data lines have a hierarchical structure including pairs of the local data lines DL (DL1 to DLn), DLB (DLB1 to DLBk) or supplying and receiving data to and from the memory cells, and pairs or the global data lines GDL (GDL1 to GDLk), (GDLB1 to GDLBk) longitudinally extending in parallel. Each pair of the global data lines is connected to a plurality of blocks BLK (BLK11 to BLKmk). Each block includes a pair of local data lines connected with the memory cells MC (MC11 to MCn1) and switching MOSFETs (QRT, QWT) for connecting the global data line and the local data line. The switching MOSFETs are controlled by block select signals RWC (RWC1 to RWCm) generated by a peripheral circuit (PERI). A given pair of the global data lines described above are connected to a complementary common pair of the data lines (IO and IOB) by decoding an external input address (YADR) of the DRAM core (DRAMC) with a Y decoder (YDEC) and driving the corresponding switches QY1, QY2 with a corresponding Y driver (YDRV). Each pair of the global data lines, though not specifically limited, have a well-known differential amplifier of CMOS latch type SA including P-type MOSFETs Q1, Q2 and N-type MOSFETs Q3, Q4 as shown in
As described above, this invention has the feature that the high-speed amplification operation is made possible by the hierarchical structure of the data lines which can reduce the capacitance of the data line pair driven directly by the sense amplifier. This is by reason of the fact that the capacitance of the diffusion layer of the MOSFET is larger than the parasitic capacitance of the wiring layer metal and therefore the parasitic capacitance can be effectively reduced by reducing the number of the MOSFETs connected to the same wiring. The reason why the differential amplifier is used, on the other hand, is to prevent the rash current which otherwise might be generated in the transistors QR, QS at the time of writing into the memory cell. In the case where the voltage VDD is written into the node N1 of the block BLK11 among others, for example, the transistor QS is turned on. At the same time, the transistors CAR and QW are also in on state, and therefore the data line DL1 acquires a path to the voltage VSS. As a result, the rash current is undesirably generated in the transistors QR and QS unless the data line DL1 is at 0 V. This poses the problem, for example, at the time of the operation of inverting the 0 information stored in the node N1 to the 1 information (what is called the inverted writing), for example. In the process, the data line DL1 is at the precharged level, so that the rash current undesirably flows in the transistors QR and QS unless written differentially.
The local data lines DL and DLB have precharge MOSFETs QP1 and QP2 controlled by the precharge signal PC. During the precharge period, the data lines DL and DLB are precharged to a source voltage VDD (say, 1 V) and a voltage VDD/2 (say, 0.5 V) one half as large. Also, the pair of the global data lines GDL, GDLB are precharged to the VDD/2 level during the precharge period by the precharge MOSFETs QP3, QP4 controlled by the precharge signal PC.
The memory array is configured with a plurality of data line pairs and a plurality of word lines (WL1 to WLmn, etc.) orthogonal thereto. In the drawing, four word lines WL1, WLn, WLmn-n+1, WLmn are illustrated as representative ones. By decoding an external input X address (XADR) with an X decoder (XDEC), one of the word lines is selectively driven by the X driver (XDRV) (also called the word driver). This drawing shows an example in which the X address and the Y address are input without multiplexing, but the number of address terminals can be reduced to one half by multiplexing the addresses.
Each memory cell is arranged at the intersection between a word line and local data lines DL, DLB, and is configured with three transistors including a storage MOSFET QS adapted to turn on or off by the information voltage at the gate thereof when the particular word line is selected, a read MOSFET QR for reading the information held by the transistor QS and transmitting it to the local data line DL, and a write MOSFET QW for applying the write data from the local data line DLB to the gate of the transistor QS. According to this embodiment, the gates of the transistors QS and QR are connected to the same word line. The source-drain path of the storage MOSFET QS is connected to the read MOSFET QR and the ground potential VSS (0 V) described above.
The data are input and output to and from outside of the DAM core. The read switch SW is turned on and the memory cell is read. Then, the stored information transmitted to the lines IO and IOB is output to the data output terminal DO through a main amplifier and a data output buffer DOB. At the time of write operation, on the other hand, the data input to the data input buffer DIB from the data input terminal DI is transmitted with a differential voltage to the lines IO and IOB by turning on the write switch WSW and written in the memory cell by the write operation described later.
A power generating circuit (VGC) has the function of decreasing, with a regulator or the like, the voltage VDD input from an external source to form a VDL power supply and the function of generating a VDH power supply by boosting the voltage VDL or VDD with a charge pump circuit or the like. The voltages VDL and VDH are used as a read level and a write level, respectively, of the word line described later. In the case where the VDL power supply is required to be higher than the voltage VDD, the VDD voltage input from an external source is directly boosted or regulated and then boosted.
This embodiment has the feature that a reference voltage level of the differential sense amplifier is generated without a dummy cell by combining a memory cell having the amplification function and a pair of the local data lines set to different precharge voltages.
Once the precharge signal PC reaches 0 V, the precharge MOSFET is turned off, and therefore the pair of the lines described above assume a floating state thus continue to hold the precharge voltage. Under this condition, the write and read operations into and from the memory cell are carried out. An explanation will be given below of the write, read and refresh operations of the memory cell in the case where the word line WL1 and the column line YS1 are selected.
(1) Write Operation
For writing the high voltage VDD or the low voltage VSS corresponding to binary information 1 or 0, respectively, into the storage node (N1) of the memory cell MC1, a sufficiently boosted high voltage VDH is required to be applied to the word line WL1. This voltage VDH is required to satisfy the relation VDH≧VDD+Vtw, where Vtw is the threshold value (say, 0.5 V) of the write MOSFET QW (VDH=2.5 V, for example). Under this condition, assume that one (RWC1) of the block select signal lines (RWC) is selected. Then, the differential voltage corresponding to the write data input from the data input terminal D1 is applied to the gate of the transistor QS through the corresponding local data line from the global data line and written into the memory cell ACE. It should be noted here, however, that once the voltage VDH is applied to the word line WL1, the information stored in the column unselected memory cells not selected by a column select signal which is arranged on the same word line is destroyed. Specifically, the precharge voltage VDD/2 of the corresponding local data line DLB1 is undesirably applied to the storage node in each column unselected memory cell. In order to prevent this information destruction, all the memory cells on the selected word line are read beforehand and by amplifying them with each sense amplifier, the amplified voltage is rewritten in the respective memory cells. In the selected memory cell MC11, however, the amplified voltage is written in by replacing it with the input data voltage from the common data line IOB. Thus, the read operation is required in advance of the write operation. This read operation will be explained below. As described above, the word line voltage of the memory cell in
First, an explanation will be given of the operation of reading the high voltage VDD which may be stored in the memory cell MC11. The read operation is started by applying a pulse of intermediate level voltage VDL to the word line. The amplitude VDL of this pulse is required to be set in such a manner as to turn on the transistor QR and to turn off the transistor QW. For this purpose, the following conditions are required to be met.
Assume that the memory cell stores the binary information of voltage VDD or 0 V in the gate of the transistors QS and the stored information is detected according to whether the transistor QS is on or off when a read pulse is applied to the word line. For applying the read pulse VDL and turning on the transistor QR, the following relation is required to be satisfied.
VDL>Vtr (1)
where Vtr is the threshold value of the transistor QR. If the information stored in the gate of the transistor QS is not to be destroyed upon application of a read pulse to the transistor QW, the following conditions must be met. Specifically, the conditions for turning off the transistor QW are determined which assure that the charge accumulated in the gate of the transistor QS is not released to the local data line DLB1 through the transistor QW in the case where the gate voltage of the transistor QS is VDD. The data line precharged to VDD/2 is the source of the transistor QW, and therefore the condition is described as follows.
VDL<VDD/2+Vtw (2)
where Vtw is the threshold value of the transistor QW. In the case where the gate voltage of the transistor QS is 0 V, on the other hand, the transistor QS remains off even if the gate of the transistor QS is charged and the gate voltage is boosted from 0 V by the turning on of the transistor QW, if the boosted voltage is lower than the threshold voltage Vts. The condition for this is as follows.
VDL<Vts+Vtw (3)
If the charge accumulated in the gate of the transistor QS is not to be released to the local data lines for a long time (say, 2 ms to 64 ms), the threshold voltage Vtw is desirably increased. For high-speed reading, on the other hand, the voltages Vts and Vtr are desirably as low as possible. Thus, the threshold values of these three voltages can be freely selected within a range satisfying the aforementioned inequality. Nevertheless, the voltage Vtr cannot be reduced as much as the voltage Vts. Otherwise, an instability may be caused. The reason is that a leak current (what is called the subthreshold current) flows in the transistor QR in a multiplicity of other unselected memory cells connected to the same local data line thereby reducing the precharge voltage of the local data line. Assuming that VDD=1 V, Vtw=1 V, Vts=0 V and Vtr=0.5 V, for example, the range of the voltage VDL in which the stored information is not destroyed by the transistor QW is given as follows from equations (1) to (3).
1.5 V>VDL>0.5 V
By setting the voltage VDL in this way, the data lines DL1 and DLB1 thus far precharged to VDD and VDD/2, respectively, are changed as follows. In the case where the gate (storage node N1) voltage of the transistor QS is VDD, the data line DL1 is discharged to 0 V (designated by N1 in
Now, after the stored information is read out on the local data line DL1, assume that the control signal RWC1 is set to high level thereby to turn on the transistors QRT and QWT. The data lines DL1 and GDL1 or the data lines DLB1 and GDLB1 are connected to each other. In the process, the data lines DLB1 and GDLB1 are at the same potential level (precharge level), and therefore the potential remains unchanged. Nevertheless, a read signal (vs) appears on the data line GDL1 due to toe charge share corresponding to the parasitic capacitance as described below.
In the case where the local data line DL1 is discharged to 0 V, the level of the global data line GDL1 is reduced by vs from VDD/2, and the data line DL1 also comes to assume the same level, i.e. VDD/2 less vs. In the case where the read data line DL1 remains at the precharge level VDD, on the other hand, the data line GDL1 increases by a small voltage (+vs) from the precharge voltage VDD/2, and the data line DL1 also comes to assume the same level of VDD/2+vs. This situation is described by dotted line in the waveform diagrams of the data lines DL1, DLB1, GDL1, GDLB1 of
The differential voltage between VDD and VSS applied to the pair of the common data lines (IO, IOB) for writing in the memory cell after amplification in the sense amplifier is sent to the pair of the global data lines (GDL1, GDLB1) and the pair of the local data lines (DL1, DLB1) by setting the column select line YS1 to high level selectively. (In the drawing, the behavior of the data line DL1′ indicated by dotted line represents the case in which 0 V is stored in the gate of the storage MOSFET QS.) After that, the word line level is raised to the write level VDH. As a result, the voltage of the write data line DLB1 is transmitted to the gate of the transistor QS in the memory cell MC11 thereby to complete the write operation. An amplified stored information voltage is rewritten in other column unselected memory cells on the same word line.
Upon completion of the write operation into the column selected memory cell an the rewrite operation into the column unselected memory cells as described above, the word lines WL1 and YS1 are reduced to low level and the transistors QY1, QY2 are turned off. Further, the precharge signal PC is set to high level (VDH) so that each local data line pair and each global data line pair are precharged in preparation for the next memory access.
(2) Read Operation
(3) Refresh Operation
The refresh operation is performed in such a manner that the column select line YS is left in unselected state in
To clarify the relation between the layers, the sectional views taken in lines a-a′ and line b-b′ of
[Embodiment 3]
In the second embodiment described above, a sufficient timing margin is available in view of the fact that the read and transfer MOSFET QRT and the write and transfer MOSFET QWT are controlled by a single signal RWC. Also, the electrical balancing level of the pair of the data lines as viewed from the sense amplifier is so good that a correspondingly stabler, high-speed operation is possible. In view of the need of wiring the power lines of the voltages VSS and VDD/2 for each block BLK, however, the area may increase in some cases.
In the read operation, the read signal for the selected memory cell is amplified by the sense amplifier SA and output to the pair of the common data lines and led out from the data output terminal DO. By increasing the select level of the word line to the high voltage VDH, a voltage corresponding to the read information can be rewritten for all the column selected cells and the column unselected cells.
For the refresh operation, on the other hand, the column select line YS is kept in unselected state while the read/rewrite operation for all the memory cells on the word lines is performed for all the word lines.
[Embodiment 4]
In the embodiments described above, the pair of the local data lines connected to the pair of the global data ines constitutes only a selected block in the case of amplification by the sense amplifier. This configuration can reduce the number of the MOSFETs connected to the pair of the global data lines and makes possible a high-speed amplification operation with a small load capacitance. This is because the parasitic capacitance of the metal wiring is generally smaller than the parasitic capacitance generated by the connection of a multiplicity of MOSFETs. Nevertheless, it is sometimes more desired to save the number of the wirings than to achieve the high-speed amplification operation. A memory array having a reduced number of wirings according to an embodiment will be explained below.
[Embodiment 5]
The write operation according to this embodiment shown in
In the first step of the read operation for the memory cell, the column select switches QY1 and QY2 are turned on so that the write signal voltage transmitted to the pair of the common data lines is transmitted to the pair of the global data lines. After that, the word line is set to the write level VDH so that the write signal is transmitted to the storage node N1 of the memory cell. In this way, the word line is set to the column unselected level of 0 V thereby to electrically isolate the storage node from the local data line. After that, the precharge state is restored in the same manner as explained with reference to
Reference is made to
With reference to
For the write operation into the memory cell, the first step is to turn on the column select switches QY1, QY2 so that the write signal voltage transmitted to the pair of the common data lines is transmitted to the pair of the main data lines MGDL, MGDLB, and the control signal IC is set to high level, which control signal IC is transmitted to the pair of the global data lines by turning on the switches QI1, QI2. After that, the write signal is transmitted to the storage node N1 of the memory cell by setting the word line to the write level VDH, and the word line is set to the unselected level of 0 V thereby to isolate the storage node from the local data lines. Then, the precharge state is restored in the same manner as described with reference to
[Embodiment 6]
The write operation and the read operation are substantially the same as those explained with reference to
[Embodiment 7]
In the memory array configuration shown in
First, an explanation will be given of the equalization of the parasitic capacitance. For convenience' sake, adjacent pairs of the global data lines (GDL1, GDLB1 and GDL2, GDLB2) will be taken as an example. These global data line pairs each are assumed to be connected with four blocks each including n memory cells MC11 to MC1n. Also, assume that the block BLK11 is selected and the control signal RC is at high level. Under this condition, the data line GDL1 is connected with a total of 3n+2 transistors, i.e. (n+1) MOSFETs including the transistor QRT of the block BLK11 and the read MOSFETs connected thereto, n write MOSFETs for the BLK12, one read and transfer MOSFET for the block BLK13, and n write MOSFETs for the block BLK14. The global data line GDLB1, on the other hand, is connected with a total of 2n+1 MOSFETs including n write MOSFETs for the block BLK1, one read and transfer MOSFET for the block BLK13, n write MOSFETs for the block BLK13 and one read and transfer MOSFET for the block BLK14. In the case where the global data lines are not twisted, the number of the MOSFETs connected to the global data line GDL is n+4 in total including the transistor QRT of the block BLK11 and n read MOSFETs connected thereto, a read and transfer MOSFET for the block BLK12, a read and transfer MOSFET for the block BLK13 and a read and transfer MOSFET for the block BLK14. The number of the MOSFETs connected to the global data line GDLB, on the other hand, is 4n in total including n write MOSFETs for the block BLK11, n write MOSFETs for the block BLK12, n write MOSFETs for the block BLK13 and n write MOSFETs for the block BLK14. In this way, the imbalance of the number of the MOSFETs connected to the global data line pair is remarkably improved. In similar fashion, the arrangement of the pair of the global data lines as indicated by the data lines GDL2, GDLB2 also equalizes the number of connections on the read and write sides of the block BLK and therefore clearly improves the imbalance of the number of the connected MOSFETs.
Now, the reduction in the noise appearing in the global data lines GDL and GDLB will be explained. At the time of write and read operations of the memory, the data lines GDL and GDLB change from the precharge level to VDD or VSS. This process is known to generate a noise in adjacent global data lines due to capacitive coupling. In the case where the data lines GDL and GDLB are arranged as shown in
Incidentally, the invention is not limited to this example in which a pair of global data lines are connected with four blocks.
[Embodiment 8]
[Embodiment 9]
The present invention eliminates the need of the dummy cell which has been essential to the conventional DRAM circuit using the gain cell, and therefore can reduce the required space and the fabrication cost. Also, the hierarchical data line structure makes high-speed operation possible.
Claims
1-25. (canceled)
26. A semiconductor integrated circuit comprising:
- a first global data line pair including a first global data line and a second global data line;
- a first sense amplifier coupled between the first global data line and the second global data line;
- a plurality of first memory blocks each including a first data line, a plurality of first memory cells coupled to the first data line, and a first switch coupled between the first data line and the first global data line; and
- a plurality of second memory blocks each including a second data line, a plurality of second memory cells coupled to the second data line, and a second switch coupled between the second data line and the second global data line,
- wherein when information is read out from one of the plurality of first memory cells, a read signal appears on the first global data line via the first switch and the sense amplifier amplifies the read signal on the first global data line,
- wherein when information is read out from one of the plurality of second memory cells, a read signal appears on the second global data line via the second switch and the sense amplifier amplifies the read signal on the second global data line, and
- wherein the number of the first switches is the same as the number of the second switches.
27. A semiconductor integrated circuit according to claim 26,
- wherein the first global data line is directly connected to the plurality of second memory cells, and the second global data line is directly connected to the plurality of first memory cells,
- wherein when information is written into one of the plurality of first memory cells a write signal is directly supplied from the second global data line to the one of the plurality of first memory cells, and
- wherein when information is written into one of the plurality of second memory cells a write signal is directly supplied from the first global data line to the one of the plurality of second memory cells.
28. A semiconductor integrated circuit according to claim 26,
- wherein each of the plurality of first memory blocks further includes a third data line coupled to the plurality of first memory cells and a third switch coupled between the second global data line and the third data line,
- wherein each of the plurality of second memory blocks further includes a fourth data line coupled to the plurality of second memory cells and a fourth switch coupled between the first global data line and the fourth data line,
- wherein when information is written into one of the plurality of first memory cells, a write signal is supplied to the third data line via the third switch, and
- wherein when information is written into one of the plurality of second memory cells, a write signal is supplied to the fourth data line via the fourth switch.
29. A semiconductor integrated circuit according to claim 26,
- wherein each of the first and second memory cells is a gain cell.
30. A semiconductor integrated circuit according to claim 29,
- wherein each of the plurality of first memory cells has a first storage transistor, a first read transistor, and a first write transistor,
- wherein a source and drain of the first write transistor are coupled between a gate of the first storage transistor and the second global data line, and a sate of the first write transistor is coupled to a first word line,
- wherein a source and drain of the first storage transistor and a source and drain of the first read transistor are coupled in series between the first data line and a first potential, and a gate of the first read transistor is coupled to the first word line,
- wherein each of the plurality of second memory cells has a second storage transistor, a second read transistor, and a second write transistor,
- wherein a source and drain of the second write transistor are coupled between a gate of the second storage transistor and the first global data line, and a gate of the second write transistor is coupled to a second word line, and
- wherein a source and drain of the second storage transistor and a source and drain of the second read transistor are coupled in series between the second data line and the first potential, and a gate of the second read transistor is coupled to the second word line.
31. A semiconductor integrated circuit according to claim 29,
- wherein each of the plurality of first memory cells has a first storage transistor, a first read transistor, and a first write transistor,
- wherein a source and drain of the first write transistor are coupled between a gate of the first storage transistor and the first global data line, and a gate of the first write transistor is coupled to a first write word line,
- wherein a source and drain of the first storage transistor and a source and drain of the first read transistor are coupled in series between the first data line and a first potential, and a gate of the first read transistor is coupled to a first read word line,
- wherein each of the plurality of second memory cells has a second storage transistor, a second read transistor is coupled to a first read word line,
- wherein a source and drain of the second write transistor are coupled between a gate of the second storage transistor and the first global data line, and a gate of the second write transistor is coupled to a second write word line, and
- wherein a source and drain of the second storage transistor and a source and drain of the second read transistor are coupled in series between the second data line and the first potential, and a gate of the second read transistor is coupled to a second read word line.
32. A semiconductor integrated circuit according to claim 29,
- wherein each of the plurality of first memory blocks further includes a third data line coupled to the plurality of first memory cells,
- wherein each of the plurality of second memory blocks further includes a fourth data line coupled to the plurality of second memory cells,
- wherein each of the plurality of first memory cells has a first storage transistor, a first read transistor, and a first write transistor,
- wherein a source and drain of the first write transistor are coupled between a gate of the first storage transistor and the third data line, and a gate of the first write transistor is coupled to a first word line,
- wherein a source and drain of the first storage transistor and a source and drain of the first read transistor are coupled in series between the first data line and a first potential, and a gate of the first read transistor is coupled to the first word line,
- wherein each of the plurality of second memory cells has a second storage transistor, a second read transistor, and a second write transistor,
- wherein a source and drain of the second write transistor are coupled between a gate of the second storage transistor and the fourth data line, and a gate of the second write transistor is coupled to a second word line, and
- wherein a source and drain of the second storage transistor and a source and drain of the second read transistor are coupled in series between the second data line and the first potential, and a gate of the second read transistor is coupled to the second word line.
33. A semiconductor integrated circuit according to claim 29,
- wherein each of the plurality of first memory blocks further includes a third data line coupled to the plurality of first memory cells,
- wherein each of the plurality of second memory blocks further includes a fourth data line coupled to the plurality of second memory cells,
- wherein each of the plurality of first memory cells has a first storage transistor, a first read translator, and a first write transistor,
- wherein a source and drain of the first write transistor are coupled between a gate of the first storage transistor and the third data line, and a gate of the first write transistor is coupled to a first write word line,
- wherein a source and drain of the first storage transistor and a source and drain of the first read transistor are coupled in series between the first data line and a first potential, and a gate of the first read transistor is coupled to a first read word line,
- wherein each of the plurality of second memory cells has a second storage transistor, a second read transistor, and a second write transistor,
- wherein a source and drain of the second write transistor are coupled between a gate of the second storage transistor and the fourth data line, and a gate of the second write transistor is coupled to a second write word line, and
- wherein a source and drain of the second storage transistor and a source and drain of the second read transistor are coupled in series between the second data line and the first potential, and a gate of the second read transistor is coupled to a second read word line.
34. A semiconductor integrated circuit according to claim 26,
- wherein the first global data line crosses the second global data line.
35. A semiconductor integrated circuit according to claim 34, further comprising:
- a second global data line pair including a third global data line and a fourth global data line;
- a second sense amplifier coupled between the third global data line and the fourth global data line;
- a plurality of third memory blocks each including a third data line, a plurality of third memory cells coupled to the third data line, and a third switch coupled between the third data line and the third global data line; and
- a plurality of fourth memory blocks each including a fourth data line, a plurality of fourth memory cells coupled to the fourth data line, and a fourth switch coupled between the fourth data line and the fourth global data line,
- wherein the number of the third switches is the same as the number of the fourth switches;
- wherein the third global data line crosses the fourth global data line, and
- wherein a number of cross-points of the first and second global data lines is larger than a number of cross-points of the third and fourth global data lines.
Type: Application
Filed: Nov 3, 2004
Publication Date: Apr 28, 2005
Applicant:
Inventors: Yusuke Kanno (Hachiouji), Kiyoo Itoh (Hagashikurume)
Application Number: 10/979,124