Driving circuit and driving method of active matrix organic electro-luminescence display
The invention relates to the driving circuit and method of an active matrix organic electro-luminescence display. The writing thin film transistor (TFT) gates of all pixels on the scan line are connected to the scan line. The resetting TFT gates of all pixels on the scan line are connected to the front scan line of the previous row. The switching TFT gates of all pixels within the driving block are connected to the block control line of the driving block. The above block division control and pixel driving circuit design can be used to present gray scale by modulating the display time-ratio. This invention makes use of block separation control and pixel driving circuit design to improve the defect of the timing-inefficiency of the existing digital driving technology tremendously.
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This invention relates to the driving circuit and driving method of an active matrix organic electro-luminescence display. More particularly, the invention is directed to improve the defect of the timing-inefficiency of the well-known digital driving scheme.
BACKGROUND OF THE INVENTIONOrganic electro-luminescence (OEL) displays can be divided into passive matrix type and active matrix type according to the driving method. The so-called active matrix organic light-emitting displays (AMOLED) is to use the thin film transistor (TFT) and the capacitor to store image signals and control the luminance and gray scale of OLED.
Though the manufacturing cost is lower and the technology is common for passive matrix OLED; however, the resolution of the panel can't be enhanced due to its driving method. Therefore, the size of the applied products is limited less than 5 inches, which is confined to low resolution and small size market. The active matrix driving method needs to be applied for finer and larger screens. The so-called active matrix means to store image signals by capacitors. Thus, the original brightness of pixels can be maintained after scanning. In this way, extreme brightness of OLED is not needed, longer operation life is guaranteed and requirements for high resolution can be achieved. Active matrix OLED can be put into practice by combining OLED and TFT technology, which not only meets stricter requirements for smoothness and resolution on the monitor market, but also reveals the superb features of OLED to the full extent.
For driving technology at present, development of AMOLED has two directions; one is the analog method and the other one is the digital way. The reason why digital driving is developed is because TFT elements with excellent features (e.g. threshold voltage and mobility) can't be produced through the current LTPS process. Nevertheless, the stringent demands for LTPS process are not required for digital driving since the image non-uniformity due to the characteristic variation of TFT elements can be compensated merely through a simple 2T1C driving circuit.
As a result, digital driving technology will play a certain role in the development of AMOLED in the future if shortcomings of digital driving method can be corrected efficiently and the integrated driving system can be established.
For the application of digital driving technology at the moment, time-ratio and area-ratio modulation methods are used for gray scale. Take the U.S. Pat. No. 6,452,341 as an example for time-ratio technology. It is based on the separation structure of a writing time 61 and a display time 62 (Program Display Separation) for the realization of digital driving scheme. As
For instance, refer to the U.S. Pat. No. 6,452,341 as
This flaw is acceptable for small size applications; however, this problem needs to be overcome for large size or higher resolution requirement in the future. To promote application of digital driving technology, certain solutions are required to correct the defect of low time utility rate of the conventional driving scheme—program display separation.
One of the solutions is to increase the operating frequency, including scanning frequency and data shifting frequency, etc. This method has no problems for earlier display system that uses external driving IC; however, the solution of built-in driving circuit LTPS-TFT adopted to cope with the development trend of system-on-glass (SOG) cannot easily support very high frequency operation.
Japan Patent No. 2001-343933 discloses an AMOLED driving circuit.
The main purpose of this invention is to solve the aforementioned problems existed for a long time. This invention can be applied to LTPS-TFT with AMOLED device to improve the inefficient time utility rate of the original digital driving technology. Meanwhile, a set of scanning device can be shared for data write scan and erase scan through this invention so that the number of elements required for the existing scan circuit technology can be reduced (two sets of scan drivers required, but only one set required for this invention), which benefits reduction of manufacturing cost.
To achieve the said goal, this invention divides the display panel into k driving blocks. The driving circuit of each pixel consists of a Writing TFT, a Switching TFT, a Resetting TFT, a Driving TFT, a Storage Capacitance, an Organic Electro-luminescence Element, a Scan Line, a Data Line, a Supply Line, a Block Control Line and a Start-Erase Line.
The gate of the writing TFT on the scan line is connected to the scan line. The gate of the resetting TFT gates is connected to the front scan line. The gate of switching TFT within the driving block is connected to the block control line of the driving block.
Furthermore, sequences of the operations of a driving circuit can be divided into (1) Data Reset Time, (2) Data Write Time, (3) Data Display Phase 301 and (4) Data Erase Phase 302. The above block division control and pixel driving circuit design can be used to generate the gray scale by modulating the display time-ratio. In every sub-frame, data resetting and data writing are conducted in order from the first to the last scan line. After that, pixels on the scan line are ready to display. Compare with the driving structure of the well-known driving scheme—“Program Display Separation”. When the system works at the same scan frequency of 120 KHz, the time utility rate of Program Display Separation only accounts for 40%; however, that of this invention can be up to 78.75%, which improves the defect of timing-inefficiency tremendously.
This invention makes use of block separation control and pixel driving circuit design to put digital driving of AMOELD into practice.
BRIEF DESCRIPTION OF THE DRAWINGS
A description of the content and the technology of this invention along with drawings are made in detail as follows:
Refer to
Refer to
The display circuit comprises several scan lines 121 S1˜Sn. Gates of Writing TFT 101 of all pixels are connected to Scan Line 121. The drain of Writing TFT 101 and Data Line 122 are connected to each other.
The drain of switching TFT 102 is connected to the source of writing TFT 101 and the gate is connected to the Block Control Line 124.
The drain of resetting TFT 103 is connected to the source of switching TFT 102. The source is connected to supply line 123 and the gate is connected to the front scan line 130. The only exception is the gate of resetting TFT 103 on the first scan line 121 (S1) is connected to Start-Erase Line 210 (See
Storage Capacitance 105 has two ends. One of them is connected to supply line 123 and the other is connected to the joint where the source of switching TFT 102 and the drain of resetting TFT 103 meet.
The source of driving TFT 104 is connected to supply line 123 and the gate is connected to the joint where the source of switching TFT 102 and the drain of resetting TFT 103 meet.
The positive electrode of organic electro-luminescence element 106 is connected to the drain of driving TFT 104 and the negative electrode is grounded.
The operation of the circuit for this invention is described as follows. Driving sequences of this invention can be divided into (1) Data Reset Time, (2) Data Write Time, (3) Data Display Phase 301 and (4) Data Erase Phase 302. Explanations are as the following (See
(1) Data Reset Time:
Resetting TFT 103 of all pixels on scan line 121 is turned on by the control signal of the front scan line 130. Electric charges of storage capacitance 105 will be erased once again to ensure there's no voltage difference between both ends of storage capacitance 105. At the same time, writing TFT 101 is in OFF state and switching TFT 102 is ON. As writing TFT 101 and switching TFT 102 are series connected and writing TFT 101 is OFF, data voltage signals on data line 122 can't be inputted into storage capacitance 105 despite switching TFT 102 is ON.
(2) Data Write Time:
The control signal of the front scan line 130 makes resetting TFT 103 of all pixels on scan line 121 OFF and the control signal of scan line 121 turns on writing TFT 101 of all pixels on scan line 121. As switching TFT 102 of all pixels is ON at this moment, data voltage signals on each data line 122 can be inputted into the corresponding storage capacitance 105.
(3) Data Display Phase 301:
The control signal of the front scan line 130 makes resetting TFT 103 of all pixels on scan line 121 OFF and the control signal of scan line 121 turns off writing TFT 101 of all pixels on scan line 121. Though switching TFT 102 is ON, the storage capacitance 105 of each pixel can hold data voltage signals inputted during data write because the writing TFT 101 is off. Current of the driving TFT 104 of every pixel is determined by the voltage between both ends of storage capacitance 105. When the current of driving TFT 104 passes through the organic electro-luminescence element 106, the corresponding brightness will be generated.
(4) Data Erase Phase 302:
The control signal of block control line 124 makes switching TFT 102 of all pixels within the driving block OFF and the control signal of the front scan line 130 turns on the resetting TFT 103 of all pixels on scan line 121. When the resetting TFT 103 is turned on, electric charges of storage capacitance 105 will be erased, which makes the voltage difference between two ends of storage capacitance 105 become zero. As a result, the current of driving TFT 104 of all pixels on scan line 121 decreases to zero. Consequently, the organic electro-luminescence element 106 on scan line 121 stops illuminating.
As switching TFT 102 is OFF and writing TFT 101 and switching TFT 102 are series connected, the data voltage signal of data line 122 can not be inputted into the storage capacitance 105 even the control signal of the scan line 121 will turn on the writing TFT 101 of all pixels on scan line 121.
Refer to
One thing to be noticed is: the length of time of certain sub-frame data display phase 301 on some scan lines comes to an end; however, certain scan lines 121 do not finish data resetting and data writing of that sub-frame yet due to the limitation of scan frequency. Therefore, the scan line which has finished data display phase 301 has to start data erase phase 302.
Take the first sub-frame (SF1) in
At t2, the last scan line 121 (S30) in the first driving block (Block-1) finishes data resetting and data writing for the first sub-frame (SF1). Starting from t2, block control line 124 (BCL-1) sends control signals to turn off the switching TFT 102 of all pixels in every scan line 121 within the first block (Block-1) and erase scan signal is sent from the start-erase line 210 so that data erasing of the first sub-frame (SF1) will be conducted in order from the first scan line (S1) to the last scan line (S30). One point that has to be emphasized is that since erase scan signals of scan line 121 also turn on writing TFT 101 on scan line 121, data voltage signals can be prevented from being inputted into the storage capacitance 105 due to turning off the switching TFT 102 by block control line 124 (BCL-1). When the last scan line (S30) in the first driving block (Block-1) completes data erase phase 302 for the first sub-frame (SF1) at t3, block control line 124 (BCL-1) will shift control signals to block control line 124 (BCL-2).
At t3, control signals of block control line 124 (BCL-2) make the switching TFT 102 of all pixels in every scan line 121 within the second driving block (Block-2) off and erase scan signals transmitted from the last scan line in the first block (Block-1) motivate scan line 121 in the second block (Block-2) to conduct data erase phase 302 of the first sub-frame (SF1). When the last scan line 121 (S60) in the second driving block (Block-2) completes data erase phase 302 of the first sub-frame (SF1), block control line 124 (BCL-2) will shift control signals to block control line 124 (BCL-3).
At t4, the last scan line in the last driving block (Block-8) finishes data resetting and data writing of the first sub-frame (SF1). Starting from t4, data resetting and data writing of the second sub-frame will be conducted in order from the first scan line 121 (S1) to the last scan line 121 (S30). Meanwhile, control signals shifted from the previous block control line 124 (BCL-7) will appear on the last block control line 124 (BCL-8) at t4. Thus, control signals of the last block control line 124 (BCL-8) make the switching TFT 102 of all pixels on every scan line 121 in the last block (Block-8) off. Whereas, erase scan signals transmitted from the last scan line 121 (S210) in the previous block control line 124 (BCL-7) will motivate scan line 121 in the last block (Block-8) to conduct data erase phase 302 of the first sub-frame (SF1) in order.
Based on the explanation above, we may say the quantity k of block control line 124 (i.e. the number of blocks divided) equals to the sum of the length of data display phase 301 (t2−t1) of the first sub-frame and the length of data erase phase 302 (t4−t2) of the first sub-frame divided by the length of data display phase 301 (t2−t1) of the first sub-frame, which is shown as k=[(t4−t1)/(t2−t1)].
The second sub-frame (SF2) in
Frame time required for driving by this invention is (8T+8T+8T+8T+16T+32T)=80T as shown in
Compare with the driving structure of the well-known driving scheme—“Program Display Separation”. When the system works at the same scan frequency of 120 KHz, the time utility rate of Program Display Separation only accounts for 40%; however, that of this invention can be up to 78.75%, which improves the defect of timing-inefficiency tremendously.
To sum up, only one set of scanning device is required for data-write scan and data-erase scan while applying this invention, which not only decreases the number of elements needed for a scan circuit in the technology in practice (2 sets of scan drivers required for the prior art, but only 1 set is needed for this invention), but also reduces the manufacturing cost.
In addition, this invention makes use of block separation control and pixel driving circuit design to put digital driving of AMOELD into practice.
Claims
1. A driving circuit can drive an active matrix organic electro-luminescence display panel which is composed of pixels arranged in columns and rows; columns of pixels are divided as a block controlled by the block control line; the driving circuit of each pixel consists of:
- A writing TFT having a gate connected to a scan line and having a drain connected to a data line;
- A switching TFT having a drain connected to the source of the writing TFT and having a gate connected to the block control line;
- A resetting TFT having a drain connected to the source of the switching TFT and having a source connected to a supply line and a gate connected to the front scan line, wherein the gate of resetting TFT of all pixels on the first scan line is connected to a Start-Erase Line;
- A storage capacitance with one end connected to the supply line and another end connected to the joint where the source of switching TFT meets the drain of resetting TFT;
- A driving TFT whose source connected to the supply line. Its gate, the same as one end of storage capacitance is connected to the joint where the source of switching TFT and the drain of resetting TFT meet;
- An organic electro-luminescence element with the positive electrode connected to the drain of the driving TFT and the negative electrode grounded.
2. For the driving circuit of a first said active matrix organic electro-luminescence display in Item 1, the number of block control lines is determined by the addition of the length of data display phase of the first sub-frame and the length of data erase phase of the first sub-frame, which is divided by the data display phase of the first sub-frame.
3. Sequences of driving an AMOLED for this invention can be divided into data resetting, data writing, data displaying and data erasing with explanations in detail as follows:
- Data Reset Time: Control signals from the scan line of the previous row will turn on the resetting TFT of all pixels on the scan line of the current row and electric charges inside the storage capacitance will be erased once again to ensure there is no voltage difference between both ends of storage capacitance.
- Data Write Time: Control signals from the scan line of the previous row will turn off the resetting TFT of all pixels on the scan line and control signals from the scan line of the current row will turn on the writing TFT of all pixels on the scan line on, as the switching TFT of all pixels is on, data voltage signals on each data line can be inputted into the corresponding storage capacitance.
- Data Display Phase: Control signals from the scan line of the previous row will turn off the resetting TFT of all pixels on the scan line of the row and control signals from the scan line of the current row will turn off the writing TFT of all pixels on the scan line of the current row. As data voltage signals on the data line can't be inputted into the storage capacitance, such signals stored during data write in every pixel will be held, as a result, TFT driving current of each pixel will be decided by the voltage stored on both ends of storage capacitance and brightness of the organic electro-luminescence element will be generated in accordance with the current passed.
- Data Erase Phase: Control signals from the block control line will turn off the switching TFT of all pixels in that driving block and the control signals from the scan line of the previous row will turn on the resetting TFT of all pixels on the scan line of the current row, an activated resetting TFT will remove electric charges inside the storage capacitance, which leads to no voltage difference between two ends of storage capacitance, consequently, TFT driving current of all pixels on the scan line of the present row turns to zero, which causes the organic electro-luminescence element on the scan line of the row to stop illuminating.
Type: Application
Filed: Nov 1, 2003
Publication Date: May 5, 2005
Patent Grant number: 7126566
Applicant:
Inventor: Shin-Tai Lo (Miaoli City)
Application Number: 10/699,558