Drive circuit for el display panel
To provide a source driver circuit for an EL display panel with reduced variations in output current. A source driver circuit contains unit transistors 634 each of which constitutes a single unit. The 0th bit consists of one unit transistor 634, the 1st bit consists of two unit transistors 634, the 2nd bit consists of four unit transistors 634, the 3rd bit consists of eight unit transistors 634, the 4th bit consists of 16 unit transistors 634, and the 5th bit consists of 32 unit transistors 634. Each unit transistor 634 composes a current mirror circuit in conjunction with a transistor 633a. Regulating the current Ib flowing through the transistor 633a allows for changing the current flowing through the unit transistors 634. Accurate source driver IC with small variations can be provided by configuring output current circuits with unit transistors and regulating reference currents so that the output current of the unit transistors can be regulated.
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The present invention relates to a self-luminous display panel such as an EL display panel which employs organic or inorganic electroluminescent (EL) elements as well as to a drive circuit (IC) for the display panel. Also, it relates to an information display apparatus and the like which employ the EL display panel, a drive method for the EL display panel, and the drive circuit for the EL display panel.
BACKGROUND ARTGenerally, active-matrix display apparatus display images by arranging a large number of pixels in a matrix and controlling the light intensity of each pixel according to a video signal. For example, if liquid crystals are used as an electrochemical substance, the transmittance of each pixel changes according to a voltage written into the pixel. With active-matrix display apparatus which employ an organic electroluminescent (EL) material as an electrochemical substance, emission brightness changes according to current written into pixels.
In a liquid crystal display panel, each pixel works as a shutter, and images are displayed as a backlight is blocked off and revealed by the pixels or shutters. An organic EL display panel is of a self-luminous type in which each pixel has a light-emitting element. Consequently, organic EL display panels have the advantages of being more viewable than liquid crystal display panels, requiring no backlighting, having high response speed, etc.
Brightness of each light-emitting element (pixel) in an organic EL display panel is controlled by an amount of current. That is, organic EL display panels differ greatly from liquid crystal display panels in that light-emitting elements are driven or controlled by current.
A construction of organic EL display panels can be either a simple-matrix type or active-matrix type. It is difficult to implement a large high-resolution display panel of the former type although the former type is simple in structure and inexpensive. The latter type allows a large high-resolution display panel to be implemented, but involves a problem that it is a technically difficult control method and is relatively expensive. Currently, active-matrix type display panels are developed intensively. In the active-matrix type display panel, current flowing through the light-emitting elements provided in each pixel is controlled by thin-film transistors (transistors) installed in the pixels.
Such an organic EL display panel of an active-matrix type is disclosed in Japanese Patent Laid-Open No. 8-234683. An equivalent circuit for one pixel of the display panel is shown in
The organic EL element 15, in many cases, may be referred to as an OLED (organic light-emitting diode) because of its rectification. In
Incidentally, the EL element 15 according to the present specification is not limited to an OLED. It may be of any type as long as its brightness is controlled by the amount of current flowing through the element 15. Examples include an inorganic EL element, a white light-emitting diode consisting of a semiconductor, atypical light-emitting diode, and a light-emitting transistor. Rectification is not necessarily required of the EL element 15. Bidirectional diodes are also available. The EL element 15 according to the present specification may be any of the above elements.
In the example of
To drive the pixel 16, a video signal which represents brightness information is first applied to the source signal line 18 with the gate signal line 17a selected. Then, the transistor 11a conducts, the storage capacitance 19 is charged or discharged, and gate potential of the transistor 11b matches the potential of the video signal. When the gate signal line 17a is deselected, the transistor 11a is turned off and the transistor 11b is cut off electrically from the source signal line 18. However, the gate potential of the transistor 11a is maintained stably by the storage capacitance (capacitor) 19. Current delivered to the EL element 15 via the transistor 11a depends on gate-source voltage Vgs of the transistor 11a and the EL element 15 continues to emit light at an intensity which corresponds to the amount of current supplied via the transistor 11a.
Since liquid crystal display panels are not self-luminous devices, there is a problem that they cannot display images without backlighting. Also, there has been a problem that a certain thickness is required to provide a backlight, which makes the display panel thicker. Besides, to display colors on a liquid crystal display panel, color filters must be used. Therefore, there has been a problem of the lowered usability of light. Also, there has been the problem of narrow color reproduction range.
Organic EL display panels are made of low-temperature polysilicon transistor arrays. However, since organic EL elements use current to emit light, there has been a problem that variations in the characteristics of the transistors will cause display irregularities.
The display irregularities can be reduced using current programming of pixels. For current programming, a current-driven driver circuit is required. However, with a current-driven driver circuit, variations will also occur in transistor elements which compose a current output stage. This in turn causes variations in gradation output currents from output terminals, making it impossible to display images properly.
DISCLOSURE OF THE INVENTIONTo achieve this object, a driver circuit for an EL display panel (EL display apparatus) according to the present invention comprises a plurality of transistors which output unit currents and produces an output current by varying the number of transistors. Also, the driver circuit is characterized by comprising a multi-stage current mirror circuit. A transistor group which delivers signals via voltages is formed densely. Also, signals are delivered between the transistor group and current mirror circuit group via currents. Besides, reference currents are produced by a plurality of transistors.
A first invention of the present invention is a driver circuit for an EL display panel comprising:
-
- reference current generating means of generating a reference current;
- a first current source which is fed the reference current from the reference current generating means and outputs a first current which corresponds to the reference current to a plurality of second current sources;
- the second current sources which are fed the first current outputted from the first current source and output a second current which corresponds to the first current to a plurality of third current sources; and
- the third current sources which are fed the second current outputted from the second current sources and output a third current which corresponds to the second current to a plurality of fourth current sources,
- characterize in that among the fourth current sources, an appropriate number of unit current sources are selected according to input image data.
A second invention of the present invention is a driver circuit for an EL display panel comprising:
-
- a plurality of current generator circuits each of which has unit transistors equal in number to a power of two;
- switch circuits connected to the respective current generator circuits;
- internal wiring connected to output terminals; and
- a control circuit which turns on and off the switch circuits according to input data,
- wherein one end of each switch circuit is connected to the current generator circuit and the other end is connected to the internal wiring.
A third invention of the present invention is the driver circuit for an EL display panel according to the second invention of the present invention, wherein:
-
- channel width W of the unit transistors is from 2 to 9 μm both inclusive, and
- size (WL) of the transistors is 4 square μm or more.
A fourth invention of the present invention is the driver circuit for an EL display panel according to the second invention of the present invention, wherein:
-
- a ratio of channel length L to the channel width W of the unit transistors is two or larger; and
power supply voltage used is between 2.5 V and 9 V both inclusive.
A fifth invention of the present invention is a driver circuit for an EL display panel comprising:
-
- a first output current circuit consisting of a plurality of unit transistors which pass a first unit current;
- a second output current circuit consisting of a plurality of unit transistors which pass a second unit current; and
- an output stage which produces an output by adding an output current of the first output current circuit and an output current of the second output current circuit,
- wherein the first unit current is smaller than the second unit current,
- the first output current circuit operates in a low gradation region and a high gradation region according to gradations, and
- the second output current circuit operates in the high gradation region according to gradations, and output current values of the first output current circuit do not change in the high gradation region when the second output current circuit operates.
A sixth invention of the present invention is a driver circuit for an EL display panel comprising:
-
- a programming current generator circuit which has a plurality of unit transistors corresponding to output terminals;
- first transistors which generate a first reference current which defines a current flowing through the unit transistors;
- gate wiring connected to gate terminals of the plurality of first transistors; and
- a second and third transistors whose gate terminals are connected to the gate wiring and which form current mirror circuits in conjunction with the first transistors,
- wherein a second reference current is supplied to the second and third transistors.
A seventh invention of the present invention is the driver circuit for an EL display panel according to the sixth invention of the present invention, comprising:
-
- a programming current generator circuit which has a plurality of unit transistors corresponding to output terminals;
- a plurality of first transistors which form current mirror circuits in conjunction with the unit transistors; and
- a second transistor which generates a reference current flowing through the first transistors,
- wherein the reference current generated by the second transistor branches through the plurality of first transistors.
An eighth invention of the present invention is the driver circuit for an EL display panel according to the sixth or seventh invention of the present invention, wherein in a driver IC chip which includes the driver circuit, the third transistor is electrically connected, in an area in which the first reference current supply wirings are placed, to two outermost placed wirings of the reference current supply wiring group placed in the area.
A ninth invention of the present invention is an EL display apparatus comprising:
-
- a first substrate on which driver transistors are placed in a matrix and which contains a display area consisting of EL elements formed corresponding to the driver transistors;
- a source driver IC which applies a programming current or voltage to the driver transistors;
- a first wiring formed on the first substrate located under the source driver IC;
- a second wiring electrically connected to the first wiring and formed between the source driver IC and the display area; and
- anode wiring which branches from the second wiring and applies an anode voltage to pixels in the display area.
A tenth invention of the present invention is the EL display apparatus according to the ninth invention of the present invention, wherein the first wiring has a light shielding function.
An eleventh invention of the present invention is an EL display apparatus comprising:
-
- a display area where pixels with EL elements are formed in a matrix;
- driver transistors which supply light-emitting current to the EL elements; and
- a source driver circuit which supplies programming current to the driver transistors,
- wherein the driver transistors are P-channel transistors, and
- transistors which generate the programming current in the source driver circuit are N-channel transistors.
A twelfth invention of the present invention is an EL display apparatus comprising:
-
- a display area where EL elements, driver transistors which supply light-emitting current to the EL elements, first switching elements which form paths between the driver transistors and the EL elements, and second switching elements which form paths between the driver transistors and source signal lines are formed in a matrix;
- a first gate driver circuit which performs on/off control of the first switching elements;
- a second gate driver circuit which performs on/off control of the second switching elements;
- a source driver circuit which applies video signals to the transistor elements; and
- a source driver circuit which supplies programming current to the driver transistors,
- wherein the driver transistors are P-channel transistors, and
- transistors which generate the programming current in the source driver circuit are N-channel transistors.
A thirteenth invention of the present invention is an EL display apparatus comprising:
-
- EL elements;
- P-channel driver transistors which supply light-emitting current to the EL elements;
- switching transistors formed between the EL elements and the driver transistors;
- a source driver circuit which supplies programming current;
- and gate driver circuits which keep the switching transistors off for two horizontal scanning periods or longer in one frame period.
- 11 Transistor (thin-film transistor)
- 12 Gate driver IC (circuit)
- 14 Source driver IC (circuit)
- 15 EL (element) (light-emitting element)
- 16 Pixel
- 17 Gate signal line
- 18 Source signal line
- 19 Storage capacitance (additional capacitor, additional capacitance)
- 50 Display screen
- 51 Write pixel (row)
- 52 Non-display pixel (non-display area, non-illuminated area)
- 53 Display pixel (display area, illuminated area)
- 61 Shift register
- 62 Inverter
- 63 Output buffer
- 71 Array board (display panel)
- 72 Laser irradiation range (laser spot)
- 73 Positioning marker
- 74 Glass substrate (array board)
- 81 Control IC (circuit)
- 82 Power supply IC (circuit)
- 83 Printed board
- 84 Flexible board
- 85 Sealing lid
- 86 Cathode wiring
- 87 Anode wiring (Vdd)
- 88 Data signal line
- 89 Gate control signal line
- 101 Bank (rib)
- 102 Interlayer insulating film
- 104 Contact connector
- 105 Pixel electrode
- 106 Cathode electrode
- 107 Desiccant
- 108 λ/4 plate
- 109 Polarizing plate
- 111 Thin encapsulation film
- 281 Dummy pixel (row)
- 341 Output stage circuit
- 371 OR circuit
- 401 Illumination control line
- 471 Reverse bias line
- 472 Gate potential control line
- 561 Electronic regulator circuit
- 562 SD (source-drain) short circuit of a transistor
- 571 Antenna
- 572 Key
- 573 Housing
- 574 Display panel
- 581 Eye ring
- 582 Magnifying lens
- 583 Convex lens
- 591 Supporting point (pivot point)
- 592 Taking lens
- 593 Storage section
- 594 Switch
- 601 Body
- 602 Photographic section
- 603 Shutter switch
- 611 Mounting frame
- 612 Leg
- 613 Mount
- 614 Fixed part
- 631 Current source
- 632 Current source
- 633 Current source
- 641 Switch (on/off means)
- 634 Current source (single unit)
- 643 Internal wiring
- 651 Regulator (current regulating means)
- 681 Transistor group
- 691 Resistor (current limiting means, predetermined-current generating means)
- 692 Decoder circuit
- 693 Level shifter circuit
- 701 Counter (counting means)
- 702 NOR
- 703 AND
- 704 Current output circuit
- 711 Padder circuit
- 721 D/A converter
- 722 Operational amplifier
- 731 Analog switch (on/off means)
- 732 Inverter
- 761 Output pad (output signal terminal)
- 771 Reference current source
- 772 Current control circuit
- 781 Temperature detection circuit
- 782 Temperature control circuit
- 931 Cascade current connection line
- 932 Reference current signal line
- 941i Current input terminal
- 941o Current output terminal
- 951 Base anode line (anode voltage line)
- 952 Anode wiring
- 953 Connection terminal
- 961 Connection anode line
- 962 Common anode line
- 971 Contact hole
- 991 Base cathode line
- 992 Input signal line
- 1001 Connection resin (conductive resin, anisotropic conductive resin)
- 1011 Light absorbing film
- 1012 Resin bead
- 1013 Sealing resin
- 1021 Circuit forming section
- 1051 Gate voltage line
- 1091 Power supply circuit (IC)
- 1092 Power supply IC control signal
- 1093 Gate driver circuit control signal
- 1111 Unit gate output circuit
- 1241 Adjusting transistor
- 1251 Cutting site
- 1252 Common terminal
- 1341 Dummy transistor
- 1351 Transistor (single-unit transistor)
- 1352 Sub-transistor
- 1401 Switching circuit (analog switch)
- 1491 Flash memory (setting storage means)
- 1501 Laser device
- 1502 Laser light
- 1503 Resistor array (adjustment resistor)
- 1521 Switch (on/off means)
- 1531 Steady-state transistor
- 1541 NAND circuit
- 1601 Capacitor
- 1611 Sleep switch (on/off control means, reference current on/off means)
- 1671 Protective diode
- 1731 Coincidence circuit (gradation detection circuit)
- 1741 Output switching circuit
- 1742 Changeover switch
- 1821 Anode connection circuit
- 2011 Coil (transformer)
- 2012 Control circuit
- 2013 Diode
- 2014 Capacitor
- 2021 Switch
- 2022 Temperature sensor
- 2041 Level shifter circuit
- 2042 Gate driver control signal
- 2061 Bonding layer (connection layer, heat conduction layer, and adhesion layer)
- 2062 Chassis (Metal chassis)
- 2063 Projections and depressions
- 2071 Hole
- 2211 Control electrode
- 2212 Video signal circuit
- 2213 Electron emission protuberance
- 2214 Holding circuit
- 2215 On/off control circuit
- 2221 Selection signal line
- 2222 On/off signal line
- 2281 Sealing resin
Some parts of drawings herein are omitted and/or enlarged/reduced herein for ease of understanding and/or illustration. For example, in a sectional view of a display panel shown in
Incidentally, what is described with reference to drawings or the like can be combined with other examples or the like even if not noted specifically. For example, a touch panel or the like can be attached to a display panel in
Also, thin-film transistors are cited herein as driver transistors 11 and switching transistors 11, this is not restrictive. Thin-film diodes (TFDs) or ring diodes may be used instead. Also, the present invention is not limited to thin-film elements, and transistors formed on silicon wafers may also be used. In this case, a board 71 can be made of a silicon wafer. Needless to say, FETs, MOS-FETs, MOS transistors, or bipolar transistors may also be used. They are basically, thin-film transistors. It goes without saying that the present invention may also use varistors, thyristors, ring diodes, photodiodes, phototransistors, or PLZT elements. That is, the transistor 11, gate driver circuit 12, and source driver circuit 14 according to the present invention can use any of the above elements.
An EL panel according to the present invention will be described below with reference to drawings. As shown in
Preferably, the metal electrode 106 is made of metal with a small work function, such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy thereof. In particular, it is preferable to use, for example, an Al—Li alloy. The transparent electrodes 105 may be made of, conductive materials with a large work function such as ITO, or gold and the like. If gold is used as an electrode material, the electrodes become translucent. Incidentally, IZO or other material may be used instead of ITO. This also applies to other pixel electrodes 105.
Incidentally, a desiccant 107 is placed in a space between the sealing lid 85 and array board 71. This is because the organic EL film 15 is vulnerable to moisture. The desiccant 107 absorbs water penetrating a sealant and thereby prevents deterioration of the organic EL film 15.
Although the sealing lid 85 is used for sealing in
Desirably, film thickness of the thin film is such that n·d is equal to or less than main emission wavelength λ of the EL element 15 (where n is the refraction factor of the thin film, or the sum of refraction factors if two or more thin films are laminated (n·d of each thin film is calculated); d is the film thickness of the thin film, or the sum of refraction factors if two or more thin films are laminated). By satisfying this condition, it is possible to more than double the efficiency of light extraction from the EL element 15 compared to when a glass substrate is used for sealing. Also, an alloy, mixture, or laminate of aluminum and silver may be used.
A technique which uses a thin encapsulation film 111 for sealing instead of a sealing lid 85 as described above is called thin film encapsulation. In the case of “underside extraction (see
In the case of “topside extraction (see
Half the light produced by the organic EL layer 15 is reflected by the metal electrode 106 and emitted through the array board 71. However, the metal electrode 106 reflects extraneous light, resulting in glare, which lowers display contrast. To deal with this situation, a λ/4 phase plate 108 and polarizing plate (polarizing film) 109 are placed on the array board 71. These are generally called circular polarizing plates (circular polarizing sheets).
Incidentally, if the pixels are reflective electrodes, the light produced by the organic EL layer 15 is emitted upward. Thus, needless to say, the phase plate 108 and polarizing plate 109 are placed on the side from which light is emitted. Reflective pixels can be obtained by making pixel electrodes 105 from aluminum, chromium, silver, or the like. Also, by providing projections (or projections and depressions) on a surface of the pixel electrodes 105, it is possible to increase an interface with the organic EL layer 15, and thereby increase the light-emitting area, resulting in improved light-emission efficiency. Incidentally, the reflective film which serves as the cathode 106 (anode 105) is made as a transparent electrode. If reflectance can be reduced to 30% or less, no circular polarizing plate is required. This is because glare is reduced greatly. Light interference is reduced as well.
Preferably, LDD (low doped drain) structure is used for the transistors 11. The EL elements will be described herein taking organic EL elements (known by various abbreviations including OEL, PEL, PLED, OLED) 15 as an example, but this is not restrictive and inorganic EL elements may be used as well.
An organic EL display panel of active-matrix type must satisfy two conditions: that it is capable of selecting a specific pixel and give necessary display information and that it is capable of passing current through the EL element throughout one frame period.
To satisfy the two conditions, in a conventional organic EL pixel configuration shown in
To display a gradation using this configuration, a voltage corresponding to the gradation must be applied the gate of the driver transistor 11a. Consequently, variations in a turn-on current of the driver transistor 11a appear directly in display.
The turn-on current of a transistor is extremely uniform if the transistor is monocrystalline. However, in the case of a low-temperature polycrystalline transistor formed on an inexpensive glass substrate by low-temperature polysilicon technology at a temperature not higher than 450, its threshold varies in a range of ±0.2 V to 0.5 V. The turn-on current flowing through the driver transistor 11a varies accordingly, causing display irregularities. The irregularities are caused not only by variations in the threshold voltage, but also by mobility of the transistor and thickness of a gate insulating film. Characteristics also change due to degradation of the transistor 11.
This phenomenon is not limited to low-temperature polysilicon technologies, and can occur in transistors formed on semiconductor films grown in solid-phase (CGS) by high-temperature polysilicon technology at a process temperature of 450 degrees (centigrade) or higher. Besides, the phenomenon can occur in organic transistors and amorphous silicon transistors.
As described below, the present invention provides a configuration or scheme which can accommodate the above technologies. Description will be given herein mainly of transistors produced by the low-temperature polysilicon technology.
In a method which displays gradations by the application of voltage as shown in
Each pixel structure in an EL display panel according to the present invention comprises at least four transistors 11 and an EL element as shown concretely in
When the gate signal line (first scanning line) 17a is activated (a turn-on voltage is applied), a current to be passed through the EL element 15 is delivered from the source driver circuit 14 via the driver transistor 11a and switching transistor 11c of the EL element 15. Also, upon activation of (application of a turn-on voltage to) the gate signal line 17a, the transistor 11b opens to cause a short circuit between gate and drain of the transistor 11a and gate voltage (or drain voltage) of the transistor 11a is stored in a capacitor (storage capacitance, additional capacitance) 19 connected between the gate and drain of the transistor 11a (see
Preferably, the capacitor (storage capacitance) 19 should be from 0.2 pF to 2 pF both inclusive. More preferably, the capacitor (storage capacitance) 19 should be from 0.4 pF to 1.2 pF both inclusive. The capacity of the capacitor 19 is determined taking pixel size into consideration. If the capacity needed for a single pixel is Cs (pF) and an area (rather than an aperture ratio) occupied by the pixel is Sp (square μm), a condition 500/Sp≦Cs≦20000/Sp, and more preferably a condition 1000/Sp≦Cs≦10000/Sp should be satisfied. Since gate capacity of the transistor is small, Q as referred to here is the capacity of the storage capacitance (capacitor) 19 alone.
The gate signal line 17a is deactivated (a turn-off voltage is applied), a gate signal line 17b is activated, and a current path is switched to a path which includes the first transistor 11a, a transistor 11d connected to the EL element 15, and the EL element 15 to deliver the stored current to the EL element 15 (see
In this circuit, a single pixel contains four transistors 11. The gate of the transistor 11a is connected to the source of the transistor 11b. The gates of the transistors 11b and 11c are connected to the gate signal line 17a. The drain of the transistor 11b is connected to the source of the transistor 11c and source of the transistor 11d. The drain of the transistor 11c is connected to the source signal line 18. The gate of the transistor 11d is connected to the gate signal line 17b and the drain of the transistor 11d is connected to the anode electrode of the EL element 15.
Incidentally, all the transistors in
Optimally, P-channel transistors should be used for all the transistors 11 composing pixels as well as for the built-in gate drivers 12. By composing an array solely of P-channel transistors, it is possible to reduce the number of masks to 5, resulting in low costs and high yields.
To facilitate understanding of the present invention, the configuration of the EL element according to the present invention will be described below with reference to
The second timing is the one when the transistor 11a and transistor 11c are closed and the transistor 11d is opened. The equivalent circuit available at this time is shown in
Results of this operation are shown in
In the pixel configuration in
During a period when the current flows through the EL element 15, the transistors 11c and 11b turn off and the transistor 11d turns on as shown in
A timing chart is shown in
As can be seen from
Incidentally, the gate of the transistor 11a and gate of the transistor 11c are connected to the same gate signal line 11a. However, the gate of the transistor 11a and gate of the transistor 11c may be connected to different gate signal lines 11 (see
By sharing the gate signal line 17a and gate signal line 17b and using different conductivity types (N-channel and P-channel) for the transistors 11c and 11d, it is possible to simplify the drive circuit and improve the aperture ratio of pixels.
With this configuration, a write paths from signal lines are turned off according to operation timing of the present invention That is, when a predetermined current is stored, an accurate current value is not stored in a capacitance (capacitor) between the source (S) and gate (G) of the transistor 11a if a current path is branched. By using different conductivity types for the transistors 11c and 11d and controlling their thresholds, it is possible to ensure that when scanning lines are switched, the transistor 11d is turned on after the transistor 11c is turned off.
In that case, however, since the thresholds of the transistors must be controlled accurately, it is necessary to pay attention to processes. The circuit described above can be implemented using four transistors at the minimum, but even if more than four transistors including a transistor 11e are cascaded for more accurate timing control or for reduction of mirror effect (described later), the principle of operation is the same. By adding the transistor 11e, it is possible to deliver programming current to the EL element 15 more precisely via the transistor 11c.
Incidentally, the pixel configuration according to the present invention is not limited to those shown in
In
A terminal b of the changeover switch 1401 is connected to cathode voltage (indicated as ground in
A terminal c of the changeover switch 1401 is connected with a cathode terminal of the EL element 15. Incidentally, the changeover switch 1401 may be of any type as long as it has a capability to turn on and off the current flowing through the EL element 15. Thus, its installation location is not limited to the one shown in
Also, the term “off” here does not mean a state in which no current flows, but it means a state in which the current flowing through the EL element 15 is reduced to below normal. The items mentioned above also apply to other configurations of the present invention.
The changeover switch 1401 will require no explanation because it can be implemented easily by a combination of P-channel and N-channel transistors. For example, it can be implemented by two circuits of analog switches. Of course, the changeover switch 1401 can be constructed of only P-channel or N-channel transistors because it only turns off the current flowing through the EL element 15.
When the changeover switch 1401 is connected to the terminal a, the Vdd voltage is applied to the cathode terminal of the EL element 15. Thus, current does not flow through the EL element 15 regardless of the voltage state of voltage held by the gate terminal G of the driver transistor 11a. Consequently, the EL element 15 is non-illuminated.
When the changeover switch 1401 is connected to the terminal b, the GND voltage is applied to the cathode terminal of the EL element 15. Thus, current flows through the EL element 15 according to the state of voltage held by the gate terminal G of the driver transistor 11a. Consequently, the EL element 15 is illuminated.
Thus, in the pixel configuration shown in
In the pixel configurations shown in
In
In the example shown in
Variations in the characteristics of the transistor 11a are correlated to the transistor size. To reduce the variations in the characteristics, preferably the channel length of the first transistor 11a is from 5 μm to 100 μm (both inclusive). More preferably, it is from 10 μm to 50 μm (both inclusive). This is probably because a long channel length L increases grain boundaries contained in the channel, reducing electric fields, and thereby suppressing kink effect.
Thus, according to the present invention, circuit means which controls the current flowing through the EL element 15 is constructed, formed, or placed on the path along which current flows into the EL element 15 and the path along which current flows out of the EL element 15 (i.e., the current path for the EL element 15).
Incidentally, the configuration for use to control the path along which current flows into the EL element 15 is not limited to the pixel configuration in current-programming mode shown in
Further, even in the case of current mirroring, a type of current programming, by forming or placing a transistor 11g as a switching element between the driver transistor 11b and EL element 15 as shown in
Incidentally, although the switching transistors 11d and 11c in
As shown in
An object of the present invention is to propose a circuit configuration in which variations in transistor characteristics do not affect display. Four or more transistors are required for that. When determining circuit constants using transistor characteristics, it is difficult to determine appropriate circuit constants unless the characteristics of the four transistors are not consistent. Both thresholds of transistor characteristics and mobility of the transistors vary depending on whether the channel direction is horizontal or vertical with respect to the longitudinal axis of laser irradiation. Incidentally, variations are more of the same in both cases. However, the mobility and average threshold vary between the horizontal direction and vertical direction. Thus, it is desirable that all the transistors in a pixel have the same channel direction.
Also, if the capacitance value of the storage capacitance 19 is Cs and the turn-off current value of the second transistor 11b is Ioff, preferably the following equation is satisfied.
3<Cs/Ioff<24
More preferably the following equation is satisfied.
6<Cs/Ioff<18
By setting the turn-off current of the transistor 11b to 5 pA or less, it is possible to reduce changes in the current flowing through the EL to 2% or less. This is because when leakage current increases, electric charges stored between the gate and source (across the capacitor) cannot be held for one field with no voltage applied. Thus, the larger the storage capacity of the capacitor 19, the larger the permissible amount of the turn-off current. By satisfying the above equation, it is possible to reduce fluctuations in current values between adjacent pixels to 2% or less.
Also, preferably transistors composing an active matrix are p-channel polysilicon thin-film transistors and the transistor 11b is a dual-gate or multi-gate transistor. As high an ON/OFF ratio as possible is required of the transistor 11b, which acts as a source-drain switch for the transistor 11a. By using a dual-gate or multi-gate structure for the transistor 11b, it is possible to achieve a high ON/OFF ratio.
The semiconductor films composing the transistors 11 in the pixel 16 are generally formed by laser annealing in low-temperature polysilicon technology. Variations in laser annealing conditions result in variations in transistor 11 characteristics. However, if the characteristics of the transistors 11 in the pixel 16 are consistent, it is possible to drive the pixel using current programming such as the one shown in
Incidentally, the semiconductor film formation according to the present invention is not limited to the laser annealing method. The present invention may also use a heat annealing method and a method which involves solid-phase (CGS) growth. Besides, the present invention is not limited to the low-temperature polysilicon technology and may use high-temperature polysilicon technology.
To deal with this problem, the present invention moves a laser spot (laser irradiation range) 72 in parallel to the source signal line 18 as shown in
Pixels are constructed in such a way that three pixels of RGB will form a square shape. Thus, each of the R, G, B pixels has oblong shape. Consequently, by performing annealing using an oblong laser spot 72, it is possible to eliminate variations in the characteristics of the transistors 11 within each pixel. Also, the characteristics (mobility, Vt, S value, etc.) of the transistors 11 connected to the same source signal line 18 can be made uniform (i.e., although the transistors 11 connected to adjacent source signal lines 18 may differ in characteristics, the characteristics of the transistors 11 connected to the same source signal line can be made almost equal).
In the configuration shown in
Preferably, the laser annealing method (which involves emitting a linear laser spot in parallel to the source signal line 18) described with reference to
For example, in the case of white raster display, since almost the same current is passed through the transistors 11a in adjacent pixels, the current outputted from the source driver IC 14 does not have significant amplitude changes. If the transistors 11a in
A method which involves programming two or more pixel rows simultaneously and which are described with reference to
Incidentally, although an IC chip is illustrated in
The present invention, in particular, ensures that a voltage threshold Vth2 of the driver transistor 11b will not fall below a voltage threshold Vth1 of the corresponding driver transistor 11a in the pixel. For example, gate length L2 of the transistor 11b is made longer than gate length L1 of the transistor 11a so that Vth2 will not fall below Vth1 even if process parameters of these thin-film transistors change. This makes it possible to suppress subtle current leakage.
Incidentally, the items mentioned above also apply to pixel configuration of a current mirror shown in
In
Next, the EL display panel or EL display apparatus of the present invention will be described.
Incidentally, the minimum output current of one current mirror circuit is from 10 nA to 50 nA (both inclusive). Preferably, the minimum output current of the current mirror circuit should be from 15 nA to 35 nA (both inclusive) to secure accuracy of the transistors composing the current mirror circuit in the source driver IC 14.
Besides, a precharge or discharge circuit is incorporated to charge or discharge the source signal line 18 forcibly. Preferably, voltage (current) output values of the precharge or discharge circuit which charges or discharges the source signal line 18 forcibly can be set separately for R, G, and B. This is because the thresholds of the EL element 15 differ among R, G, and B (regarding the precharge circuit refer to
Organic EL elements are known to have heavy temperature dependence (temperature characteristics). To adjust changes in emission brightness caused by the temperature characteristics, reference current is adjusted (varied) in an analog fashion by adding nonlinear elements such as thermistors or posistors to the current mirror circuits to vary output current and adjusting the changes due to the temperature characteristics with the thermistors or the like.
According to the present invention, the source driver 14 is made of a semiconductor silicon chip and connected with a terminal on the source signal line 18 of the board 71 by glass-on-chip (COG) technology. The source driver 14 can be mounted not only by the COG technology. It is also possible to mount the source driver circuit 14 by chip-on-film (COF) technology and connect it to the signal lines of the display panel. Regarding the driver IC, it may be made of three chips by constructing a power supply IC 82 separately.
Panel is tested before the source driver IC 14 is mounted. The test is conducted by applying a constant current to the source signal lines 18.
The constant current is applied by attaching lead wires 2271 to the pads 1522 formed on the ends of the source signal lines 18 and forming test pads 2272 on their ends as illustrated in
By forming the test pads 2272, it is possible to conduct the test without using the pads 1522.
After the source driver IC 14 is mounted on the substrate 71, its periphery is sealed with sealing resin 2281 as illustrated in
On the other hand, the gate driver circuit 12 is formed by low-temperature polysilicon technology. That is, it is formed in the same process as the transistors in pixels. This is because the gate driver 12 has a simpler internal structure and lower operating frequency than the source driver circuit 14. Thus, it can be formed easily even by low-temperature polysilicon technology and allows bezel width to be reduced. Of course, it is possible to construct the gate driver circuit 12 from a silicon chip and mount it on the board 71 using the COG technology. Also, switching elements such as pixel transistors as well as gate drivers may be formed by high-temperature polysilicon technology or may be formed of an organic material (organic transistors).
The gate driver 12 incorporates a shift register circuit 61a for a gate signal line 17a and a shift register circuit 61b for a gate signal line 17b. The shift register circuits 61 are controlled by positive-phase and negative-phase clock signals (CLKxP and CLKxN) and a start pulse (STx) (see
Since the shift register circuits 61 have small buffer capacity, they cannot drive the gate signal lines 17 directly. Therefore, at least two or more inverter circuits 62 are formed between each shift register circuit 61 and an output gate 63 which drives the gate signal line 17 (see
The same applies to cases in which the source driver 14 is formed on the board 71 by polysilicon technology such as low-temperature polysilicon technology. A plurality of inverter circuits are formed between an analog switching gate such as a transfer gate which drives the source signal line 18 and the shift register of the source driver circuit 14. The following matters (shift register output and output stages which drive signal lines (inverter circuits placed between output stages such as output gates or transfer gates) are common to the gate driver circuit and source driver circuit.
For example, although the output from the source driver 14 is shown in
The inverter circuit 62 consists of a P-channel MOS transistor and N-channel MOS transistor. As described earlier, the shift register circuit 61 of the gate driver circuit 12 has its output end connected with multiple stages of inverter circuits 62 and the final output is connected to the output gate 63. Incidentally, the inverter circuit 62 may be composed solely of P-channel MOS transistors. In that case, however, the circuit may be configured simply as a gate circuit rather than an inverter.
In
In
When the display panel is used for information display apparatus such as a cell phone, it is preferable to mount (form) the source driver IC (circuit) 14 and gate driver IC (circuit) 12 on one side of the display panel as shown in
Incidentally, the three-side free configuration includes not only a configuration in which ICs are placed or formed directly on the board 71, but also a configuration in which a film (TCP, TAB, or other technology) with a source driver IC (circuit) 14 and gate driver IC (circuit) 12 mounted are pasted on one side (or almost one side) of the board 71. That is, the three-side free configuration includes configurations and arrangements in which two sides are left free of ICs and all similar configurations.
If the gate driver circuit 12 is placed beside the source driver circuit 14 as shown in
Incidentally, the thick solid line in
Spacing between the gate signal lines 17 formed on the side C is from 5 μm to 12 μm (both inclusive). If it is less than 5 μm, parasitic capacitance will cause noise on adjacent gate signal lines. It has been shown experimentally that parasitic capacitance has significant effects when the spacing is 7 μm or less. Furthermore, when the spacing is less than 5 μm, beating noise and other image noise appear intensely on the display screen. In particular, noise generation differs between the right and left sides of the screen and it is difficult to reduce the beating noise and other image noise. When the spacing exceeds 12 μm, bezel width D of the display panel becomes too large to be practical.
To reduce the image noise, a ground pattern (conductive pattern which has been fixed at a constant voltage or set generally at a stable potential) can be placed under or above the gate signal lines 17. Alternatively, a separate shield plate (shield foil: a conductive pattern which has been fixed at a constant voltage or set generally at a stable potential) may be placed on the gate signal lines 17.
The gate signal lines 17 on the side C in
Incidentally, although it has been stated with reference to
Also, the source driver IC 14 and gate driver IC 12 may be integrated into a single chip. Then, it suffices to mount only one IC chip on the display panel. This also reduces implementation costs. Furthermore, this makes it possible to simultaneously generate various voltages for use in the single-chip driver IC.
Incidentally, although it has been stated that the source driver IC 14 and gate driver IC 12 are made of silicon or other semiconductor wafers and mounted on the display panel, this is not restrictive. Needless to say, they may be formed directly on the display panel 82 using low-temperature polysilicon technology or high-temperature polysilicon technology.
Although it has been stated that pixels are of the three primary colors of R, G, and B, this is not restrictive. They may be of three colors of cyan, yellow, and magenta. They may be of two colors of B and yellow. Of course, they may be monochromatic. Alternatively, they may be of six colors of R, G, B, cyan, yellow, and magenta or of five colors of R, G, B, cyan, and magenta. These are natural colors which provide an expanded color reproduction range, enabling good display. Thus, the EL display apparatus according to the present invention is not limited to those which provide color display using the three primary colors of R, G, and B.
Mainly three methods are available to colorize an organic EL display panel. One of them is a color conversion method. It suffices to form a single layer of blue as a light-emitting layer. The remaining green and red colors needed for full color display can be produced from the blue color through color conversion. Thus, this method has the advantage of eliminating the need to paint the R, G, and B colors separately and prepare organic EL materials for the R, G, and B colors. The color conversion method does not lower yields unlike the multi-color painting method. Any of the three methods can be applied to the EL display panel of the present invention.
Also, in addition to the three primary colors, white light-emitting pixels may be formed. The white light-emitting pixels can be created (formed or constructed) by laminating R, G, and B light-emitting structures. A set of pixels consists of pixels for the three primary colors RGB and a white light-emitting pixel 16W. Forming the white light-emitting pixels makes it easier to express peak brightness of white, and thus possible to implement bright image display.
Even when using a set of pixels for the three primary colors RGB, it is preferable to vary pixel electrode areas for the different colors. Of course, an equal area may be used if luminous efficiencies of the different colors as well as color purity are well balanced. However, if one or more colors are poorly balanced, preferably the pixel electrodes (light-emitting areas) are adjusted. The electrode area for each color can be determined based on current density. That is, when white balance is adjusted in a color temperature range of 7000 K (Kelvin) to 12000 K (both inclusive), difference between current densities of different colors should be within ±30%. More preferably, the difference should be within ±15%. For example, if current densities are around 100 A/square meter, all the three primary colors should have a current density of 70 A/square meter to 130 A/square meter (both inclusive). More preferably, all the three primary colors should have a current density of 85 A/square meter to 115 A/square meter (both inclusive).
The EL element 15 is a self-luminous element. When light from this self-luminous element enters a transistor serving as a switching element, a photoconductive phenomenon occurs. The photoconductive phenomenon is a phenomenon in which leakage (off-leakage) increases due to photoexcitation when a switching element such as a transistor is off.
To deal with this problem, the present invention forms a shading film under the gate driver 12 (source driver 14 in some cases) and under the pixel transistor 11. The shading film is formed of thin film of metal such as chromium and is from 50 nm to 150 nm thick (both inclusive). A thin film will provide a poor shading effect while a thick film will cause irregularities, making it difficult to pattern the transistor 11A1 in an upper layer.
In the case of the driver circuit 12 and the like, it is necessary to reduce penetration of light not only from the topside, but also from the underside. This is because the photoconductive phenomenon will cause malfunctions. If cathode electrodes are made of metal films, the present invention also forms a cathode electrode on the surface of the driver 12 and the like and uses it as a shading film.
However, if a cathode electrode is formed on the driver 12, electric fields from the cathode electrode may cause driver malfunctions or place the cathode electrode and driver circuit in electrical contact. To deal with this problem, the present invention forms at least one layer of organic EL film, and preferably two or more layers, on the driver circuit 12 simultaneously with the formation of organic EL film on the pixel electrode.
If a short circuit occurs between terminals of one or more transistors 11 or between a transistor 11 and signal line in the pixel, the EL element 15 may become a bright spot which remains illuminated constantly. The bright spot is visually conspicuous and must be turned into a black spot (turned off). The pixel 16 which corresponds to the bright spot is detected and the capacitor 19 is irradiated with laser light to cause a short circuit across the capacitor. As a result, the capacitor 19 can no longer hold electric charges, and thus the transistor 11a can be stopped from passing current. It is desirable to remove that part of a cathode film which will be irradiated with laser light to prevent the laser irradiation from causing a short circuit between a terminal electrode of the capacitor 19 and the cathode film.
Flaws in a transistor 11 in the pixel 16 will affect the source driver IC 14 and the like. For example, if a source-drain (SD) short circuit 562 occurs in the driver transistor 11a in
If an SD short circuit 562 occurs in the transistor 11a, an excessive current flows through the EL element 15. In other words, the EL element 15 remains illuminated constantly (becomes a bright spot). The bright spot is conspicuous as a defect. For example, if a source-drain (SD) short circuit occurs in the transistor 11a in
On the other hand, if an SD short circuit occurs in the transistor 11a and if the transistor 11c is on, the Vdd voltage is applied to the source signal line 18 and to the source driver 14. If the power supply voltage of the source driver 14 is not higher than Vdd, voltage resistance may be exceeded, causing the source driver 14 to rupture. Thus, it is preferable that the power supply voltage of the source driver 14 is equal to or higher than the Vdd voltage (the higher voltage of the panel).
An SD short circuit of the transistor 11a may go beyond a point defect and lead to rupture of the source driver circuit of the panel. Also, the bright spot is conspicuous, which makes the panel defective. Thus, it is necessary to turn the bright spot into a black spot by cutting the wiring which connects between the transistor 11 and EL element 15. Preferably an optical means such as laser light is used to cut the wiring.
A drive method according to the present invention will be described below. As shown in
Parasitic capacitance (not shown) is present in the source signal line 18. The parasitic capacitance is caused by the capacitance at the junction of the source signal line 18 and gate signal line 17, channel capacitance of the transistors 11b and 11c, etc.
The time t required to change the current value of the source signal line 18 is given by t=C·V/I, where C is stray capacitance, V is a voltage of the source signal line, and I is a current flowing through the source signal line. Thus, if the current value can be increased tenfold, the time required to change the current value can be reduced nearly tenfold. This also means that the current value can be changed to a predetermined value even if the parasitic capacitance of the source signal line 18 is increased tenfold. Thus, to apply a predetermined current value during a short horizontal scanning period, it is useful to increase the current value.
When input current is increased tenfold, output current is also increased tenfold, resulting in a tenfold increase in the EL brightness. Thus, to obtain predetermined brightness, a light emission period is reduced tenfold by reducing the conduction period of the transistor 17d in
Thus, in order to charge and discharge the parasitic capacitance of the source signal line 18 sufficiently and program a predetermined current value into the transistor 11a of the pixel 16, it is necessary to output a relatively large current from the source driver 14. However, when such a large current is passed through the source signal line 18, its current value is programmed into the pixel and a current larger than the predetermined current flows through the EL element 15. For example, if a 10 times larger current is programmed, naturally a 10 times larger current flows through the EL element 15 and the EL element 15 emits 10 times brighter light. To obtain predetermined emission brightness, the time during which the current flows through the EL element 15 can be reduced tenfold. This way, the parasitic capacitance can be charged/discharged sufficiently from the source signal line 18 and the predetermined emission brightness can be obtained.
Incidentally, although it has been stated that a 10 times larger current value is written into the pixel transistor 11a (more precisely, the terminal voltage of the capacitor 19 is set) and that the conduction period of the EL element 15 is reduced to 1/10, this is only exemplary. In some cases, a 10 times larger current value may be written into the pixel transistor 11a and the conduction period of the EL element 15 may be reduced to ⅕. On the other hand, a 10 times larger current value may be written into the pixel transistor 11a and the conduction period of the EL element 15 may be halved.
The present invention is characterized in that the write current into a pixel is set at a value other than a predetermined value and that a current is passed through the EL element 15 intermittently. For ease of explanation, it has been stated herein that an N times larger current is written into the pixel transistor 11 and the conduction period of the EL element 15 is reduced to 1/N. However, this is not restrictive. Needless to say, N1 times larger current may be written into the pixel transistor 11 and the conduction period of the EL element 15 maybe reduced to 1/N2 (N1 and N2 are different from each other)
In white raster display, it is assumed that average brightness over one field (frame) period of the display screen 50 is B0. This drive method performs current (voltage) programming in such a way that the brightness B1 of each pixel 16 is higher than the average brightness B0. Also, a non-display area 53 appears during at least one field (frame) period. Thus, in the drive method according to the present invention, the average brightness over one field (frame) period is lower than B1.
Incidentally, the non-display area 52 and display area 53 are not necessarily spaced equally. For example, they may appear at random (provided that the display period or non-display period makes up a predetermined value (constant ratio) as a whole). Also, display periods may vary among R, G, and B.
That is, display periods of R, G, and B or non-display periods can be adjusted (set) to predetermined values (proportions) in such a way as to obtain an optimum white balance.
To facilitate explanation of the drive method according to the present invention, it is assumed that “1/N” means reducing 1F (one field or one frame) to 1/N. Needless to say, however, it takes time to select one pixel row and to program current values (normally, one horizontal scanning period (1 H)) and error may result depending on scanning conditions.
For example, the EL element 15 may be illuminated for ⅕ of a period by programming the pixel 16 with an N=10 times larger current. The EL element 15 illuminates 10/5=2 times more brightly. It is also possible to program an N=2 times larger current into the pixel 16 and illuminate the EL element 15 for ¼ of the period. The EL element 15 illuminates 2/4=0.5 time more brightly. In short, the present invention achieves display other than constant display (1/1, i.e., non-intermittent display) by using a current other than an N=1 time current for current programming. Also, the drive system turns off the current supplied to the EL element 15, at least once during one frame (or one field) period. Also, the drive system at least achieves intermittent display by programming the pixel 16 with a current larger than a predetermined value.
A problem with an organic (inorganic) EL display is that it uses a display method basically different from that of an CRT or other display which presents an image as a set of displayed lines using an electron gun. That is, the EL display holds the current (voltage) written into a pixel for 1F (one field or one frame) period. Thus, a problem is that displaying moving pictures will result in blurred edges.
According to the present invention, current is passed through the EL element 15 only for a period of 1F/N, but current is not passed during the remaining period (1F(N−1)/N). Let us consider a situation in which the drive system is implemented and one point on the screen is observed. In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed intermittently in the temporal sense. When moving picture data are displayed intermittently, a good display condition is achieved without edge blur. In short, movie display close to that of a CRT can be achieved.
The drive method according to the present invention implements intermittent display. However, the intermittent display can be achieved by simply turning on and off the transistor 11d on a 1-H cycle. Consequently, a main clock of the circuit does not differ from conventional ones, and thus there is no increase in the power consumption of the circuit. Liquid crystal display panels need an image memory in order to achieve intermittent display. According to the present invention, image data is held in each pixel 16. Thus, the present invention requires no image memory for intermittent display.
The present invention controls the current passed through the EL element 15 by simply turning on and off the switching transistor 11d, the transistor 11e, and the like. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is held as it is in the capacitor 19. Thus, when the transistor 11d is turned on the next time, the current passed through the EL element 15 has the same value as the current flowing through the EL element 15 the previous time. Even to achieve black insertion (intermittent display such as black display), the present invention does not need to speed up the main clock of the circuit. Also, it does not need to elongate a time axis, and thus requires no image memory. Besides, the EL element 15 responds quickly, requiring a short time from application of current to light emission. Thus, the present invention is suitable for movie display, and by using intermittent display, it can solve a problem with conventional data-holding display panels (liquid crystal display panels, EL display panels, etc.) in displaying moving pictures.
Furthermore, in a large display apparatus, if increased wiring length of the source signal line 18 results in increased parasitic capacitance in the source signal line 18, this can be dealt with by increasing the value of N. When the value of programming current applied to the source signal line 18 is increased N times, the conduction period of the gate signal line 17b (the transistor 11d) can be set to 1F/N. This makes it possible to apply the present invention to television sets, monitors, and other large display apparatus.
The output stage of the source driver circuit 14 is constituted of a constant-current circuit 704 (see
The drive method according to the present invention will be described with reference to drawings in more detail below. The parasitic capacitance of the source signal line 18 is generated by the coupling capacitance with adjacent source signal lines 18, buffer output capacitance of the source driver IC (circuit) 14, cross capacitance between the source signal line 18 and gate signal line 17, etc. This parasitic capacitance is normally 10 pF or larger. In the case of voltage driving, since voltage is applied to the source signal line 18 from the source driver IC 14 at low impedance, more or less large parasitic capacitance does not disturb driving.
However, in the case of current driving, especially image display at the black level, the pixel capacitor 19 needs to be programmed with a minute current of 20 nA or less. Thus, if parasitic capacitance larger than a predetermined value is generated, the parasitic capacitance cannot be charged and discharged during the time when one pixel row is programmed (normally within 1 H, but not limited to 1 H because two pixel rows may be programmed simultaneously). If the parasitic capacitance cannot be charged and discharged within a period of 1 H, sufficient current cannot be written into the pixel, resulting in inadequate resolution.
In the pixel configuration in
During a period when the current flows through the EL element 15, the transistors 11c and 11b turn off and the transistor 11d turns on as shown in
Suppose a current I1 is N times the current which should normally flow (a predetermined value), the current flowing through the EL element 15 in
If the transistor 11d is kept on for a period 1/N the period during which it is normally kept on (approximately 1F) and is kept off during the remaining period (N−1)/N, the average brightness over the 1F equals predetermined brightness. This display condition closely resembles the display condition under which a CRT is scanning a screen with an electronic gun. The difference is that 1/N of the entire screen illuminates (where the entire screen is taken as 1) (in a CRT, what illuminates is one pixel row—more precisely, one pixel).
According to the present invention, 1F/N of the image display area 53 moves from top to bottom of the screen 50 as shown in
Incidentally, as shown in
In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed at intervals (intermittently) in the temporal sense. Liquid crystal display panels (EL display panels other than that of the present invention), which hold data in pixels for a period of 1F, cannot keep up with changes in image data during movie display, resulting is blurred moving pictures (edge blur of images). Since the present invention displays images intermittently, it can achieve a good display condition without edge blur of images. In short, movie display close to that of a CRT can be achieved.
Incidentally, to drive the pixel 16 as shown in
For example, when only a single gate signal line 17 is laid from the gate driver circuit 12 to the pixel 16, the drive method according to the present invention cannot be implemented using a configuration in which logic (Vgh or Vgl) applied to the gate signal line 17 is applied to the transistor 11b and the logic applied to the gate signal line 17 is converted (Vgh or Vgl) by an inverter and applied to the transistor 11d. Thus, the present invention requires a gate driver circuit 12a which operates the gate signal line 17a and gate driver circuit 12b which operates the gate signal line 17b.
Besides, the drive method according to the present invention provides a non-illuminated display even with the pixel configuration shown in
A timing chart of the drive method shown in
In
After 1 H, a gate signal line 17a(2) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row to the source driver circuit 14. The programming current is N times larger than a predetermined value (for ease of explanation, it is assumed that N=10). Therefore, the capacitor 19 is programmed so that 10 times larger current will flow through the transistor 11a. When the pixel row (2) is selected, in the pixel configuration shown in
After the next 1 H, a gate signal line 17a(3) is selected, a turn-off voltage (Vgh) is applied to the gate signal line 17b(3), and current does not flow through the EL element 15 in the pixel row (3). However, since a turn-off voltage (Vgh) is applied to the gate signal lines 17a(1) and (2) and a turn-on voltage (Vgl) is applied to the gate signal lines 17b(1) and (2) in the pixel rows (1) and (2), the EL element 15 illuminates.
Through the above operation, images are displayed in sync with a synchronization signal of 1 H. However, with the drive method in
Incidentally, the drive method according to the present invention causes a current larger than a predetermined current to flow through the EL element 15, and thereby charges and discharges the parasitic capacitance of the source signal line 18 sufficiently. That is, there is no need to pass an N times larger current through the EL element 15. For example, it is conceivable to form a current path in parallel with the EL element 15 (form a dummy EL element and use a shield film to prevent the dummy EL element from emitting light) and divide the flow of current between the EL element 15 and the dummy EL element. For example, when a signal current is 0.2 μA, a programming current is set to 2.2 μA and the current of 2.2 μA is passed through the transistor 11a. Then, the signal current of 0.2 μA may be passed through the EL element 15 and 2 μA may be passed through the dummy EL element, for example. That is, the dummy pixel row 281 in
With the above configuration, by increasing the current passed through the source signal line 18 N times, it is possible to pass an N times larger current through the driver transistor 11a and pass a current sufficiently smaller than the N times larger current through the EL element 15. As shown in
In
Suppose an N times larger current is used for programming (it is assumed that N=10 as described above), the screen becomes 10 times brighter. Thus, 90% of the display screen 50 can be constituted of the non-illuminated area 52. Thus, for example, if the number of horizontal scanning lines in the screen display area is 220 (S=220) in compliance with QCIF, 22 horizontal scanning lines can compose a display area 53 while 220−22=198 horizontal scanning lines can compose a non-display area 52. Generally speaking, if the number of horizontal scanning lines (number of pixel rows) is denoted by S, S/N of the entire area constitutes a display area 53, which is illuminated N times more brightly. Then, the display area 53 is scanned in the vertical direction of the screen. Thus, S(N−1)/N of the entire area is a non-illuminated area 52. The non-illuminated area presents a black display (is non-luminous). Also, the non-luminous area 52 is produced by turning off the transistor 11d. Incidentally, although it has been stated that the display area 53 is illuminated N times more brightly, naturally the value of N is adjusted by brightness adjustment and gamma adjustment.
In the above example, if a 10 times larger current is used for programming, the screen becomes 10 times brighter and 90% of the display screen 50 can be constituted of the non-illuminated area 52. However, this does not necessarily mean that R, G, and B pixels constitute the non-illuminated area 52 in the same proportion. For example, ⅛ of the R pixels, ⅙ of the G pixels, and 1/10 of the B pixels may constitute the non-illuminated area 52 with different colors making up different proportions. It is also possible to allow the non-illuminated area 52 (or illuminated area 53) to be adjusted separately among R, G, and B. For that, it is necessary to provide separate gate signal lines 17b for R, G, and B. However, allowing R, G, and B to be adjusted separately makes it possible to adjust white balance, making it easy to adjust color balance for each gradation (see
As shown in
In
To deal with this problem, the display area 53 can be divided into a plurality of parts as shown in
Dividing the display area 53 reduces flickering of the screen. Thus, a flicker-free good image display can be achieved. Incidentally, the display area 53 may be divided more finely. However, the more finely the display area 53 is divided, the poorer the movie display performance becomes.
Incidentally, although it has been stated with reference to
In the example described above, the display screen 50 is turned on and off (illuminated and non-illuminated) as the current delivered to the EL element 15 is switched on and off. That is, approximately equal current is passed through the transistor 11a multiple times using electric charges held in the capacitor 19. The present invention is not limited to this. For example, the display screen 50 may be turned on and off (illuminated and non-illuminated) by charging and discharging the capacitor 19.
Since black display on EL display apparatus corresponds to complete non-illumination, contrast does not lower unlike in the case of intermittent display on liquid crystal display panels. Also, with the configurations in
Thus, the drive method described above is not limited to a current-driven type and can be applied to a voltage-driven type as well. That is, in a configuration in which the current passed through the EL element 15 is stored in each pixel, intermittent driving is implemented by switching on and off the current path between the driver transistor 11 and EL element 15.
It is important to maintain terminal voltage of the capacitor 19. This is because if the terminal voltage of the capacitor 19 changes (charge/discharge) during one field (frame) period, flickering occurs when the screen brightness changes and the frame rate lowers. The current passed through the EL element 15 by the transistor 11a must be higher than 65%. More specifically, if the initial current written into the pixel 16 and passed through the EL element 15 is taken as 100%, the current passed through the EL element 15 just before it is written into the pixel 16 in the next frame (field) must not fall below 65%.
With the pixel configuration shown in
Also, since the operation clock of the gate driver circuit 12 is significantly slower than the operation clock of the source driver circuit 14, there is no need to upgrade the main clock of the circuit. Besides, the value of N can be changed easily.
Incidentally, the image display direction (image writing direction) may be from top to bottom of the screen in the first field (frame), and from bottom to top of the screen in the second field (frame). That is, an upward direction and downward direction may be repeated alternately.
Alternatively, it is possible to use a downward direction in the first field (frame), turn the entire screen into black display (non-display) once, and use an upward direction in the second field (frame). It is also possible to turn the entire screen into black display (non-display) once.
Incidentally, although top-to-bottom and bottom-to-top writing directions on the screen are used in the drive method described above, this is not restrictive. It is also possible to fix the writing direction on the screen to a top-to-bottom direction or bottom-to-top direction and move the non-display area 52 from top to bottom in the first field, and from bottom to top in the second field. Alternatively, it is possible to divide a frame into three fields and assign the first field to R, the second field to G, and the third field to B so that three fields compose a single frame. It is also possible to display R, G, and B in turns by switching among them every horizontal scanning period (1 H) (see FIGS. 175 to 180 and their description). The items mentioned above also apply to other examples of the present invention.
The non-display area 52 need not be totally non-illuminated. Weak light emission or dim image display will not be a problem in practical use. It should be regarded to be an area which has a lower display brightness than the image display area 53. Also, the non-display area 52 may be an area which does not display one or two colors out of R, G, and B. Also, it may be an area which displays one or two colors among R, G, and B at low brightness.
Basically, if the brightness of the display area 53 is kept at a predetermined value, the larger the display area 53, the brighter the display screen 50. For example, when the brightness of the image display area 53 is 100 (nt), if the percentage of the display screen 50 accounted for by the display area 53 changes from 10% to 20%, the brightness of the screen is doubled. Thus, by varying the proportion of the display area 53 in the entire screen 50, it is possible to vary the display brightness of the screen. The display brightness of the screen 50 is proportional to the ratio of the display area 53 to the screen 50.
The size of the display area 53 can be specified freely by controlling data pulses (ST2) sent to the shift register circuit 61. Also, by varying the input timing and period of the data pulses, it is possible to switch between the display condition shown in
Changes from
In brightness adjustment of a conventional screen, low brightness of the screen 50 results in poor gradation performance. That is, even if 64 gradations can be displayed in a high-brightness display, in most cases, less than half the gradations can be displayed in a low-brightness display. In contrast, the drive method according to the present invention does not depend on the display brightness of the screen and can display up to 64 gradations, which is the highest.
To eliminate flickering at an even lower frame rate, the display areas 53 can be scattered more finely as shown in
Mainly, N=two times, N=4 times, etc. are used in the above example. Needless to say, however, the present invention is not limited to integral multiples. It is not limited to a value equal to or larger than N=two, either. For example, less than half the screen 50 may be a non-display area 52 at a certain time point. A predetermined brightness can be achieved if a current Iw 5/4 a predetermined value is used for current programming and the EL element is illuminated for 4/5 of 1F.
The present invention is not limited to the above. For example, a current Iw 10/4 a predetermined value may be used for current programming to illuminate the EL element for 4/5 of 1F. In this case, the EL element illuminates at twice a predetermined brightness. Alternatively, a current Iw 5/4 a predetermined value may used for current programming to illuminate the EL element for 2/5 of 1F. In this case, the EL element illuminates at 1/2 the predetermined brightness. Also, a current Iw 5/4 a predetermined value may be used for current programming to illuminate the EL element for 1/1 of 1F. In this case, the EL element illuminates at 5/4 the predetermined brightness.
Thus, the present invention controls the brightness of the display screen by controlling the magnitude of programming current and illumination period IF. Also, by illuminating the EL element for a period shorter than the period of 1F, the present invention can insert a non-display area 52, and thereby improve movie display performance. By illuminating the EL element constantly for the period of 1F, the present invention can display a bright screen.
If pixel size is A square mm and predetermined brightness of white raster display is B (nt), preferably programming current I (μA) (programming current outputted from the source driver circuit 14) or the current written into the pixel satisfies:
(A×B)/20≦I≦(A×B)
This provides good light emission efficiency and solves a shortage of write current.
More preferably, the programming current I (μA) falls within the range:
(A×B)/10≦I≦(A×B)
According to the invention described with reference to
Current is passed through the EL element 15 only for a period M/N the frame (field) period, but current is not passed during the remaining period (1F(N−1)M/N). In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed at intervals (intermittently) in the temporal sense. This achieves a good display condition without edge blur of images. Also, since the source signal line 18 is driven by an N times larger current, it is not affected by parasitic capacitance. Thus, this method can accommodate high-resolution display panels.
In
The programming current flowing through the source signal line 18 is N times larger than a predetermined value (for ease of explanation, it is assumed that N=10. Of course, since the predetermined value is a data current for use to display images, it is not a fixed value unless in the case of white raster display). It is also assumed that five pixel rows are selected simultaneously (M=5). Therefore, ideally the capacitor 19 of one pixel is programmed so that a twice (N/M=10/5=2) larger current will flow through the transistor 11a.
When the write pixel row is the (1)-th pixel row, the gate signal lines 17a(1), (2), (3), (4), and (5) are selected as shown in
Ideally, the transistors 11a in the five pixels deliver a current of Iw×2 each to the source signal line 18 (i.e., a current of Iw×2×N=Iw×2×5=Iw×10 flows through the source signal line 18. Thus, if a predetermined voltage Iw flows when the N-fold pulse driving according to the present invention is not used, a current 10 times larger than Iw flows through the source signal line 18).
Through the above operation (drive method), the capacitor 19 of each pixel 16 is programmed with a twice larger current. For ease of understanding, it is assumed here that the transistors 11a have equal characteristics (Vt and S value)
Since five pixel rows are selected simultaneously (M=5), five driver transistors 11a operate. That is, 10/5=2 times larger current flows through the transistor 11a per pixel. The total programming current of the five transistors 11a flows through the source signal line 18. For example, if a current conventionally written into the write pixel row 51a is Iw, a current of Iw×10 is passed through the source signal line 18. The write pixel rows 51b into which image data is written later than the write pixel row (1) are auxiliary pixel rows used to increase the amount of current delivered to the source signal line 18. However, there is no problem because regular image data is written into the write pixel rows 51b later.
Thus, the four pixel rows 51b provide the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel rows 51b selected to increase current are in non-display mode 52. However, in the pixel configuration of a current mirror, such as shown in
After 1 H, the gate signal line 17a(1) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(6) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (6) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (1).
After the next 1 H, the gate signal line 17a(2) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(7) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (7) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (2). The entire screen is redrawn as it is scanned by shifting pixel rows one by one through the above operations.
With the drive method in
As is the case with
To deal with this problem, the display area 53 can be divided into a plurality of parts as illustrated in
As described above, dividing the display area 53 reduces flickering of the screen. Thus, a flicker-free good image display can be achieved. Incidentally, the display area 53 may be divided more finely. The more finely the display area 53 is divided, the less flickering occurs. Since the EL element 15 is highly responsive, even if it is turned on and off at intervals shorter than 5 μsec, there is no lowering of the display brightness.
With the drive method according to the present invention, the EL element 15 can be turned on and off by turning on and off a signal applied to the gate signal line 17b. Thus, the drive method according to the present invention can perform control using a low frequency on the order of KHz. Also, it does not need an image memory or the like in order to insert a black screen (insert anon-display area 52). Thus, the drive circuit or method according to the present invention can be implemented at low costs.
This is because that part of a semiconductor film which is annealed simultaneously has uniform characteristics. That is, the semiconductor film is created uniformly within an irradiation range of laser stripes and the Vt and mobility of the transistors which use the semiconductor film are almost uniform. Thus, if a striped laser shot is moved in parallel with the source signal line 18, pixels (a pixel column, i.e., pixels arranged vertically on the screen) along the source signal line 18 take on almost equal characteristics. Therefore, if a plurality of pixel rows are turned on simultaneously for current programming, the current obtained by dividing the programming current by the number of selected pixels are programmed almost uniformly into the pixels This makes it possible to program a current close to a target value and achieve uniform display. Thus, the direction of a laser shot and the drive method described with reference to
As described above, if the direction of a laser shot is made to coincide approximately with the direction of the source signal line 18 (see
Incidentally, as described with reference to
Incidentally, in the examples of the present invention a write pixel row is shifted every 1 H, but this is not restrictive. Pixel rows may be shifted every 2 Hs (two pixel rows at a time). Also, more than two pixel rows may be shifted at a time. Also, pixel rows may be shifted at desired time intervals or every second pixel may be shifted.
The shifting interval may be varied according to locations on the screen. For example, the shifting interval may be decreased in the middle of the screen, and increased at the top and bottom of the screen. For example, a pixel row may be shifted at intervals of 200 μsec. in the middle of the screen 50, and at intervals of 100 μsec. at the top and bottom of the screen 50. This increases emission brightness in the middle of the screen 50 and decreases it around the perimeters (at the top and bottom of the screen 50)). Needless to say, the shifting interval is varied smoothly among the top, middle, and bottom of the screen 50 to avoid brightness contours.
Incidentally, the reference voltage of the source driver circuit 14 may be varied with the scanning location on the screen 50 (see
Also, it goes without saying that images may be displayed by combining a drive method which varies the pixel-row shifting interval with the location on the screen and a drive method which varies the reference voltage with the location on the screen 50.
The shifting interval may be varied on a frame-by-frame basis. Also, it is not strictly necessary to select consecutive pixel rows. For example, every second pixel row may be selected.
Specifically, a possible drive method involves selecting the first and third pixel rows in the first horizontal scanning period, the second and fourth pixel rows in the second horizontal scanning period, the third and fifth pixel rows in the third horizontal scanning period, and the fourth and sixth pixel rows in the fourth horizontal scanning period. Of course, a drive method which involves selecting the first, third, and fifth pixel rows in the first horizontal scanning period also belongs to the technical category of the present invention. Also, one in every few pixel rows maybe selected.
Incidentally, the combination of the direction of a laser shot and selection of multiple pixel rows is not limited to the pixel configurations in
In
Ideally, the transistors 11a in the two pixel rows deliver a current of Iw×5 each to the source signal line 18 (when N=10. Since K=2, a current of Iw×K×5=Iw×10 flows through the source signal line 18). Then, the capacitor 19 of each pixel 16 is programmed with a 5 times larger current.
Since two pixel rows are selected simultaneously (K=2), two driver transistors 11a operate. That is, 10/2=5 times larger current flows through the transistor 11a per pixel. The total programming current of the two transistors 11a flows through the source signal line 18.
For example, if the current written into the write pixel row 51a is Id, a current of Iw×10 is passed through the source signal line 18. There is no problem because regular image data is written into the write pixel row 51b later. The pixel row 51b provides the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel row 51b selected to increase current are in non-display mode 52.
After the next 1 H, the gate signal line 17a(1) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(3) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (3) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (1).
After the next 1 H, the gate signal line 17a(2) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(4) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (4) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (2). The entire screen is redrawn as it is scanned by shifting pixel rows one by one through the above operations (of course, two or more pixel rows may be shifted simultaneously. For example, in the case of pseudo-interlaced driving, two pixel rows will be shifted at a time. Also, from the viewpoint of image display, the same image may be written into two or more pixel rows).
As in the case of
As shown in
To deal with this problem, the present invention forms (places) a dummy pixel row 281 at the bottom of the screen 50, as shown in
Incidentally, although the dummy pixel row 281 is illustrated as being adjacent to the top end or bottom end of the display screen 50, this is not restrictive. It may be formed at a location away from the display screen 50. Besides, the dummy pixel row 281 does not need to contain a switching transistor 11d or EL element 15 such as those shown in
Although it has been stated with reference to
The present invention is not limited to this. For example, five pixel rows may be selected simultaneously (see
The dummy pixel row configuration or dummy pixel row driving according to the present invention uses one or more dummy pixel rows. Of course, it is preferable to use the dummy pixel row driving and N-fold pulse driving in combination.
In the drive method which selects two or more pixel rows at a time, the larger the number of pixel rows selected simultaneously, the more difficult it becomes to absorb variations in the characteristics of the transistors 11a. However, the current programmed into one pixel increases with decreases in the number M of pixel rows selected simultaneously, resulting in a large current flowing through the EL element 15, which in turn makes the EL element 15 prone to degradation.
Referring to
Naturally, since the same image data is written into the five write pixel rows, the transistors 11d in the five write pixel rows are turned off in order not to display the image. Thus, the display condition is as shown in
In the next ½ H period, one pixel is selected for current (voltage) programming. The condition is as shown in
Specifically, in
Incidentally, scanning of the non-illuminated area 52 from top to bottom of the screen and scanning of the write pixel rows 51a from top to bottom of the screen are performed in the same manner as in examples in
First, the ISEL signal will be described. The driver circuit 14 which performs operations shown in
When the ISEL signal is low, the current output circuit A which outputs 25 times larger current is selected and current from the source signal line 18 is absorbed by the source driver IC 14 (more precisely, the current is absorbed by the current output circuit A formed in the source driver IC 14). The magnification (such as ×25 or ×5) of the current from the current output circuits can be adjusted easily using a plurality of resisters and an analog switch.
As shown in
Ideally, the transistors 11a in the five pixels deliver a current of Iw×2 each to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with a five times larger current. For ease of understanding, it is assumed here that the transistors have equal characteristics (Vt and S value).
Since five pixel rows are selected simultaneously (K=5), five driver transistors 11a operate. That is, 25/5=5 times larger current flows through the transistor 11a per pixel. The total programming current of the five transistors 11a flows through the source signal line 18. For example, if the current written into the write pixel row 51a by a conventional drive method is Iw, a current of Iw×25 is passed through the source signal line 18. The write pixel rows 51b into which image data is written later than the write pixel row (1) are auxiliary pixel rows used to increase the amount of current delivered to the source signal line 18. However, there is no problem because regular image data is written into the write pixel rows 51b later.
Thus, the pixel rows 51b provide the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel rows 51b selected to increase current are in non-display mode 52.
In the next ½ H period (½ of the horizontal scanning period), only the write pixel row 51a is selected. That is, only the (1)-th pixel row is selected. As can be seen from
Besides, since ISEL is high, the current output circuit B which outputs 5 times larger current is selected and connected to the source signal line 18. Also, a turn-off voltage (Vgh) is applied to the gate signal line 17b, which is in the same state as during the first ½ H. Thus, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52.
Thus, each transistor 11a in the pixel row (1) deliver a current of Iw×5 to the source signal line 18. Then, the capacitor 19 in each pixel row (1) is programmed with a 5 times larger current.
In the next horizontal scanning period, the write pixel row shifts by one. That is, the pixel row (2) becomes the current write pixel row. During the first ½ H period, when the write pixel row is the (2)-th pixel row, the gate signal lines 17a(2), (3), (4), and (5) and (6) are selected. That is, the switching transistors 11b and the transistors 11c in the pixel rows (2), (3), (4), (5), and (6) are on. Besides, since ISEL is low, the current output circuit A which outputs 25 times larger current is selected and connected to the source signal line 18. Also, a turn-off voltage (Vgh) is applied to the gate signal line 17b.
Thus, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52. On the other hand, since Vgl voltage is applied to the gate signal line 17b(1) of the pixel row (1), the transistor 11d is on and the EL element 15 in the pixel row (1) illuminates.
Since five pixel rows are selected simultaneously (K=5), five driver transistors 11a operate. That is, 25/5=5 times larger current flows through the transistor 11a per pixel. The total programming current of the five transistors 11a flows through the source signal line 18.
In the next ½ H period (½ of the horizontal scanning period), only the write pixel row 51a is selected. That is, only the (2)-th pixel row is selected. As can be seen from
Thus, the transistors 11a in the pixel rows (1) and (2) are in operation (the pixel row (1) supplies current to the EL element 15 and the pixel row (2) supplies current to the source signal line 18), but the switching transistors 11b and the transistors 11c in the pixel rows (3), (4), (5), and (6) are off. That is, they are non-selected.
Besides, since ISEL is high, the current output circuit B which outputs 5 times larger current is selected and the current output circuit 1222b is connected to the source signal line 18. Also, a turn-off voltage (Vgh) is applied to the gate signal line 17b, which is in the same state as during the first ½ H. Thus, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52.
Thus, each transistor 11a in the pixel row (1) deliver a current of Iw×5 to the source signal line 18. Then, the capacitor 19 in each pixel row (1) is programmed with a 5 times larger current. The entire screen is drawn as the above operations are performed in sequence.
The drive method described with reference to
Another scheme is also available. It selects G pixel rows (G is 2 or larger) in the first period and does programming in such a way that the total current in all the pixel rows will be an N times larger current. In the second period, this scheme selects B pixel rows (B is smaller than G, but not smaller than 1) and does programming in such a way that the total current in the selected pixel rows (the current in the one pixel row if one pixel row is selected) will be an N times larger current. For example, in
Incidentally, although a plurality of pixel rows are selected simultaneously in a period of ½ H and a single pixel row is selected in a period of ½ H in
In
In
In the example described above, pixel rows are selected one by one and programmed with current, or two or more pixel rows are selected at a time and programmed with current. However, the present invention is not limited to this. It is also possible to use a combination of the two methods according to image data: the method of selecting pixel rows one by one and programming them with current and the method of selecting two or more pixel rows at a time and programming them with current.
In the case where multiple pixel rows are selected at a time, it is assumed for ease of understanding that two pixel rows are selected simultaneously as illustrated in
The drive system which selects pixel rows one by one does not need to use dummy pixel rows.
Incidentally, for ease of understanding, it is assumed that the source driver IC 14 in
Thus, the drive system which selects two pixel rows at a time as shown in
To provide equal screen brightness, the duty ratio in
Also, the magnitude of the reference current inputted in the source driver IC 14 can be varied twice as much. Alternatively, the programming current can be doubled.
If input video signals are non-interlaced (progressive) signals, the drive system in
If input video signals are interlaced signals, the drive system in
Also, if video signals have low image resolution, the drive system in
It is also possible to use the drive method in
The drive method in
A problem is that the drive system which selects two pixel rows at a time as shown in
To provide equal screen brightness, the duty ratio in
That is, the proportions of the non-display area 52 and display area 53 in
The proportions of the non-display area 52 and display area 53 in
Now, interlaced driving according to the present invention will be described below in more detail.
Thus, through operation (control) of the gate driver circuit 12a1, image data in the odd-numbered pixel rows are rewritten in sequence. In the odd-numbered pixel rows, illumination and non-illumination of the EL elements are controlled through operation (control) of the gate driver circuit 12b1. Also, through operation (control) of the gate driver circuit 12a2, image data in the even-numbered pixel rows are rewritten in sequence. In the even-numbered pixel rows, illumination and non-illumination of the EL elements are controlled through operation (control) of the gate driver circuit 12b2.
In this way, interlaced driving can be implemented easily on an EL display panel. Also, N-fold pulse driving eliminates shortages of write current and blurred moving pictures. Besides, current (voltage) programming and illumination of EL elements 15 can be controlled easily and circuits can be implemented easily.
Incidentally, the drive method according to the present invention is not limited to those shown in
The drive method in
In the above example, the drive method programs pixel rows with current (voltage) one at a time. However, the drive method according to the present invention is not limited to this. Needless to say, two pixel rows (a plurality of pixel rows) maybe programmed with current (voltage) simultaneously as shown in
Besides, in
The N-fold pulse driving method according to the present invention uses the same waveform for the gate signal lines 17b of different pixel rows and applies current by shifting the pixel rows at 1 H intervals. The use of such scanning makes it possible to shift illuminating pixel rows in sequence with the illumination duration of the EL elements 15 fixed to 1F/N. It is easy to shift pixel rows in this way while using the same waveform for the gate signal lines 17b of the pixel rows. It can be done by simply controlling data ST1 and ST2 applied to the shift register circuits 61a and 61b in
Incidentally, the EL elements 15 must be turned on and off at intervals of 0.5 msec or longer. Short intervals will lead to insufficient black display due to persistence of vision, resulting in blurred images and making it look as if the resolution has lowered. This also represents a display state of a data holding display. However, increasing the on/off intervals to 100 msec will cause flickering. Thus, the on/off intervals of the EL elements must be not shorter than 0.5 μsec and not longer than 100 msec. More preferably, the on/off intervals should be from 2 msec to 30 msec (both inclusive). Even more preferably, the on/off intervals should be from 3 msec to 20 msec (both inclusive).
As also described above, an undivided black screen 152 achieves good movie display, but makes flickering of the screen more noticeable. Thus, it is desirable to divide the black insert into multiple parts. However, too many divisions will cause moving pictures to blur. The number of divisions should be from 1 to 8 (both inclusive). More preferably, it should be from 1 to 5 (both inclusive).
Incidentally, it is preferable that the number of divisions of a black screen can be varied between still pictures and moving pictures. When N=4, 75% is occupied by a black screen and 25% is occupied by image display. When the number of divisions is 1, a strip of black display which makes up 75% is scanned vertically. When the number of divisions is 3, three blocks are scanned, where each block consists of a black screen which makes up 25% and a display. screen which makes up 25/3 percent. The number of divisions is increased for still pictures and decreased for moving pictures. The switching can be done either automatically according to input images (detection of moving pictures) or manually by the user. Alternatively, the switching can be done according to input outlet such as video on the display apparatus.
For example, for wallpaper display or an input screen on a cell phone, the number of divisions should be 10 or more (in extreme cases, the display may be turned on and off every 1 H). When displaying moving pictures in NTSC format, the number of divisions should be from 1 to 5 (both inclusive). Preferably, the number of divisions can be switched in three or more steps; for example, 0, 2, 4, 8 divisions, and so on Preferably, the ratio of the black screen to the entire display screen should be from 0.2 to 0.9 (from 1.2 to 9 in terms of N) both inclusive when the area of the entire screen is taken as 1. More preferably, the ratio should be from 0.25 to 0.6 (from 1.25 to 6 in terms of N) both inclusive. If the ratio is 0.20 or less, movie display is not improved much. When the ratio is 0.9 or more, the display part becomes bright and its vertical movements become liable to be recognized visually.
Also, preferably, the number of frames per second is from 10 to 100 (10 Hz to 100 Hz) both inclusive. More preferably, it is from 12 to 65 (12 Hz to 65 Hz) both inclusive. When the number of frames is small, flickering of the screen becomes conspicuous while too large a number of frames makes writing from the source driver circuit 14 and the like difficult, resulting in deterioration of resolution.
The present invention allows the brightness of images to be varied by controlling the gate signal lines 17. However, needless to say, the brightness of images may be varied by varying the current (voltage) applied to the source signal lines 18. It goes without saying that the two methods described above (
Needless to say, the above items also apply to the pixel configurations for current programming in
Also, the gate signal line 17b may be set to Vgl for a period of 1F/N anytime during the period of 1F (not limited to 1F. Any unit time will do). This is because a predetermined brightness is obtained by turning off the EL element 15 for a predetermined period out of a unit time. However, it is preferable to set the gate signal line 17b to Vgl and illuminate the EL element 15 immediately after the current programming period (1 H). This will reduce the effect of retention characteristics of the capacitor 19 in
Also, preferably the number of screen divisions is configured to be variable. For example, when the user presses a brightness adjustment switch or turns a brightness adjustment knob, the value of K may be changed in response. Alternatively, the value of K may be changed manually or automatically depending on images or data to be displayed.
In this way, the mechanism for changing the value of K (the number of divisions of the image display part 53) can be implemented easily. This can be achieved by simply making the time to change ST (when to set ST low during 1F) adjustable or variable.
Incidentally, although it has been stated with reference to
The above examples involve placing (forming) the transistor 11d serving as a switching element between the EL element 15 and driver transistor 11a and turning on and off the screen 50 by controlling the transistor 11d. This drive method eliminates shortages of write current in black display condition during current programming and thereby achieves proper resolution or black display. That is, in current programming, it is important to achieve proper black display. The drive method described next achieves proper black display by resetting the driver transistor 11a. This example will be described below with reference to
The pixel configuration in
To implement reset driving using the pixel configuration shown in
Preferably, the drive voltage should be varied between the gate signal line 17a which drives the transistor 11b and the gate signal line 17b which drives the transistor 11d (when the pixel configuration in
Too large an amplitude value of the gate signal line 17 will increase penetration voltage between the gate signal line 17 and pixel 16, resulting in an insufficient black level. The amplitude of the gate signal line 17a can be controlled by controlling the time when the potential of the source signal line 18 is not applied (or is applied (during selection)) to the pixel 16. Since changes in the potential of the source signal line 18 are small, the amplitude value of the gate signal line 17a can be made small.
On the other hand, the gate signal line 17b is used for on/off control of EL. Thus, its amplitude value becomes large. For this, output voltage is varied between the shift register circuits 61a and 61b. If the pixel is constructed of P-channel transistors, approximately equal Vgh (turn-off voltage) is used for the shift register circuits 61a and 61b while Vgl (turn-on voltage) of the shift register circuit 61a is made lower than Vgl (turn-on voltage) of the shift register circuit 61b.
Reset driving will be described below with reference to
The reset mode (in which no current flows) of the transistor 11a is equivalent to a state in which an offset voltage is held in voltage offset canceling mode described with reference to
That is, in the state in
The offset voltage varies with the characteristics of the transistor 11a. Thus, in
Incidentally, before the operation in
As the operation time of
Preferably, this period should be varied among R, G, and B pixels. This is because EL material varies among different colors and rising voltage varies among different EL materials. Optimum periods suitable for EL materials should be specified separately for the R, G, and B pixels. Although it has been stated that the period should be from 1 H to 5 Hs (both inclusive) in this example, it goes without saying that the period may be 5 Hs or longer in the case of a drive system which mainly concerns black insertion (writing of a black screen). Incidentally, the longer the period, the better the black display condition of pixels.
A state shown in
If the programming current Iw is 0 A, the transistor 11a is held in the state in
After the programming in
The drive system (reset driving) described with reference to
In image display mode (if instantaneous changes can be observed), the pixel row to be programmed with current is reset (black display mode) and is programmed with current after 1 H (also in black display mode because the transistor 11d is off). Next, current is supplied to the EL element 15 and the pixel row illuminates at a predetermined brightness (at the programmed current). That is, the pixel row of black display moves from top to bottom of the screen and it should look as if the image were rewritten at the location where the pixel row passed by.
Incidentally, although it has been stated that current programming is performed 1 H after a reset, this period may be approximately 5 Hs or shorter. This is because it takes a relatively long time for the reset in
Also, the number of pixel rows which are reset at a time is not limited to one, and two or more pixel rows may be reset at a time. It is also possible to reset and scan two or more pixel rows at a time by overlapping some of them. For example, if four pixel rows are reset at a time, pixel rows (1), (2), (3), and (4) are reset in the first horizontal scanning period (1 unit), pixel rows (3), (4), (5), and (6) are reset in the second horizontal scanning period, pixel rows (5), (6), (7), and (8) are reset in the third horizontal scanning period, and pixel rows (7), (8), (9), and (10) are reset in the fourth horizontal scanning period. Incidentally the drive operations in FIGS. 33(b) and 33(c) are naturally carried out in sync with the drive operation in
Needless to say, the drive operation of FIGS. 33(b) and 33(c) may be performed after resetting all the pixels in the screen simultaneously or during scanning. Also, it goes without saying that pixel rows may be reset (at intervals of one or more pixel rows) in interlaced driving mode (scanning at intervals of one or more pixel rows). Also, pixel rows may be reset at random. The reset driving according to the present invention involves operating pixel rows (i.e., controlling the vertical direction of the screen). However, the concept of reset driving does not limit control directions to the pixel row direction. For example, it goes without saying that reset driving may be performed in the direction of pixel columns.
Incidentally, the reset driving in
Needless to say, more excellent image display can be achieved by combining with a reverse bias drive method, a precharge drive method, a penetration voltage drive method, or the like described later. Thus, it goes without saying that reset driving can be performed in combination with other examples according to the present invention.
Thus, the gate signal line 17a is controlled by the gate driver circuit 12a while the gate signal line 17c is controlled by the gate driver circuit 12b. This makes it possible to freely specify the time to turn on the transistor 11b and reset the driver transistor 11a as well as the time to turn on the transistor 111c and program the driver transistor 11a with current. Other parts of the configuration are the same as or similar to those described earlier, and thus description thereof will be omitted.
Although in the timing chart shown in
The duration of the reset period can be changed easily using a DATA (ST) pulse period inputted in the gate driver circuit 12. For example, if DATA inputted in an ST terminal is set high for a period of 2 Hs, the reset period outputted for each gate signal line 17a is 2 Hs. Similarly, if DATA inputted in the ST terminal is set high for a period of 5 Hs, the reset period outputted for each gate signal line 17a is 5 Hs.
After a reset period of 1 H, a turn-on voltage is applied to the gate signal line 17c(1) of the pixel row (1). As the transistor 11c turns on, the programming current Iw applied to the source signal line 18 is written into the driver transistor 11a via the transistor 11c.
After current programming, a turn-off voltage is applied to the gate signal line 17c of the pixel row (1), the transistor 11c is turned off, and the pixel disconnected from the source signal line. At the same time, a turn-off voltage is also applied to the gate signal line 17a and the driver transistor 11a exits the reset mode (incidentally, the use of the term “current-programming mode” is more appropriate than the term “reset mode” to refer to this period). On the other hand, a turn-on voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and the current programmed into the driver transistor 11a flows through the EL element 15. What has been said about the pixel row (1) similarly applies to the pixel row (2) and subsequent pixel rows. Also, their operation is obvious from
In
In
In the circuit configuration shown in
As can be seen from the fact that an OR circuit 371 is included in
For example, if the shift register circuit 61a outputs a high-level signal second, a turn-on voltage is output to the gate signal lines 17c of the pixel 16(1), which now is in a state of being programmed with current (voltage). At the same time, a turn-on voltage is also output to the gate signal lines 17a of the pixel 16(2), turning on the transistor 11b of the pixel 16(2) and resetting the driver transistor 11a of the pixel 16(2).
Similarly, if the shift register circuit 61a outputs a high-level signal third, a turn-on voltage is output to the gate signal lines 17c of the pixel 16(2), which now is in a state of being programmed with current (voltage). At the same time, a turn-on voltage is also output to the gate signal lines 17a of the pixel 16(3, turning on the transistor 11b of the pixel 16(3) and resetting the driver transistor 11a of the pixel 16(3). Thus, the gate signal lines 17a outputs turn-on voltages for a period of 2 Hs, and the gate signal lines 17c receive a turn-on voltage for a period of 1 H.
In programming mode, since the transistors 11b and 11c turn on simultaneously (
The above example concerns the pixel configuration in
As shown in
The reset mode (in which no current flows) of the transistors 11a and 11b is equivalent to a state in which a offset voltage is held in voltage offset canceling mode described with reference to
In
As in the case of
After the state in
If the programming current Iw is 0 A (black display), the transistor 11b is held in the state in
After the current programming in
The drive system (reset driving) described with reference to
At least the second operation is performed after the first operation. Incidentally, the operation of disconnecting the driver transistor 11a or 11b from the EL element 15 in the first operation is not absolutely necessary. The drain (D) terminal and gate (G) terminal of the driver transistor are short-circuited in the first operation without disconnecting the driver transistor 11a or 11b from the EL element 15, nothing more than some variations in reset mode may result. Whether to omit disconnection should be determined by considering the characteristics of the transistors in the constructed array.
The current-mirror pixel configuration in
With the current-mirror pixel configuration in
In image display mode (if instantaneous changes can be observed), the pixel row to be programmed with current is reset (black display mode) and is programmed with current after a predetermined H. The pixel row of black display moves from top to bottom of the screen and it should look as if the image were rewritten at the location where the pixel row passed by.
Although the above example has been described mainly in relation to pixel configuration for current programming, the reset driving according to the present invention can also be applied to pixel configuration for voltage programming.
In the configuration shown in
As illustrated in
The reset mode (in which no current flows) of the transistors 11a and 11b is equivalent to a state in which an offset voltage is held in voltage offset canceling mode described with reference to
Incidentally, in the pixel configuration for voltage programming, as the reset period becomes longer, a larger Ib current tends to flow, reducing the terminal voltage of the capacitor 19, as in the case of pixel configuration for current programming. Thus, the operation time in
Besides, it is preferable that the gate signal line 17e should be shared with the gate signal line 17a in a preceding stage. That is the gate signal line 17e should be shorted to the gate signal line 17a in the pixel row in the preceding stage. This configuration is referred to as a preceding-stage gate control system. Incidentally, the stage-stage gate control system uses waveforms of gate signal lines of a pixel row selected one or more Hs before the pixel row of interest. Thus, this system is not limited to the previous pixel row. For example, the driver transistor 11a of the pixel row of interest maybe reset using the waveforms of gate signal lines two pixel rows ahead.
The stage-stage gate control system will be described more concretely. Suppose, the pixel row of interest is the (N)-th pixel row whose gate signal lines are 17e(N) and 17a(N). The preceding pixel row selected 1 H before is assumed to be the (N−1)-th pixel row whose gate signal lines are 17e(N−1) and 17a(N−1). The pixel row selected 1 H after the pixel row of interest is assumed to be the (N+1)-th pixel row whose gate signal lines are 17e(N+1) and 17a(N+1).
In the (N−1)-th H-period, as a turn-on voltage is applied to the gate signal line 17a(N−1) of the (N−1)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N) of the (N)-th pixel row. This is because the gate signal line 17e(N) and the gate signal line 17a(N−1) of the pixel row in the preceding stage are shorted. Consequently, the pixel transistor 11b(N−1) in the (N−1)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a(N−1). At the same time, the pixel transistor 11e(N) in the (N)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a(N) are shorted, and the driver transistor 11a(N) is reset.
In the (N)-th H-period which follows the (N−1)-th H-period, as a turn-on voltage is applied to the gate signal line 17a(N) of the (N)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N+1) of the (N+1)-th pixel row. Consequently, the pixel transistor 11b(N) in the (N)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a(N). At the same time, the pixel transistor 11e(N+1) in the (N+1)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a(N+1) are shorted, and the driver transistor 11a(N+1) is reset.
Similarly, in the (N+1)-th period which follows the (N)-th H-period, as a turn-on voltage is applied to the gate signal line 17a(N+1) of the (N+1)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N+2) of the (N+2)-th pixel row. Consequently, the pixel transistor 11b(N+1) in the (N+1)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a(N+1). At the same time, the pixel transistor 11e(N+2) in the (N+2)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a(N+2) are shorted, and the driver transistor 11a(N+2) is reset.
According to the above-described stage-stage gate control system of the present invention, the driver transistor 11a is reset for a period of 1 H, and then voltage (current) programming is performed.
As in the case of
After the state in
When performing voltage programming for white display using the configuration shown in
After the current programming in
As described above, the reset driving according to the present invention using the voltage programming shown in
In the above example, the transistor 11d is turned on and off to control the current delivered from the driver transistor element 11a (in the case of configuration shown in
Incidentally, although the pixel configuration for current programming illustrated in
According to the invention, since this method passes current through the EL elements 15 intermittently, it can be used in combination with a method (described with reference to
In
Incidentally, although four gate signal lines 17b are grouped into a block here, this is not restrictive and it goes without saying that more than four gate signal lines 17b may be grouped into a block. Generally, it is preferable to divide the screen 50 into five or more parts. More preferably, the screen 50 should be divided into ten or more parts. Even more preferably, the screen 50 should be divided into twenty or more parts. A small number of divisions will make flickering conspicuous. Too large a number of divisions will increase the number of illumination control lines 401, making it difficult to lay out the illumination control lines 401.
Thus, in the case of a QCIF display panel, which has 220 vertical scanning lines, at least 220/5=44 or more lines should be grouped into a block. More preferably, 220/10=11 or more lines should be grouped into a block. However, if odd-numbered rows and even-numbered rows are grouped into two different blocks, there is not much flickering even at a low frame rate, and thus the two blocks are sufficient.
In the example shown in
Incidentally, in the example in
The gate driver circuit 12 is connected with the gate signal lines 17a. When a turn-on voltage is applied to gate signal lines 17a, the appropriate pixel rows are selected and the transistors 11b and 11c in the selected pixel rows are turned on. Then, currents (voltage) applied to the source signal lines 18 are programmed into the capacitors 19 in the pixels. On the other hand, the gate signal lines 17b are connected with the gate (G) terminals of the transistors 11d in the pixels. Thus, when a turn-on voltage (Vgl) is applied to the illumination control lines 401, current paths are formed between the driver transistors 11a and EL elements 15. When a turn-off voltage (Vgh) is applied, the anode terminals of the EL elements 15 are opened.
Preferably, control timing of turn-on/turn-off voltages applied to the illumination control lines 401 and a pixel row selection voltage (Vgl) outputted to the gate signal lines 17a by the gate driver circuit 12 are synchronized with one horizontal scanning clock (1H). However, this is not restrictive.
The signals applied to the illumination control lines 401 simply turn on and off the current delivered to the EL elements 15. They do not need to be synchronized with image data outputted from the source driver circuits 14. This is because the signals applied to the illumination control lines 401 are intended to control the current programmed into the capacitors 19 in the pixels 16. Thus, they do not always need to be synchronized with the pixel row selection signal. Even when they are synchronized, the clock is not limited to a 1-H signal and may be a ½-H or ¼-H signal.
Even in the case of the current-mirror pixel configuration shown in
Incidentally, in
In the above example, one selection pixel row is placed (formed) per pixel row. The present invention is not limited to this and a selection gate signal line may be placed (formed) for two or more pixel rows.
Thus, when the gate signal line 17a is selected, the pixels 16R, 16G, and 16B are selected and get ready to write data. The pixel 16R writes data into a capacitor 19R via a source signal line 18R, the pixel 16G writes data into a capacitor 19G via a source signal line 18G, and the pixel 16B writes data into a capacitor 19B via a source signal line 18B.
The transistor 11d of the pixel 16R is connected to a gate signal line 17bR, the transistor 11d of the pixel 16G is connected to a gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to a gate signal line 17bB. Thus, an EL element 15R of the pixel 16R, EL element 15G of the pixel 16G, and EL element 15B of the pixel 16B can be turned on and off separately. Illumination times and illumination periods of the EL element 15R, EL element 15G, and EL element 15B can be controlled separately by controlling the gate signal line 17bR, gate signal line 17bG, and gate signal line 17bB.
To implement this operation, in the configuration in
Incidentally, although it has been stated that a current N times larger than a predetermined current is passed through the source signal line 18 and that a current N times larger than a predetermined current is passed through the EL element 15 for a period of 1/N, this cannot be implemented in practice. Actually, signal pulses applied to the gate signal line 17 penetrate into the capacitor 19, making it impossible to set a desired voltage value (current value) on the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set on the capacitor 19. For example, even if 10 times larger current value is meant to be set, only approximately 5 times larger current value is set on the capacitor 19. For example, even if N=10 is specified, N=5 times larger current actually flows through the EL element 15. Thus, this method sets an N times larger current value to pass a current proportional or corresponding to the N-fold value through the EL element 15. Alternatively, this drive method applies a current larger than a desired value to the EL element 15 in a pulsed manner.
This method performs current (voltage) programming so as to obtain desired emission brightness of the EL element by passing a current larger than a desired value intermittently through the driver transistor 11a (in the case of
Incidentally, a compensation circuit which employs the penetration to the capacitor 19 is installed in the source driver circuit 14. This will be described later.
Preferably, N-channel transistors are used as the switching transistors 11b and 11c, etc. in
Depending on pixel configuration, if the penetration voltage tends to increase the current flowing through the EL element 15, white peak voltage will increase, increasing perceived contrast in image display. This provides for a good image display.
Conversely, it is also useful to use P-channel transistors as the switching transistors 11b and 11c in
Another drive method according to the present invention will be described below with reference to drawings.
Signals outputted from the source driver circuit 14 to the connection terminals 761 are allocated to 18R, 18G, and 18B by an output switching circuit 1741. The output switching circuit 1741 is formed directly on a board 71 by polysilicon technology. Alternatively, the output switching circuit 1741 may be formed with silicon chips and mounted on the board 71 by COG technology. Also, the output switching circuit 1741 may be incorporated into the source driver circuit 14 as a sub-circuit of the source driver circuit 14.
If a changeover switch 1742 is connected to an R terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18R. If the changeover switch 1742 is connected to a G terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18G. If the changeover switch 1742 is connected to a B terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18B.
Incidentally, in the configuration in
When the changeover switch 1742 is connected to the G terminal, the R terminal and B terminal of the changeover switch are open. Thus, the current entering the source signal lines 18R and 18B is 0 A. Consequently, the pixels 16 connected to the source signal lines 18R and 18B provide a black display.
In the configuration in
Basically, if one frame consists of three fields, R image data is written in sequence into the pixels 16 in the screen 50 in the first field. In the second field, G image data is written in sequence into the pixels 16 in the screen 50. In the third field, B image data is written in sequence into the pixels 16 in the screen 50.
Thus, R data→G data→B data→R data→ . . . are rewritten in sequence in the appropriate fields to implement sequential driving. Description of how N-fold pulse driving is performed by turning on and off the switching transistor 11d as shown in
In the above example, it has been stated that when image data is written into the R pixel 16, black data is written into the G pixel and B pixel, that when image data is written into the G pixel 16, black data is written into the R pixel and B pixel, and that when image data is written into the B pixel 16, black data is written into the R pixel and G pixel. The present invention is not limited to this.
For example, when image data is written into the R pixel 16, the G pixel and B pixel may retain the image data rewritten in the previous field. This can make the screen 50 brighter. When image data is written into the G pixel 16, the R pixel and B pixel may retain the image data rewritten in the previous field. When image data is written into the B pixel 16, the G pixel and R pixel may retain the image data rewritten in the previous field.
In order to retain image data in pixels other than the color pixel being rewritten, the gate signal line 17a can be controlled separately for the R, G, and B pixels. For example, as illustrated in
With the above configuration, when the source driver circuit 14 outputs R image data and the changeover switch 1742 is set to an R contact, a turn-on voltage can be applied to the gate signal line 17aR and a turn-off voltage can be applied to the gate signal lines aG and aB. Thus, the R image data can be written into the R pixel 16 and the G pixel 16 and R pixel 16 can retain the image data of the previous field.
When the source driver circuit 14 outputs G image data in the second field and the changeover switch 1742 is set to aG contact, a turn-on voltage can be applied to the gate signal line 17aG and a turn-off voltage can be applied to the gate signal lines aR and aB. Thus, the G image data can be written into the G pixel 16 and the R pixel 16 and B pixel 16 can retain the image data of the previous field.
When the source driver circuit 14 outputs B image data in the third field and the changeover switch 1742 is set to aB contact, a turn-on voltage can be applied to the gate signal line 17aB and a turn-off voltage can be applied to the gate signal line aR and aG. Thus, the B image data can be written into the B pixel 16 and the R pixel 16 and G pixel 16 can retain the image data of the previous field.
In the example shown in
In relation to the configuration in
In the state shown in
In the above state, the B pixel is being rewritten and a black display voltage is applied to the R pixel and G pixel. As the changeover switches 1742 are controlled in the above manner, an image composed of the pixels 16 are rewritten. Incidentally, control of the gate signal lines 17b is the same as in the examples described above, and thus detailed description thereof will be omitted.
In the above example, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten changes every field. The present invention is not limited to this. The color of the pixel rewritten may be changed every horizontal scanning period (1 H). For example, a possible drive method involves rewriting the R pixel in the first H, the G pixel in the second H, the B pixel in the third H, the R pixel in the fourth H, and so on. Of course, the color of the pixel rewritten may be changed every two horizontal scanning periods or every ⅓ field.
Needless to say, in the drive system in FIGS. 174 to 178, it is also possible to use the N-fold pulse driving in
One frame need not necessarily consist of three fields and may consist of two fields or four or more fields. In one example illustrated herein, one frame consists of two fields and the R and G pixels out of the three primary RGB colors are rewritten in the first field and the B pixel is rewritten in the second field. In another example illustrated herein, one frame consists of four fields and the R pixel out of the three primary RGB colors is rewritten in the first field, the G pixel is rewritten in the second field, and the B pixel is rewritten in the third and fourth field. In these sequences, white balance can be achieved more efficiently if the luminous efficiencies of the R, G, and B EL elements 15 are taken into consideration.
In the above example, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten changes every field.
According to the example shown in
According to the example shown in
Thus, by rewriting the R, G, and B pixels in each field arbitrarily or with some regularity, it is possible to prevent separation among the R, G, and B colors. Also, flickering is reduced.
In
In
Incidentally, even in the example in
As shown in
The panel in an example in
Needless to say, the drive method in
Incidentally, for ease of explanation, it is assumed that the display panel according to the present invention has the three primary colors RGB, but this is not restrictive. The display panel may have cyan, yellow, and magenta in addition to R, G, and B, or it may have any one of R, G, and B or any two of R, G, and B.
Also, although it has been stated that the sequential driving system handles R, G, and B in each field, it goes without saying that the present invention is not limited to this. Besides, the examples in FIGS. 174 to 178 illustrate how image data is written into pixels 16. They do not illustrate (although, of course, they are related to) a method of displaying images by operating the transistors 11d and passing current through the EL elements 15 unlike in
Also, the drive methods in
With organic EL display panels, B often has a low luminous efficiency. By making the B display area 53B larger than the display areas 53 of other colors as shown in
The drive system according to the present invention is not limited to either
Incidentally, the drive method in
The above driving can be implemented by forming or placing a gate driver circuit 12bR which controls the gate signal line 17bR, a gate driver circuit 12bG which controls the gate signal line 17bG, and a gate driver circuit 12bB which controls the gate signal line 17bB, as illustrated in
Also, with the configuration shown in FIGS. 174 to 177, the drive method in
It has been stated with reference to
Thus, the unit length of a conduction period is 1 H.
However, the present invention is not limited to this. The duration of the conduction period may be less than 1 H (½ H in
In short, the unit length of the conduction period is not limited to 1 H and a unit length other than 1 H can be generated easily. The OEV2 circuit formed or placed in the output stage of the gate driver circuit 12b (circuit which controls the gate signal line 17b) can be used for that.
To introduce a concept of output enable (OEV), the following provisions are made. By performing OEV control, turn-on and turn-off voltages (Vgl voltage and Vgh voltage) can be applied to the pixels 16 from the gate signal line 17a and 17b within one horizontal scanning period (1 H).
For ease of explanation, it is assumed that in the display panel according to the present invention, the pixel rows to be programmed with current are selected by the gate signal line 17a (in the case of
The gate driver circuits 12 are fed a start pulse, which is shifted as holding data in sequence within a shift register. Based on the holding data in the shift register of the gate driver circuit 12a, it is determined whether to output a turn-on voltage (Vgl) or turn-off voltage (Vgh) to the WR-side selection signal line. An OEV1 circuit (not shown) which turns off output forcibly is formed or placed in an output stage of the gate driver circuit 12a. When the OEV1 circuit is low, a WR-side selection signal which is an output of the gate driver circuit 12a is output as it is to the gate signal line 17a. The above relationship is illustrated logically in
That is, when the gate driver circuit 12a outputs a turn-off voltage, the turn-off voltage is applied to the gate signal line 17a. When the gate driver circuit 12a outputs a turn-on voltage (logic low), it is ORed with the output of the OEV1 circuit by the OR circuit and the result is output to the gate signal line 17a. That is, when the OEV1 circuit is high, the turn-off voltage (Vgh) is output to the gate driver signal line 17a (see an exemplary timing chart in
Based on holding data in a shift register of the gate driver circuit 12b, it is determined whether to output a turn-on voltage (Vgl) or turn-off voltage (Vgh) to the gate signal line 17b (EL-side selection signal line). An OEV2 circuit (not shown) which turns off output forcibly is formed or placed in an output stage of the gate driver circuit 12b. When the OEV2 circuit is low, an output of the gate driver circuit 12b is output as it is to the gate signal line 17b. The above relationship is illustrated logically in
That is, when the gate driver circuit 12b outputs a turn-off voltage (an EL-side selection signal is a turn-off voltage), the turn-off voltage is applied to the gate signal line 17b. When the gate driver circuit 12b outputs a turn-on voltage (logic low), it is ORed with the output of the OEV2 circuit by the OR circuit and the result is output to the gate signal line 17b. That is, when an input signal is high, the OEV2 circuit outputs the turn-off voltage (Vgh) to the gate driver signal line 17b. Thus, even if the EL-side selection signal from the OEV2 circuit is a turn-on voltage, the turn-off voltage (Vgh) is output forcibly to the gate signal line 17b. Incidentally, if an input to the OEV2 circuit is low, the EL-side selection signal is output directly to the gate signal line 17b (see the exemplary timing chart in
Incidentally, screen brightness is adjusted under the control of OEV2. There are permissible limits to changes in screen brightness.
In
In the second field which follows the first field, a turn-on voltage little shorter than 1 H is applied to the gate signal lines 17b (EL-side selection signal lines) in even-numbered pixel rows. A turn-on voltage is applied to the gate signal lines 17b (EL-side selection signal lines) in odd-numbered pixel rows for a very short period. The duration T1 of the turn-on voltage applied to the gate signal lines 17b (EL-side selection signal lines) in even-numbered pixel rows plus the duration T2 of the turn-on voltage applied to the gate signal lines 17b (EL-side selection signal lines) in odd-numbered pixel rows is designed to be 1 H.
The sum duration of turn-on voltage applications to gate signal lines 17b in a plurality of pixel rows may be designed to be constant. Alternatively, the illumination time of each EL element 15 in each pixel row in each field may be designed to be constant.
Referring to
Incidentally, in the example in
By adjusting the duration of application of the turn-on voltage to the gate signal line 17B (EL-side selection signal line), it is possible to adjust the brightness of the display screen 50 linearly. This can be done easily through control of the OEV2 circuit. Referring to
As shown in
One of the problems with the N-fold pulse driving according to the present invention is that a current N times larger than in the case of the conventional is applied to the EL element 15 although instantaneously. A large current may lower the life of the EL element. To solve this problem, it maybe useful to apply a reverse bias voltage Vm to the EL element.
Application of a reverse bias voltage means application of a reverse current, and thus injected electrons and positive holes are drawn to the negative and positive poles, respectively. This makes it possible to cancel formation of space charge in the organic layer and reduce electro-chemical degradation, thereby prolonging the life.
The vertical axis represents the ratio of the terminal voltage after 2500 hours to the initial terminal voltage of the EL element 15.
For example, if the terminal voltage is 8V and 10V, respectively, when a current with a current density of 100 A per square meter is applied at time 0 (zero) and after 2500 hours, the terminal voltage ratio is 10/8=1.25.
The horizontal axis represents the ratio of the product of the reverse bias voltage Vm and its application duration t1 in a period to a rated terminal voltage V0. For example, if the reverse bias voltage Vm is applied at 60 Hz (60 Hz has no particular meaning) for ½ (half) a period, then t1=0.5. Also, if the terminal voltage (rated terminal voltage) is 8 V when a current with a current density of 100 A per square meter is applied at time 0 (zero) and if the reverse bias voltage Vm is 8 V, then |reverse bias voltage×t1/(rated terminal voltage×t2)=|−8 (V)×0.5|/(8 (V)×0.5)=1.0.
In
However, for bias driving, the reverse bias Vm and rated current should be applied alternately. To equalize average brightness of samples A and B over a unit time as shown in
However, in
Generally, in the case of video display, the current applied to (passed through) each EL element 15 is approximately 0.2 of a white peak current (a current which flows at a rated terminal voltage, or a current with a current density of 100 A per square meter according to examples cited herein).
Therefore, for video display in the example in
That is, on the horizontal axis (|reverse bias voltage×t1|/(rated terminal voltage×t2)) in
The reverse bias driving according to the present invention will be described below with reference to drawings. In a pixel configuration for reverse bias driving, an N-channel transistor 11g is used as shown in
In
In the pixel configuration in
Also, a gate driver circuit 12c may be formed or placed separately to control the reverse bias line 471 as illustrated in
The drive method described above makes it possible to apply the reverse bias voltage Vm to the EL element 15 by varying only the potential of the reverse bias line 471 with the gate (G) terminal of the transistor 11g set at a fixed potential. This makes it easy to control the application of the reverse bias voltage Vm.
The reverse bias voltage Vm is applied when current is not passed through the EL element 15. This can be done by turning on the transistor 11g when the transistor 11d is off. That is, the reverse of on/off logic of the transistor 11d can be applied to the gate potential control line 473. For example, in
When a turn-on voltage (Vgl) is applied to the gate signal line 17a(1) in the first pixel row, a turn-off voltage (Vgh) is applied to the gate signal line 17b(1) in the first pixel row. Thus, the transistor 11d is off and current does not flow through the EL element 15.
A voltage Vsl (which turns on the transistor 11g) is applied to a reverse bias line 471(1). Thus, the transistor 11d is on and a reverse bias voltage is applied to the EL element 15. The reverse bias voltage is applied a predetermined period (1/200 of 1 H or longer; or 0.5 μsec) after the turn-off voltage (Vgh) is applied to the gate signal line 17b. The reverse bias voltage is turned off a predetermined period (1/200 of 1 H or longer; or 0.5 μsec) before the turn-on voltage (Vgl) is applied to the gate signal line 17b. This is done in order to prevent the transistors 11d and 11g from turning on simultaneously.
In the next 1 H (horizontal scanning period), a turn-off voltage (Vgh) is applied to the gate signal line 17a, and the second pixel row is selected. That is, a turn-on voltage is applied to a gate signal line 17b(2). On the other hand, a turn-on voltage (Vgl) is applied to the gate signal line 17b, the transistor 11d is turned on, and a current from the transistor 11a flows through the EL element 15, causing the EL element 15 to emit light. Also, a turn-off voltage (Vsh) is applied to the reverse bias line 471(1) stopping the reverse bias voltage from being applied to the EL elements 15 in the first pixel row (1). The voltage Vsl (reverse bias voltage) is applied to a reverse bias line 471(2) in the second pixel row.
As the above operations are repeated in sequence the images on the entire screen is rewritten. In the above example, a reverse bias voltage is applied while the pixels are being programmed. However, the circuit configuration in
Reverse bias voltage can be applied not only during image display.
The reverse bias voltage may be applied for a predetermined period after the EL display apparatus is turned off.
Although the above example has been described with reference to the pixel configuration in
When the EL element 15 is not illuminated, the transistor 11g turns on, applying a reverse bias voltage to the EL element 15. Thus, the reverse bias voltage is applied while the transistor 11d is on. Consequently, the transistor 11d and transistor 11g turn on simultaneously in logical terms.
The voltage Vsg is applied continuously to the gate (G) terminal of the transistor 11g.
The transistor 11g turns on when a reverse bias voltage sufficiently smaller than the voltage Vsg is applied to the reverse bias line 471.
Subsequently, when there comes a horizontal scanning period in which a video signal is applied to (written into) the pixel, a turn-on voltage is applied to a gate signal line 17a1, turning on the transistor 11c.
Thus, a video signal voltage outputted from the source driver circuit 14 to the source signal line 18 is applied to the capacitor 19 (the transistor 11d remains on).
When the transistor 11d is turned on, the pixel is put into black display mode.
The longer the conduction period of the transistor 11d in one field (one frame) period, the larger the proportion of the black display period. Thus, the brightness during a display period needs to be increased to obtain a desired average brightness over one field (one frame) in spite of the black display period. That is, the current to be passed through the EL element 15 during the display period needs to be increased. This operation is based on the N-fold pulse driving according to the present invention. Thus, an operation characteristic of the present invention is implemented by a combination of the N-fold pulse driving and driving which involves creating a black display by turning on the transistor 11d. Also, a configuration (method) characteristic of the present invention involves applying a reverse bias voltage to the EL element 15 when the EL element 15 is not illuminated.
The N-fold pulse driving allows a predetermined current (programmed current (at a voltage held in the capacitor 19)) to be passed through the EL element 15 again during one field (one frame) period even after a black display is created once. With the configuration in
Incidentally, although the above example uses a pixel configuration for current programming, the present invention is not limited to this and is applicable to other current-based pixel configurations such as those shown in
With the pixel configuration in
To describe the configuration in
The initialization operation is performed after a horizontal synchronization signal (HD) is provided. A turn-on voltage is applied to the gate signal line 17b, turning on the transistor 11g. Besides, a turn-on voltage is also applied to the gate signal line 17a, turning on the transistor 11c. At this time, a voltage Vdd is applied to the source signal line 18. Thus, the voltage Vdd is applied to a terminal a of the capacitor 19b. In this state, the driver transistor 11a turns on and a small current flows through the EL element 15. This current makes the voltage on the drain (D) terminal of the driver transistor 11a larger in absolute value than at least the voltage at an operating point of the driver transistor 11a.
Next, the reset operation is performed. A turn-off voltage is applied to the gate signal line 17b, turning off the transistor 11e. On the other hand, a turn-on voltage is applied to the gate signal line 17c for a period of T1, turning on the transistor 11b. The period T1 corresponds to a reset period. A turn-on voltage is applied to the gate signal line 17a continuously for a period of 1 H. Preferably, the period T1 is between 20% and 90% (both inclusive) of 1 H or between 20 μsec and 160 μsec (both inclusive). Preferably, a capacitance ratio Ca/Cb between a capacitor 19b (Cb) and capacitor 19a (Ca) is between 1/6 and 2/1 (both inclusive) During a reset period, the transistor 11b turns on, short-circuiting the gate (G) terminal and drain (D) terminal of the driver transistor 11a. Thus, the voltages at the gate (G) terminal and drain (D) terminal of the transistor 11a become equal, putting the transistor 11a in an offset mode (reset mode: a state in which no current flows). In the reset mode, the voltage at the gate (G) terminal of the transistor 11a approaches a starting voltage at which a current starts to flow. A gate voltage which maintains the reset mode is held at a terminal b of the capacitor 19b. Thus, the capacitor 19 holds an offset voltage (reset voltage).
In a next programming mode, a turn-off voltage is applied to the gate signal line 17c, turning off the transistor 11b. On the other hand, DATA voltage is applied to the source signal line 18 for a period of Td. Thus, the sum of the DATA voltage and offset voltage (reset voltage) is applied to the gate (G) terminal of the driver transistor 11a. This allows the driver transistor 11a to pass a programmed current.
After the programming period, a turn-off voltage is applied to the gate signal line 17a, turning off the transistor 11c and cutting off the driver transistor 11a from the source signal line 18. Besides, a turn-off voltage is also applied to the gate signal line 17c, turning off the transistor 11b, which remains off for a period of 1F. On the other hand, a turn-on voltage and turn-off voltage are applied to the gate signal line 17b periodically, as required. Thus, if combined with N-fold pulse driving in
With the drive system in
To apply the reverse bias voltage Vm to the EL element 15, it is necessary to turn off the transistor 11a. To turn off the transistor 11a, the Vdd terminal and gate (G) terminal of the transistor 11a can be short-circuited. This configuration will be described with reference to
Alternatively, it is possible to apply the Vdd voltage or a voltage which turns off the transistor 11a to the source signal line 18, turn on the transistor 11b, and apply the voltage to the gate (G) terminal of the transistor 11a. This voltage turns off the transistor 11a (or makes it pass almost no current (almost off: the transistor 11a is in a high-impedance state)). Subsequently, the transistor 11g is turned on and a reverse bias voltage is applied to the EL element 15.
Next, reset driving in the pixel configuration in
Thus, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c in the pixel 16a, the pixel 16a enters voltage programming mode, the reset transistor 11b of the pixel 16b in the next stage turns on, and the driver transistor 11a of the pixel 16b is reset. Similarly, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c in the pixel 16b, the pixel 16b enters current programming mode, the reset transistor 11b of the pixel 16c in the next stage turns on, and the driver transistor 11a of the pixel 16c is reset. Thus, reset driving by way of a preceding-stage gate control system can be implemented easily. Also, the number of leads from a gate signal line per pixel can be reduced.
More detailed description will be provided. Suppose voltage is applied to gate signal lines 17 as shown in
In this state, the pixel 16a is in voltage programming mode and is not illuminated, the pixel 16b is in reset mode and not illuminated, the pixel 16c is pending current programming and is illuminated, and the pixel 16d is pending current programming and is illuminated.
After 1 H, data in a shift register 61 circuit of the controlling gate driver circuit 12 is shifted one bit to enter a state shown in
Thus, it can be seen that the voltage applied to the gate signal line 17a of each pixel resets the driver transistor 11a of the pixel in the next stage to perform voltage programming in the next horizontal scanning period sequentially.
The pixel configuration for voltage programming in
In
Thus, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b in the pixel 16a, the pixel 16a enters voltage programming mode, the reset transistor 11e of the pixel 16b in the next stage turns on, and the driver transistor 11a of the pixel 16b is reset. Similarly, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b in the pixel 16b, the pixel 16b enters current programming mode, the reset transistor 11e of the pixel 16c in the next stage turns on, and the driver transistor 11a of the pixel 16c is reset. Thus, reset driving by way of a preceding-stage gate control system can be implemented easily.
More detailed description will be provided. Suppose voltage is applied to gate signal lines 17 as shown in
In this state, the pixel 16a is in voltage programming mode, the pixel 16b is in reset mode, the pixel 16c is pending current programming, and the pixel 16d is pending current programming.
After 1 H, data in the shift register 61 circuit of the controlling gate driver circuit 12 is shifted one bit to enter a state shown in
Thus, it can be seen that the voltage applied to the previous stage for the gate signal line 17a of each pixel resets the driver transistor 11a of the pixel in the next stage to perform voltage programming in the next horizontal scanning period sequentially.
For completely black display in current driving, the driver transistors 11 of the pixels are programmed with 0 current. That is, the source driver circuit 14 delivers no current. When no current is delivered, parasitic capacitance caused in the source signal line 18 cannot be discharged and the potential of the source signal line 18 cannot be varied. Consequently, the gate potential of the driver transistors also remains unchanged and the potential in the previous frame (field) (1 F) remains accumulated in the capacitor 19. For example, if the previous frame contains white display, the white display is retained even if the current frame contains completely black display.
To solve this problem, according to the present invention, a black level voltage is written into the source signal line 18 at the beginning of one horizontal scanning period (1 H) before the current to be programmed is output to the source signal line 18. For example, if image data consists of the 0th to 7th gradations close to black level, a black level voltage is written only during a certain period at the beginning of one horizontal scanning period to reduce the load of current programming and make up for insufficient writing.
Incidentally, completely black display corresponds to the 0th gradation and white display corresponds to the 63rd gradation (in the case of 64-gradation display). Precharging will be described in detail later.
The current-driven source driver IC (circuit) 14 according to the present invention will be described below. The source driver IC according to the present invention is used to implement the drive methods and drive circuits according to the present invention described earlier. It is used in combination with drive methods, drive circuits, and display apparatus according to the present invention. Incidentally, although the source driver circuit will be described as an IC chip, this is not restrictive and the source driver circuit may be built on the display panel using low-temperature polysilicon technology, or the like.
First, an example of a conventional current-driven source driver circuit is shown in
In
If the resistance of the resister 691 is 1 MΩ and the output of the D/A converter 721 is 1 (V), a current of 1 (V)/1 MΩ=1 (μA) flows through the resister 691, forming a constant current circuit. Thus, analog output of the D/A converter 721 varies with the value of data signal, and a predetermined current flows through the resister 691 according to the analog output to provide a programming current Iw.
However, the D/A converter circuit 721 has a large circuit scale. So does the operational amplifier 722. Formation of the D/A converter circuit 721 and operational amplifier 722 in a single output circuit results in a huge source driver IC 14, which is practically impossible to build.
The present invention has been made in view of the above point. The source driver circuit 14 according to the present invention has a circuit configuration and layout configuration which reduces the scale of a current output circuit and minimizes variations in output current among current output terminals.
In
For example, when driving the source signal lines 18 with one driver IC 14, there are 176 outputs (because the source signal lines require a total of 176 outputs for R, G, and B) Here it is assumed that N=16 and M=11. Thus, 16×11=176 and the 176 outputs can be covered. In this way, by using a multiple of 8 or 16 for N or M, it becomes easier to lay out and design the current sources of the driver IC.
The current-driven source driver IC (circuit) 14 employing the multi-stage current mirror circuit according to the present invention can absorb variations in transistor characteristics because it has the second-stage current sources 632 in between instead of copying the current value of the first-stage current source 631 directly to N×M third-stage current sources 633 using the current mirror circuit.
In particular, the present invention is characterized in that a first-stage current mirror circuit (current source 631) and second-stage current mirror circuits (current sources 632) are placed close to each other. If a first-stage current source 631 are connected with third-stage current sources 633 (i.e., in the case of two-stage current mirror circuit), the second-stage current sources 633 connected to the first-stage current source are large in number, making it impossible to place the first-stage current source 631 and third-stage current sources 633 close to each other.
The source driver circuit 14 according to the present invention copies the current value of the first-stage current mirror circuit (current source 631) to the second-stage current mirror circuits (current sources 632), and the current values of the second-stage current mirror circuits (current sources 632) to the third-stage current mirror circuits (current sources 632). With this configuration, the second-stage current mirror circuits (current sources 632) connected to the first-stage current mirror circuit (current source 631) are small in number. Thus, the first-stage current mirror circuit (current source 631) and second-stage current mirror circuits (current sources 632) can be placed close to each other.
If transistors composing the current mirror circuits can be placed close to each other, naturally variations in the transistors are reduced, and so are variations in current values. The number of the third-stage current mirror circuits (current sources 633) connected to the second-stage current mirror circuits (current sources 632) are reduced as well. Consequently, the second-stage current mirror circuits (current sources 632) and third-stage current mirror circuits (current sources 633) can be placed close to each other.
That is, transistors in current receiving parts of the first-stage current mirror circuit (current source 631), second-stage current mirror circuits (current sources 632), and third-stage current mirror circuits (current sources 633) can be placed close to each other on the whole. In this way, transistors composing the current mirror circuits can be placed close to each other, reducing variations in the transistors and greatly reducing variations in current signals from output terminals. A multi-stage current mirror circuit consisting of three stages has been cited in the above example for the sake of simplicity. Needless to say, the larger the number of stages, the smaller the current variations in the source driver IC 14 of the current-driven display panel. Thus, the number of stages of a current mirror circuit is not limited to three and may be more than three.
In the present invention, the terms “current sources 631, 632, and 633” and “current mirror circuits” are used interchangeably. That is, current sources are a basic construct of the present invention and the current sources are embodied into current mirror circuits. Thus, a current source is not limited to a current mirror circuit and may be a current circuit consisting of a combination of a operational amplifier 722, transistor 631, and register R as shown in
Incidentally, the transistors composing the source driver IC (circuit) 14 according to the present invention are not limited to a MOS type and may be a bipolar type. Also, they are not limited to silicon semiconductors and may be gallium arsenide semiconductors. Also, they may be germanium semiconductors. Alternatively, they may be formed directly on a substrate using low-temperature polysilicon technology, other polysilicon technology, or amorphous silicon technology.
Sixty-four (64) gradations require one D0-bit unit transistor 634, two D1-bit unit transistors 634, four D2-bit unit transistors 634, eight D3-bit unit transistors 634, sixteen D4-bit unit transistors 634, and thirty-two D5-bit unit transistors 634 for a total of sixty-three unit transistors 634. Thus, the present invention produces one output using as many unit transistors 634 as the number of gradations (64 gradations in this example) minus 1. Incidentally, even if one unit transistor is divided into a plurality of sub-unit transistors, this simply means that a unit transistor is divided into sub-unit transistors, and makes no difference in the fact that the present invention uses as many unit transistors as the number of gradations minus 1.
In
For example, when a D1 input terminal is high (positive logic), a switch 641b is closed. Then, current flows to two current sources (single-unit) 634 composing a current mirror. The current flows through the internal wiring 643 in the IC 14. Since the internal wiring 643 is connected to the source signal line 18 via a terminal electrode of the IC 14, the current flowing through internal wiring 643 provides a programming current for the pixels 16.
The same applies to the other switches 641. When a D2 input terminal is high (positive logic), a switch 641c is closed. Then, current flows to four current sources (single-unit) 634 composing a current mirror. When a D5 input terminal is high (positive logic), a switch 641f is closed. Then, current flows to 32 (thirty-two) current sources (single-unit) 634 composing a current mirror.
In this way, based on external data (D0 to D5), current flows to the corresponding current sources (single-unit). That is, current flows to 0 to 63 current sources (single-unit) depending on the data.
Incidentally, for ease of explanation, it is assumed that there are 63 current sources for a 6-bit configuration, but this is not restrictive. In the case of 8-bit configuration, 255 unit transistors 634 can be formed (placed). For a 4-bit configuration, 15 unit transistors 634 can be formed (placed) The transistors 634 constituting the unit current sources have a channel width W and channel width L. The use of equal transistors makes it possible to construct output stages with small variations.
Besides, not all the current sources 634 need to pass equal current. For example, individual current sources 634 may be weighted. For example a current output circuit may be constructed using a mixture of single-unit current sources 634, double-sized current sources 634, quadruple-sized current sources 634, etc. However, if current sources 634 are weighted, the weighted current sources may not provide the right proportions, resulting in variations. Thus, even when using weighting, it is preferable to construct each current source from transistors each of which corresponds to a single-unit current source.
The unit transistor 634 should be equal to or larger than a certain size. The smaller the transistor size, the larger the variations in output current. The size of a transistor 634 is given by the channel length L multiplied by the channel width W. For example, if W=3 μm and L=4 μm, the size of the unit transistor 634 constituting a unit current source is W×L=12 square μm. It is believed that crystal boundary conditions of silicon wafers have something to do with the fact that a smaller transistor size results in larger variations. Thus, variations in output current of transistors are small when each transistor is formed across a plurality of crystal boundaries.
Relationship between size of transistors and variations in output current is shown in
In the case of 64 gradations, 100/64=1.5%. Thus, the variations in the output current must be within 1.5%. From
In the case of 128 gradations, 100/128=1%. Thus, the variations in the output current must be within 1%. From
Generally, if the number of gradations is K and the size of a unit transistor 634 is St (square μm), the following relationship should be satisfied:
40≦K/{square root}{square root over ( )}(St) and St≦300
More preferably, the following relationship should be satisfied:
120≦K/f{square root}{square root over ( )}(St) and St≦300
In the above example 64 gradations are represented by 63 transistors. When representing 64 gradations by 127 unit transistors 634, the unit-transistor 634 size is the total size of two unit transistors 634. For example, in the case where 64 gradations are represented by 127 unit transistors 634, if the size of a unit transistor 484 is 10 square μm, the unit-transistor 484 size is given in
It is necessary to take into consideration not only the size, but also the shape of the unit transistor 634. This is to reduce kink effect. A kink is a phenomenon in which current flowing through a unit transistor 634 changes when the voltage between the source (S) and drain (D) of the unit transistor 634 is varied with the gate voltage of the unit transistor 634 kept constant. In the absence of kink effect (in ideal state), the current flowing through the unit transistor 634 does not change even if the voltage applied between the source (S) and drain (D) of the unit transistor 484 is varied.
Kink effect occurs when the source signal lines 18 vary due to variations in Vt of driver transistors 11a shown in
Thus, the potentials of the source signal lines 18 vary due to variations in Vt of the driver transistors 11a in pixels 16. The potential of a source signal line 18 equals the source-drain voltage of the unit transistor 634 of the driver circuit 14. That is, variations in Vt of the driver transistors 11a in the pixels 16 cause the source-drain voltage applied to the unit transistors 634 to vary. Then, the source-drain voltage causes variations in the output voltage of the unit transistor 634 due to kinks.
When L/W equals 5/3, the output current remains almost unchanged even if the source-drain voltage rises. However, when L/W equals 1/1, the output current increases in approximate proportion to the source-drain voltage. Thus, the larger the L/W, the better.
In view of the above circumstances, it is preferable that L/W of a unit transistor is two or more.
However, a large L/W means a long L, and thus a large transistor size.
Thus, more preferably, L/W is 40 or less.
Besides, L/W also depends on the number of gradations. If the number of gradations is small, there is no problem even if there are variations in the output current of the unit transistor 634 due to kink effect because there are large differences between gradations. However, in the case of a display panel with a large number of gradations, since there are small differences between gradations, even small variations in the output current of the unit transistor 634 due to kink effect will decrease the number of gradations.
In view of the above circumstances, the driver circuit 14 according to the present invention is configured to satisfy the following relationship:
({square root}{square root over ( )}(K/16))≦L/W≦ and ({square root}{square root over ( )}(K/16))×20
where K is the number of gradations, L is the channel length of the unit transistor 634, and W is the channel width of the unit transistor. This relationship is illustrated in
This corresponds to the third-stage current mirror portion illustrated in
The variations in the output current of the unit transistor 634 also depend on the voltage resistance of the source driver IC 14. The voltage resistance of the source driver IC generally means the power supply voltage of the IC. For example, voltage resistance of 5 V means the use of the power supply voltage at a standard voltage of 5 V. Incidentally, IC voltage resistance can translate into maximum working voltage. Semiconductor IC makers have standardized voltage-resistance processes such as a 5-V voltage-resistance process and 10-V voltage-resistance process.
It is believed that film properties and film thickness of a gate insulating film of the unit transistor 634 have something to do with the fact that IC voltage resistance affects variations in the output current of the unit transistor 634. The transistors 634 produced in a process with high IC voltage resistance have a thick gate insulating film. This is intended to avoid dielectric breakdown even under application of a high voltage. A thick gate insulating film makes its control difficult and increases variations in its film properties. This increases variations in the transistors. Also, the transistors produced in a high voltage-resistance process have low mobility. With low mobility, even slight changes in electrons injected into transistor gates cause changes in characteristics. This increases variations in the transistors. To reduce variations in the unit transistors 634, it is preferable to adopt an IC process with low IC voltage resistance.
As can be seen from
In
On the other hand, the potential at an output terminal 64 in
Thus, a voltage of 0.5 V to ((Vw−Vb)+0.5) V is applied to the terminal 761 (during current programming, the gate terminal voltage of the driver transistor 11a of the pixel 16 is applied to the output terminal 761, which is connected with the source signal line 18). Since Vw−Vb equals 2 V, a voltage of up to 2 V+0.5 V=2.5 V is applied to the output terminal 761. Thus, even if the output voltage (current) of the source driver IC 14 is based on a rail-to-rail output, the IC voltage resistance must be 2.5V. The amplitude required by a terminal 741 is 2.5 V or more.
Thus, it is preferable to use a voltage resistance process in the range of 2.5-V to 10-V (both inclusive) for the source driver IC 14. More preferably, a voltage resistance process in the range of 3-V to 9-V (both inclusive) is used for the source driver IC 14.
Incidentally, it has been described that a voltage resistance process in the range of 2.5-V to 10-V (both inclusive) is used for the source driver IC 12. This voltage resistance is also applied to examples (e.g., a low-temperature polysilicon process) in which the source driver circuit 14 is formed directly on an array board 71. Working voltage resistance of a source driver circuit 14 formed directly on an array board 71 can be high and exceeds 15 V in some cases. In such cases, the power supply voltage used for the source driver circuit 14 may be substituted with the IC voltage resistance illustrated in
The area of a unit transistor 634 is correlated with the variations in its output current.
In
Thus, preferably, the channel width W of the unit transistor 634 is from 2 μm to 10 μm (both inclusive). More preferably, the channel width W of the unit transistor 634 is from 2 μm to 9 μm (both inclusive).
As illustrated in
D0, which is provided by one unit transistor 634, provides the value of the current flowing through the unit transistor 633 of the final-stage current source. D1, which is provided by two unit transistors 634, provides a two times larger current value than the final-stage current source. D2, which is provided by four unit transistors 634, provides a four times larger current value than the final-stage current source; and D5, which is provided by 32 unit transistors 484, provides a 32 times larger current value than the final-stage current source.
Accordingly, programming current Iw is output (drawn) to the source signal line via switches controlled by 6-bit image data consisting of D0, D1, D2, . . . , and D5. Thus, according to activation and deactivation of the 6-bit image data consisting of D0, D1, D2, . . . , and D5, currents 1 time, 2 times, 4 times, . . . and/or 32 times as large as the final-stage current source 633 are added and outputted to the output line. That is, according to activation and deactivation of the 6-bit image data consisting of D0, D1, D2, . . . , and D5, 0 to 63 times as large a current as the final-stage current source 633 is output from the output line (the current is drawn from the source signal line 18).
Actually, as illustrated in
The use of integral multiples of the current values of the final-stage current sources 633 thus makes it possible to control current values more accurately (reduce output variations among terminals) than conventional methods which use W/L-based proportional allotments.
However, this configuration is available only when the driver transistors 11a of pixels 16 are P-channel transistors and the current sources (single-unit transistors) 634 of the source driver IC 14 are N-channel transistors.
In other cases (e.g., when the driver transistors 11a of pixels 16 are N-channel transistors), the present invention can use a configuration in which the programming current Iw is a discharge current.
Now, a reference current generator circuit will be described in detail. Current output mode used for the source driver circuit (IC) 14 of the present invention uses a reference current and outputs the programming current Iw by combining unit currents which are proportional to a reference current (source drivers of liquid crystal display panels use voltage output mode, which uses steps of voltage as signals).
Output voltage of the operational amplifier 722 is fed to an N-channel transistor 1443 and the current flowing through the N-channel transistor 1443 flows through an external resistor 691. Incidentally, a resistor 691a is a fixed-chip resister. Basically, the resistor 691a is enough. A resistor 691b is a resistive element such as a posistor or thermistor whose value changes with temperature.
The resistor 691a is used to compensate for temperature characteristics of the EL element 15. The resistor 691a is inserted or placed in parallel or series with the resistor 691b according to (to compensate for) the temperature characteristics of the EL element 15. Incidentally, for ease of explanation, the resistor 691a and resistor 691b will be treated below as one resistor 691.
A resistor 691 with an accuracy of 1% or better is easily available. The resistor 691 may be built into the source driver IC 14 using diffused resistor technology or a polysilicon pattern. The chip resistor 691 is mounted on an input terminal 761a. In the case of EL display panels, in particular, the temperature characteristics of EL elements 15 differ among R, G, and B. Thus, three external resistors 691 are required for R, G, and B.
Terminal voltage of the resistor 691 provides a negative input to the operational amplifier 722 and the voltage at the negative terminal has the same magnitude as the voltage at a positive terminal of the operational amplifier 722. Thus, if a positive input voltage of the operational amplifier 722 is V1, the current obtained by dividing with this voltage by the resistance 691 flows through the transistor 1444. This current serves as the reference current. If the resistance of the resistor 691 is 100 KΩ and the input voltage of the positive terminal of the operational amplifier 722 is V1=1 (V), a reference current of 10 (μA) (=1 (V)/100 KΩ) flows through the resistor 691. Preferably, the reference current is set between 2 μA and 30 μA (both inclusive). More preferably, it is set between 5 μA and 20 μA (both inclusive) A small reference current flowing through the parent transistor 63 lowers the accuracy of the unit current source 634. Too large a reference current increases the current mirror factor converted (in the downward direction in this case) within the IC, increasing variations in the current mirror circuit, and thus lowering the accuracy of the unit current source 634 again.
The above configuration makes it possible to form an extremely accurate reference current (in terms of size and variations) provided that the positive input terminal of the operational amplifier 722 and the resistor 691 are accurate enough. When building the resistor 691 into the source driver circuit (IC) 14, it is recommended to trim the incorporated resistor to increase accuracy.
A reference voltage Vref received from a reference voltage circuit 1441 is applied to the positive terminal of the operational amplifier 722. Regarding ICs for the reference voltage circuit 1441 which outputs the reference voltage, various types are available from Maxim and other companies. Alternatively, the reference voltage Vref may be generated within the source driver circuit 14 (internally generated reference voltage Vref). Preferably, the reference voltage Vref ranges between 2 (V) and the anode voltage Vdd (V) (both inclusive).
The reference voltage is fed through a connection terminal 761a. Basically, the voltage Vref can be fed into the positive terminal of the operational amplifier 722. An electronic regulator circuit 561 is placed between the connection terminal 761a and positive terminal because the luminous efficiency of the EL elements 15 varies among R, G, and B. In other words, the electronic regulator circuit 561 is intended to adjust the current passed through each of the EL elements 15 for R, G, and B, and thereby achieve a white balance. Of course, what can be adjusted by the resistor 691 does not need to be adjusted by the electronic regulator circuit 561. For example, a variable resistor may be used as the resistor 691. One of the uses of the electronic regulator circuit 561 is to readjust white balance when the degradation rate of the EL elements 15 varies among R, G, and B. The EL elements 15 for B are especially prone to degradation. Thus, the EL elements 15 for B become darker with years of use of a EL display panel, turning the screen yellowish. In that case, the white balance is adjusted using the electronic regulator circuit 561 for B. Of course, brightness correction or white balance correction of the EL elements may be performed by linking the electronic regulator circuit 561 to a temperature sensor 781 (see
The electronic regulator circuit 561 is built into the IC (circuit) 14. Alternatively, it is formed directly on an array board 71 using the low-temperature poly-silicon technology. A plurality of unit resistors (R1, R2, R3, R4, . . . Rn) formed through polysilicon patterning are connected in series. Analog switches (S1, S2, S2, . . . Sn+1) are placed among the unit resistors, the reference voltage Vref is divided, and the resulting voltages are output.
In
In order to achieve full-color display on an EL display panel, it is necessary to provide a reference current for each of R, G, and B. The white balance can be adjusted by controlling the ratios of the RGB reference currents. In the case of current driving as well as the present invention, the value of current passed by the unit current source 634 is determined based on one reference current. Thus, the current passed by the unit current source 634 can be determined by determining the magnitude of the reference current. Consequently, the white balance in every gradation can be achieved by setting a reference current for each of R, G, and B. The above matters work because the source driver circuit 14 produces current outputs varied in steps (is current-driven). Thus, the point is how the magnitude of the reference current can be set for each of R, G, and B.
The light emission efficiency of an EL element is determined by, or depends heavily on, the thickness of a film vapor-deposited or applied to the EL element. The film thickness is almost constant within each lot. Through lot control of the film thickness of the EL element 15, it is possible to determine relationship between the current passed through the EL element 15 and light emission efficiency. That is, the current value used for white balancing is fixed for each lot.
For example, if the currents passed through the EL elements 15 for R, G, and B are Ir (A), Ig (A), and Ib (A), respectively, a ratio of reference currents which can achieve a white balance can be known on a lot-by-lot basis.
Therefore, a white balance can be achieved, for example, when Ir:Ig:Ib=1:2:4. With the duty ratio driving, etc. according to the present invention, once a white balance is achieved, it is applied to all gradations. This is accomplished by synergy between a drive method according to the present invention and source driver circuit according to the present invention.
With the configuration shown in
In
To trim the resistor array 1503, laser light 1502 can be emitted from a laser device 1501.
Incidentally it has been stated with reference to
For example, needless to say, the reference currents can be varied by varying the value of each of RGB reference voltages (VrefR, VrefG, and VrefB) in
It has been stated that 0 to 63 times the current of the final-stage current sources 633 is outputted, but this is true only when the current mirror factor of the final-stage current sources 633 is 1. When the current mirror factor is 2, 0 to 126 times the current of the final-stage current sources 633 is output and when the current mirror factor is 0.5, 0 to 31.5 times the current of the final-stage current sources 633 is output.
Thus, the present invention allows the values of output current to be changed easily by changing the current mirror factor of the final-stage current sources 633 or current sources (631, 632, etc.) in preceding stages. Preferably, the current mirror factor is varied (differed) separately for R, G, and B. The current mirror factor of any current source only for R, for example, may be varied (differed) from the other colors (from the current source circuits for the other colors). EL display panels, in particular, have different luminous efficiencies for different colors (R, G, and B; or cyan, yellow, and magenta). Thus, by varying the current mirror factor among different colors, it is possible to improve the white balance.
The current mirror factor of current sources may be varied (differed) from the other colors (from the current source circuits for the other colors) in an unfixed manner. It may be variable. The current mirror factor can be made variable by providing a plurality of transistors composing a current mirror circuit in a current source and changing, based on external signals, the number of transistors through which current current is passed. This configuration makes it possible to achieve an optimum white balance through adjustments while observing emission condition of manufactured EL display panels in various colors.
The present invention in particular is configured to connect current sources (current mirror circuits) in multiple stages. Thus, by varying the current mirror factor between the first-stage current source 631 and second-stage current sources 632, it is possible to vary the output currents of a large number of outputs easily using a small number of connections (current mirror circuits and the like). Needless to say, this makes it possible to vary the output currents of a large number of outputs easily using a smaller number of connections (current mirror circuits and the like) than by varying the current mirror factor between the second-stage current sources 632 and third-stage current sources 633.
Incidentally, varying a current mirror factor means varying (adjusting) a magnification factor of current. Thus, it is not limited to current mirror circuits. For example, it can be implemented by an operational amplifier circuit for current output or a D/A circuit for current output. The items described above also apply to other examples of the present invention.
Incidentally, dense placement means placing the first current source 631 and the second current sources 632 (the current or voltage output and current or voltage input) at least within a distance of 8 mm. More preferably, they are placed within 5 mm. It has been shown analytically that when placed at this density, the current sources can fit into a silicon chip with little difference in transistor characteristics (Vt and mobility (μ)) Similarly, the second current sources 632 and third current sources 633 (the current output and current input) are placed at least within a distance of 8 mm. More preferably, they are placed within 5 mm. Needless to say, the above items also apply to other examples of the present invention.
The current or voltage output and current or voltage input mean the following relationships. In the case of voltage-based delivery shown in
Incidentally, although it is assumed in
Similarly, although it is assumed that there is one transistor 632a, this is not restrictive. For example, it is also possible to form a plurality of small sub-transistors 632a and connect the gate terminals of the transistors 632a with the gate terminal of the transistor 631. By connecting the plurality of small transistors 632a in parallel, it is possible to reduce variations of the transistor 632a.
Thus, according to the present invention, the following configurations can be illustrated: a configuration in which one transistor 631 is connected with a plurality of transistors 632a, a configuration in which a plurality of transistors 631 are connected with one transistor 632a, and a configuration in which a plurality of transistors 631 are connected with a plurality of transistors 632a. These examples will be described in more detail below.
The above items also apply to a configuration of transistors 633a and 633b in
The above items also apply to relationship between transistors 632a and 632b in
Although description is made as a silicon chip here, this means a semiconductor chip. Thus, the chip as referred to here may be a chip formed on a gallium substrate or other semiconductor chip formed on a germanium substrate or the like. Thus, the source driver IC 14 may be constructed of any semiconductor substrate. Also, the unit transistor 634 may be a bipolar transistor, CMOS transistor, Bi-CMOS transistor, or DMOS transistor. However, in terms of reducing variations in the output of the unit transistor 634, preferably a CMOS transistor is used for the unit transistor 634.
Preferably, the unit transistor 634 is an N-channel transistor. The unit transistor consisting of a P-channel transistor has 1.5 times larger output variations than the unit transistor consisting of an N-channel transistor.
Since it is preferable that the unit transistor 634 of the source driver IC 14 is an N-channel transistor, the programming current of the source driver IC 14 is a current drawn from the pixel 16. Thus, the driver transistor 11a of the pixel 16 is a P-channel transistor. The switching transistor 11d in
Thus, the configuration in which the unit transistor 634 in the output stage of the source driver IC (circuit) 14 is an N-channel transistor and the driver transistor 11a of the pixel 16 is a P-channel transistor is characteristic of the present invention. Incidentally, if all the transistors 11 composing the pixel 16 are illustrated in
If P-channel transistors are used as the transistors 11 of pixels 16, programming current flows in the direction from the pixels 16 to the source signal lines 18. Thus, N-channel transistors should be used for the unit transistors 634 (see
Thus, if the driver transistors 11a of the pixels 16 (in the case of
Thus, P-channel transistors are used as the transistors 11 of pixels 16 and for the gate driver circuits 12. This makes it possible to reduce the costs of the array boards 71. However, in the source driver 14, unit transistors 634 must be N-channel transistors. Thus, the source driver circuit 14 cannot be formed directly on a board 71. Thus, the source driver circuit 14 is made of a silicon chip and the like separately and mounted on the array board 71. In short, the present invention is configured to mount the source driver IC 14 (means of outputting programming current as video signals) externally.
Incidentally, although it has been stated that the source driver circuit 14 is made of a silicon chip, this is not restrictive. For example, a large number of source driver circuits may be formed on a glass substrate simultaneously using low-temperature polysilicon technology or the like, cut off into chips, and mounted on boards 71. Incidentally, although it has been stated that a source driver circuit is mounted on a board 71, this is not restrictive. Any form may be adopted as long as the output terminals 681 of the source driver circuit 14 are connected to the source signal lines 18 of the board 71. For example, the source driver circuit 14 may be connected to the source signal lines 18 using TAB technology. By forming a source driver circuit 14 on a silicon chip and the like separately, it is possible to reduce variations in output current and achieve proper image display as well as to reduce costs.
The configuration in which P-channel transistors are used as selection transistors of pixels 16 and for gate driver circuits is not limited to organic EL or other self-luminous devices (display panels or display apparatus). For example, it is also applicable to liquid crystal display device and FEDs (field emission displays).
If the switching transistors 11b and 11c of a pixel 16 are P-channel transistors, the pixel 16 becomes selected at Vgh, and becomes deselected at Vgl. As described earlier, when the gate signal line 17a changes from Vgl (on) to Vgh (off), voltage penetrates (penetration voltage). If the driver transistor 11a of the pixel 16 is a P-channel transistor, the penetration voltage more tightly restricts the flow of current through the transistor 11a in black display mode. This makes it possible to achieve a proper black display. The problem with the current-driven system is that it is difficult to achieve a black display.
According to the present invention, because P-channel transistors are used for the gate driver circuits 12, the turn-on voltage corresponds to Vgh. Thus, the gate driver circuits 12 match well with the pixels 16 constructed from P-channel transistors. Also, to improve black display, it is important that the programming current Iw flows from the anode voltage Vdd to the unit transistors 634 of the source driver circuit 14 via the driver transistors 11a and source signal lines 18, as is the case with the pixel 16 configuration shown in
The same applies to
According to the present invention, the driver transistors 11a of the pixels 16 are P-channel transistors and the switching transistors 11b and 11c are P-channel transistors. Also, the unit transistors 634 in the output stages of the source driver IC 14 are N-channel transistors. Besides, preferably P-channel transistors are used for the gate driver circuits 12.
Needless to say, a configuration in which P-channel and N-channel transistors are interchanged also works well. Specifically, the driver transistors 11a of the pixels 16 are N-channel transistors and the switching transistors 11b and 11c are N-channel transistors. Also, the unit transistors 634 in the output stages of the source driver IC 14 are P-channel transistors. Besides, preferably N-channel transistors are used for the gate driver circuits 12. This configuration also belongs to the present invention.
The above items apply not only to an IC which contain a single unit transistor 634, but also to a source driver IC 14 with another configuration such as a source driver circuit whose current output stage contains a plurality of transistors or current mirrors.
Besides, they also apply to source driver circuits 14 by using semiconductor films of low-temperature polysilicon, high-temperature polysilicon, CGS formed by solid-phase growth, or amorphous silicon. In that case, however, panels are often relatively large. On a large panel, it is hard to visually perceive the effect of some variations in the output from the source signal lines 18.
Thus, in the case of a display panel in which a source driver circuit 14 is formed on the glass substrate or the like together with pixel transistors, dense placement means placing the first current source 631 and second current sources 632 (the input and output of current) at least within 30 mm (inclusive) of each other. More preferably, they are within 20 mm (inclusive) of each other. It has been shown analytically that there is little difference in characteristics (Vt and mobility (μ)) of transistors placed in this range. Similarly, the second current sources 632 and third current sources 633 (the input and output of current) are placed at least within 30 mm (inclusive) of each other. More preferably, they are within 20 mm (inclusive) of each other.
It has been stated for ease of understanding and explanation that signals are transferred between current mirror circuits by way of voltage. However, by using current-based delivery. It is possible to reduce variations in the driver circuit (IC) 14 of a current-driven display panel.
In
In
In
Incidentally, although this example of the present invention focuses on relationship between the first current source and second current source for ease of explanation or understanding, this is not restrictive and it goes without saying that this example also applies (can be applied) to relationship between the second current source and third current source as well as relationship between other current sources.
In the layout configuration of the current mirror circuit of the voltage-based delivery type shown in
In contrast, in the layout configuration of the current mirror circuit of the current-based delivery type shown in
In view of the above circumstances, it is preferable to use a layout configuration of the current-based delivery type instead of the voltage-based delivery type for the circuit configuration of the multi-stage current mirror circuit according to the present invention (the source driver IC (circuit) 14 of the current-based delivery type according to the present invention) in terms of reduced variations. Needless to say the above example can be applied to other examples of the present invention.
Incidentally, although delivery from the first-stage current source to the second-stage current source has been cited for the sake of explanation, the same applies to delivery from the second-stage current source to the third-stage current source, delivery from the third-stage current source to the fourth-stage current source, and so on.
In
The gate voltage of the first-stage current source constituted of the transistor 631 is applied to the gate of the N-channel transistor 632a of the adjacent second-stage current source, and the current consequently flowing through the transistor is delivered to the P-channel transistor 632b of the second-stage current source. Also, the gate voltage of the P-channel transistor 632b of the second-stage current source is applied to the gate of the N-channel transistor 633a of the adjacent third-stage current source, and the current consequently flowing through the transistor is delivered to the N-channel transistor 633b of the third-stage current source. A large number of current sources 634 are formed (placed) at the gate of the N-channel transistor 633b of the third-stage current source according to the required bit count as illustrated in
The configuration in
Variations in the Vt of transistors (variations in characteristics) are on the order of 100 mV within a wafer. However, variations in Vt of transistors formed within 100 μ of each other should be 10 mV or less (actual measurement) That is, by configuring a current mirror circuit with transistors formed close to each other, it is possible to reduce variations in the output current of the current mirror circuit. This reduces variations in the output current among terminals of the source driver IC.
Incidentally, although variations in Vt are described as variations among transistors, variations among transistors are not limited to variations in Vt. However, since variations in Vt are a main cause of variations among transistors, it is assumed that the variations in Vt=the variations among transistors, for ease of understanding.
However, the absolute value of output current varies from wafer to wafer. However, this problem can be dealt with by adjusting the reference voltage or setting it to a fixed value in the source driver circuit (IC) 14 of the present invention. Also, it can be dealt with (solved) by modifying the current mirror circuit ingeniously.
The present invention varies (controls) the amount of current flowing through the source signal line 18 by switching the number of currents flowing through the unit transistors 634 using input digital data (D). When the number of gradations is 64 or more, since 1/64=0.015, theoretically variations in output current should be within 1 to 2%. Incidentally, output variations within 1% are difficult to distinguish visually and output variations of 0.5% or below are impossible to distinguish (look uniform).
To keep output current variations (%) within 1%, the formation area of a transistor group (the transistors among which variations should be suppressed) should be kept within 2 square millimeters as indicated by the results shown in
Incidentally, the above applies to 8-bit (256 gradations) or larger data. For a smaller number of gradations, for example, in the case of 6-bit data (64 gradations), variations in output current may be somewhere around 2% (virtually no problem in terms of image display). In this case, the formation area of a transistor group 681 can be kept within 5 square millimeters. There is no need for the two transistor groups 681 (transistor groups 681a and 681b are shown in
In the source driver circuit (IC) 14 of the present invention, at least a plurality of current sources, such as consisting of parent, child, and grandchild current sources, are connected in multiple stages (of course there may be two stages consisting of parent and child current sources) and placed densely, as shown in
According to the present invention, one transistor group 681a is constructed, placed, formed, or built at the approximate center of the IC chip 14 and eight transistor groups 681b each are formed on the left and right of the chip (N=8+8, see
Voltage-based delivery (voltage connection) is made between the parent current source 631 and child current sources 632a. Consequently, tends to be affected by variations in the Vt of the transistors. Thus, the transistors in the transistor group 681a are placed densely. The formation area of the transistor group 681a is kept within 2 square millimeters as shown in
Data is delivered between the transistor group 681a and child transistors 632b via current, and thus the current may flow some distance. Regarding the distance (e.g., between the output terminals of the higher-level transistor group 681a and input terminals of the lower-level transistor group 681b), the transistors 632a composing the second current sources (child) and the transistors 632b composing the second current sources (child) should be placed at least within 10 mm of each other as described above. Preferably, the transistors should be placed or formed within 8 mm. More preferably, they should be placed within 5 mm.
It has been shown analytically that differences in characteristics (Vt and mobility (μ)) of transistors placed in a silicon chip do not have much impact in the case of current-based delivery if the distance is within this range. Preferably, the above conditions are satisfied especially by lower-level transistor groups. For example, if the transistor group 681a is at the top level with the transistor groups 681b lying below it and transistor groups 681c lying further below them, the current-based delivery between the transistor groups 681b and transistor groups 681c should satisfy the above conditions. Thus, according to the present invention it is not always necessary that all the transistor groups 681 satisfy the above conditions. It is sufficient that at least a pair of transistor groups 681 satisfy the above conditions. This is because the lower the level, the more transistor groups 681 there are.
This similarly applies to the transistors 633a constituting the third (grandchild) current sources and transistors 633b constituting the third current sources. Needless to say, almost the same applies to voltage-based delivery. The transistor groups 681b are formed, built, or placed in the left-to-right direction of the chip (in the longitudinal direction, i.e., at locations facing the output terminal 761). The transistor groups 681b are formed, built, or placed in the left-to-right direction of the chip (in the longitudinal direction, i.e., at locations facing the output terminal 761). According to the present invention, the number M of the transistor groups 681b is 11 (see
Voltage-based delivery (voltage connection) is made between the child current sources 632b and grandchild current sources 633a. Thus, the transistors in the transistor groups 681b are placed densely as is the case with the transistor group 681a. The formation area of the transistor group 681b should be within 2 square millimeters as shown in
Data is delivered between the grandchild transistors 633a and transistors 633b (current-based delivery), and thus the current may flow some distance in the transistor group 681b. The description of distances provided earlier applies here as well. The transistors 633a constituting the third (grandchild) current sources and transistors 633b constituting the second (grandchild) current sources should be placed within at least 8 mm of each other. More preferably, they should be placed within 5 mm.
Incidentally, in the source driver IC (circuit) 14, transistors may be referred to as current sources. This is because transistors function as current sources in current mirror circuits and the like composed of transistors.
Electronic regulators circuits are formed (or placed) according to the number of colors used by the EL display panel. For example, if the three primary colors RGB are used, preferably three electronic regulators are formed (or placed) corresponding to the colors so that the colors can be adjusted independently. However, if one color is used as a reference (is fixed), as many electronic regulators circuits as the number of colors minus 1 should be formed (or placed).
However, it is not always necessary to place them in the output current circuit 704 at the center They may be placed at an end or both ends of the IC chip. Also, they may be formed or placed in parallel with the output current circuit 704.
It is not desirable to form a controller or output current circuit 704 in the center of the IC chip 14 because they are liable to be affected by Vt distribution of the unit transistors 634 in the IC chip 14 (the Vt of an wafer is distributed evenly in the wafer).
Reasons for this will be described with reference to
However, there is a possibility that the unit transistors of the output circuits connected to the output terminals 761b and 761c differ in Vt. Even if the unit transistors 634 of the output terminals have equal gate terminal voltage, their output current will vary depending on the Vt distribution of the unit transistors 634. Consequently, there may be steps of output currents in the center of the panel. The steps of output currents can cause brightness difference between the right and left sides in the center of the screen.
A configuration used to solve this problem is shown in
In the circuit configuration in
However, if transistors are connected in a one-to-one relationship with other transistors, any variation in the characteristics (Vt, etc.) of characteristics of a transistor will result in variations in the output of the corresponding transistor connected to it.
To solve this problem, an example with an appropriate configuration is shown in
Preferably, the plurality of transistors 633a and plurality of transistors 633b are approximately equal in size and equal in number. Preferably, the unit transistors 634 (63 in number in the case of 64 gradations as in
Preferably, the current flowing through the transistors 633b is equal to or more than five times a current Ic1 passed through the transistors 632b. This will stabilize the gate potential of the transistors 633a and suppress transient phenomena caused by output current.
Although it has been stated that the transmission transistor group 681b1 and transmission transistor group 681b2 are placed adjacent to each other and that each of them consists of four transistors 633a placed next to one another, this is not restrictive. For example, the transistors 633a of the transmission transistor group 681b1 and the transistors 633a of the transmission transistor group 681b2 may be placed or formed alternately. This will reduce variations in the output current (programming current) of each terminal.
The use of multiple transistors for current-based delivery makes it possible to reduce variations in output current of the transistor group as a whole and further reduce variations in the output current (programming current) of each terminal.
The total formation area of the transistors 633 composing a transmission transistor group 681 is an important item. Basically, the larger the total formation area of the transistors 633, the smaller the variations in output current (programming current flowing in from the source signal line 18). That is, the larger the formation area of the transmission transistor group 681 (the total formation area of the transistors 633), the smaller the variations. However, a larger formation area of the transistors 633 increases a chip area, increasing the price of the IC chip 14.
Incidentally, the formation area of a transmission transistor group 681 is the sum total of the formation areas of the transistors 633 composing the transmission transistor group 681. The area of a transistor 633 is the product of the channel length L and channel width W of the transistor 633. Thus, if a transistor group 681 consists of ten transistors 633 whose channel length L is 10 μm and channel width W is 5 μm, the formation area Tm (square μm) of the transmission transistor group 681 is 10 μm×5 μm×10=500 (square μm).
The formation area of the transmission transistor group 681 should be determined in such a way as to maintain a certain relationship with the unit transistors 634. Also, the transmission transistor group 681a and transmission transistor group 681b should maintain a certain relationship.
Now, description will be given of the relationship between the formation area of the transistor group 681 and the unit transistors 634. As also illustrated in
The transistor 633b in
1/4≦Tm/Ts≦6
More preferably, the formation area Ts of the unit transistor group and formation area Tm of the transmission transistor group 681c have the following relationship:
1/2≦Tm/Ts≦4
By satisfying the above relationship, it is possible to reduce variations in the output current (programming current) of each terminal.
Also, the formation area Tmm of the transmission transistor group 681b and formation area Tms of the transmission transistor group 681c have the following relationship:
1/2≦Tmm/Tms≦8
More preferably, the formation area Ts of the unit transistor group and formation area Tm of the transmission transistor group 681c have the following relationship:
1≦Tm/Ts≦4
By satisfying the above relationship, it is possible to reduce variations in the output current (programming current) of each terminal.
Suppose output current from the transistor group 681b1 is Ic1, output current from the transistor group 681b2 is Ic2, and output current from the transistor group 681b2 is Ic3. Then, the output currents Ic1, Ic2, and Ic3 must coincide. According to the present invention, since each transistor group 681 consists of multiple transistors 633, even if individual transistors 633 have variations, there is no variation in the output current Ic of the transistor group 681 as a whole.
Incidentally, the above example is not limited to three-stage current mirror connections (multi-stage current mirror connections) shown in
In
With the configuration of the driver 14 according to the present invention, the 1st bit outputs a twice larger programming current to the 0th bit, the 2nd bit outputs a twice larger programming current to the 1st bit, the 3rd bit outputs a twice larger programming current to the 2nd bit, the 4th bit outputs a twice larger programming current to the 3rd bit, the 5th bit outputs a twice larger programming current to the 4th bit. To put it in other words, each bit must be able to output twice as large programming current as the next lower-order bit.
However, in practice because of variations in the unit transistors 634 constituting different bits, it is difficult (if not impossible) to configure such that each terminal will output exactly twice larger programming current. An example which can solve this problem is shown in
The configuration in
In the example shown in
Incidentally, the adjustment transistors 1241 and unit transistors 634 are configured or connected so as to share gate terminals, to which the same gate voltage is applied. Thus, when a current Ib flows through the transistors 633, the gate voltage of the unit transistors 634 is established, prescribing the current to be output from the unit transistors 634. At the same time, output current of the adjustment transistors 1241 is also defined. That is, the output current of the adjustment transistors 1241 is proportional to the output current of the unit transistors 634. The output current can be controlled by means of the current Ib to be passed to the transistors 633 which pair up with the unit transistors 634.
According to the present invention, the size of one unit transistor 634 is made larger than the total size of two or more adjustment transistors. That is, the size of the unit transistor 634 is larger than the size of the adjustment transistor 1241. Alternatively, the total size of two or more adjustment transistors 1241 is made larger than the size of the unit transistor 634. By controlling the number of working adjustment transistors 1241, it is possible to adjust variations in output current for each bit in small increments.
According to another example of the present invention, the output current of one unit transistor 634 is made larger than the output current of two or more adjustment transistors. That is, the output current of the unit transistor 634 is larger than the output current of the adjustment transistor 1241. By controlling the number of working adjustment transistors 1241, it is possible to adjust variations in output current for each bit in small increments.
In the above condition, adjustment transistors 1241 are cut off from the common terminal 1252 to obtain the target output current Ia. Laser cutting is used to cut off the adjustment transistors 1241. It is appropriate to use a YAG laser for the laser cutting. Besides, neon helium lasers and carbon dioxide lasers are also available. Also, machining such as sand blasting is available as well.
In
Incidentally, although it has been stated with reference to
Also, it is not strictly necessary to perform cutting at the cutting sites 1251, and it is alternatively possible to open the cutting sites in advance and make connections by depositing a metal film or the like on the cutting sites.
Besides, although it has been stated that the adjustment transistors 1241 are formed in advance, this is not restrictive. For example, it is also possible to trim part of the unit transistors 634, and thereby adjust the output current of the unit transistors 634 so as to obtain the target output current for each bit. Alternatively, it is possible to obtain the target output currents for different bits by separately adjusting the gate terminal voltages of the unit transistors 634 which correspond to the respective bits. For example, this can be accomplished by trimming the wiring connected to the gate terminals of the unit transistors 634 and thereby increasing resistance.
Incidentally, although unit transistors 634 or adjustment transistors 1241 are trimmed to adjust output current in the above example, the present invention is not limited to this. For example, it is possible to form adjustment transistors 1241 in isolation, connect their source terminals or the like to output current circuits 704 by a FIB process, and thereby adjust output current. However, there is no need to isolate the adjustment transistors 1241 completely. For example, it is possible to form output current circuits 704 and adjustment transistors 1241 with their gate terminals and source terminals connected and connect the drain terminals of the adjustment transistors 1241 by a FIB process.
Also, it is possible to construct the gate terminals of adjustment transistors 1241 in isolation from the gate terminals of unit transistors 634, which form the output current circuits 704, and form or place the unit transistors 634 and the adjustment transistors 1241 with their drain terminals and source terminals connected. The potential at the gate terminals of the unit transistors 634 is determined by current Ic as illustrated in
Although it has been stated that the output current of the adjustment transistors 1241 is adjusted through adjustment of the potential at the gate terminals, this is not restrictive. The output current may be adjusted through adjustment of the voltage applied to the source terminals or drain terminals of the adjustment transistors 1241. These terminal voltages may also be adjusted using an electronic regulator. Also the voltages applied to the terminals of the adjustment transistors 1241 are not limited to direct-current voltages. It is also possible to apply rectangular voltages (pulsed voltages or the like) and control output voltages by duration control.
To change the magnitude of output current greatly, the adjustment transistors 1241 may be cut off at a cutoff point 1661a as illustrated in
In particular, preferably the output current circuits 704 on both ends of the IC chip 14 are equipped with a trimming function. In the case of a large display panel, a plurality of source driver ICs 14 must be cascaded. This is because cascade connection makes any difference between output currents of adjacent ICs conspicuous as a boundary. By trimming transistors and the like as illustrated in
Needless to say, the above is also applicable to other examples of the present invention.
The configuration in
Thus, in this configuration, a plurality of transistors (current generating means) are formed, placed, or constructed to generate reference currents which prescribe output currents of the unit transistors 634. More preferably, output currents from the plurality of transistors are connected to current-receiving circuits such as transistors which compose current mirror circuits and the output currents of the unit transistors 634 are controlled by gate voltages generated by the plurality of transistors.
Further, an embodiment according to
As can be seen from
A reference current Ia1 flows through the transistor 632a1 and a reference current Ia2 flows through the transistor 632a2. Thus, the gate terminal voltage of the transistors 633a (633a1, 633a2, 633a3, 633a4, . . . ) a redefined by the transistors 632a1 and 632a2, and define the current outputted from the transistors 633a.
The magnitudes of the reference currents Ia1 and Ia2 are made to coincide. This can be accomplished by constant-current circuits such as the current mirror circuit which output the reference currents Ia1 and Ia2.
Even if the reference currents Ia1 and Ia2 deviate more or less from each other, this poses little problem because they correct each other.
Although it has been stated in the above example that the reference currents Ia1 and Ia2 are made to roughly coincide, the present invention is not limited to this. For example, the reference currents Ia1 and Ia2 may be different from each other. For example, if the current Ia1 is smaller than the current Ia2, a current Ib1 outputted by a transistor 633a1 can be made smaller than a current Ibn outputted by a transistor 633an (Ib1<Ibn). The smaller the current Ib1, the smaller the current outputted by a transistor group 681c1. The larger the current Ibn, the larger the current outputted by a transistor group 681cn. The transistor groups 681 placed or formed between the transistor group 681c1 and transistor group 681cn produce output currents of intermediate magnitudes.
Thus, by making the current Ia1 and current Ia2 different from each other, it is possible to produce a slope in the output currents of the transistor groups 681. The sloping of the output currents of the transistor groups 681 is effective for cascade connection of the sourced river ICs 14. This is because adjustments of the two reference currents Ia1 and Ia2 for IC chips make it possible to adjust the output currents of the output current circuits 704. Thus, it is possible to make adjustments so as to eliminate differences between output currents of adjacent ICs chip 14.
Even if the current Ia1 and current Ia2 are made different from each other, if the potentials at the gate terminals of the unit transistors 634 in the transistor groups 681 are equal, it is not possible to produce a slope in the output currents of the transistor groups 681. The reason why a slope is produced in the output currents of the transistor groups 681 is that the gate terminal voltage differs among the unit transistors 634. To vary the gate terminal voltage, it is necessary to increase the resistance of gate wiring 1261 in the transistor group 681b. Specifically, the gate wiring 1261 is formed of polysilicon. Also, the resistance value of the gate wiring between the transistors 632a1 and 632an should be between 2 KΩ and 2 MΩ (both inclusive). In this way, by increasing the resistance of the gate wiring 1261, it is possible to produce a slope in the output currents of the transistor groups 681c.
Preferably, the gate terminal voltage of the transistor 633a is set at 0.52 to 0.68 V (both inclusive) is a silicon IC chip is used. This range can reduce variations in the output current of the transistor 633a. The above items similarly apply to other examples of the present invention.
Needless to say, the above items also apply to other examples of the present invention.
In the configuration shown in
In
The transistor groups 681c constitute output-stage circuits connected to respective source signal lines 18. Thus, by supplying current to the transistor groups 681c from both sides and eliminating voltage drops or potential distribution of the gate terminals of the unit transistors 634, it is possible to do away with variations in output currents from the source signal lines 18.
Each transistor group 681c contains a plurality of unit transistors 634 which output current. On both sides of the transistor group 681c, there are transistors 633b (633b1 and 633b2) which share the gate terminals of the transistors 634 and form current mirror circuits in conjunction with the transistors 634. The reference current Ib1 flows through the transistor 633b1 and the reference current Ib2 flows through the transistor 633b2. Thus, the gate terminal voltage of the unit transistors 634 are defined by the transistors 633b1 and 633b2, and define the current outputted from the unit transistors 634.
The magnitudes of the reference currents Ib1 and Ib2 are made to coincide. This can be accomplished by constant-current circuits such as the transistors 633a which output the reference currents Ib1 and Ib2. Even if the reference currents Ib1 and Ib2 deviate more or less from each other, this poses little problem because they correct each other.
Needless to say, the above items are also applicable to the transistor groups 681c.
In the example shown in
In
With the configuration shown in
As shown in
Of course, the transistors 633a and transistors 633b need not be connected regularly, and may be connected randomly. Besides, the transistors 633a may be connected with the transistors 633b by skipping two or more instead of skipping one as shown in
In the above example, current mirror circuits are connected in multiple stages as illustrated in
With the configuration shown in
However, there are often subtle differences between the gate terminal voltage of the unit transistors 634 in the transistor group 681c1 and the gate terminal voltage of the unit transistors 634 in the transistor group. This is presumed to be due to voltage drops and the like caused by current flowing through the gate wiring and the like. Even a subtle change in voltage will result in a few percent change in output current (programming current). According to the present invention, difference among gradations is 1.5% (=100/64) in the case of 64 gradations. Thus, changes in output current should be reduced to at least on the order of 1% or less.
A configuration used to solve this problem is shown in
However, if the reference current Ib1 and reference current Ib2 are configured to be separately adjustable, it is possible to adjust output current (programming current) to be uniform when voltage at point a and voltage at point b on a common terminal 1253 differ from each other and the unit transistors 634 in the transistor group 681c1 and unit transistors 634 in the transistor group 681c2 differ in output current. Also, since unit transistors on left and right sides of the IC chip 14 differ in Vt, it is possible to eliminate a slope in output current and correct any slope which is produced.
Although two reference current generator circuits are formed separately in
The use of the configuration in
In this way, the configuration in
The reference current generator circuit 1 delivers the reference current Ib1 and the reference current generator circuit 2 delivers the reference current Ib2.
A reference current generator circuit 3 delivers reference current Ib3. The reference current Ib1, reference current Ib2, and reference current Ib3 have the same current value. The reference currents are controlled or adjusted by a reference current regulating means 651 (which, needless to say, is not limited to a variable regulator, and may be an electronic regulator).
If the reference current Ib1, reference current Ib2, and reference current Ib3 are configured to be separately adjustable, it is possible to adjust the gate terminal voltage of the transistor 633b1, transistor 633b2, and transistor 633b3. It is possible to adjust the voltage at point a, voltage at point b, and voltage at point c on a common terminal 1253. Thus, it is possible to correct (variations in) output current (programming current) by varying the Vt of the unit transistors 634 in the transistor group 681c1, the Vt of the unit transistors 634 in the transistor group 681c2, and the Vt of the unit transistors 634 in the transistor group 681cn.
Although three reference current generator circuits are formed separately in
The reference currents Ib1 and Ib2 are controlled or adjusted by a reference current regulating means 651 (which, needless to say, is not limited to a variable regulator, and may be an electronic regulator). The unit transistors 634 in each transistor group 681c form current mirror circuits in conjunction with the transistors 633b (633b1 and 633b2). The reference currents Ib1 and Ib2 define the magnitude of output current from the unit transistors 634.
With the configuration shown in
Thus, the transistor 633b1 and transistor 633b2 share a gate terminal and the voltages at point a and point b are equal. Consequently, voltage is supplied from both sides of the common terminal 1253, making the voltage at the common terminal 1253 uniform on left and right sides of the IC chip. Once the voltage at the common terminal 1253 is uniform, voltages at the gate terminals of all the unit transistors 634 in the transistor groups 681c become equal. This eliminates variations in the programming current outputted from the unit transistors 634 to the source signal lines 18.
In this way, the configuration in
The reference current generator circuit 1 delivers the reference current Ib1 and the reference current generator circuit 2 delivers the reference current Ib2. A reference current generator circuit 3 delivers reference current Ib3. The reference current Ib1, reference current Ib2, and reference current Ib3 have the same current value. The reference currents are controlled or adjusted by a reference current regulating means 651 (which, needless to say, is not limited to a variable regulator, and may be an electronic regulator).
Although three reference current generator circuits are formed separately in
Incidentally, in the configurations in
In the above examples, current-based or voltage-based delivery is carried out mainly in a single-stage configuration. However, the present invention is not limited to this. Needless to say, as shown in
In
By adjusting the reference currents Ia1 and Ia2 by the reference current regulating means 651, it is possible to adjust output current Ib of the transistors 632 in the transistor group 681a. The current Ib is delivered to a transistor 632b, causing a current to flow through the transistors 633a in the transistor groups 681b which form current mirror circuits and thereby determining the output current of the unit transistors 634. Other items are the same as in
Although it has been stated that the magnitudes of the reference currents which flow through the transistors placed on both sides of the chip are adjusted by electronic regulators or the like, the present invention is not limited to this. For example, this can be accomplished by trimming reference current adjustment resistors Rm as illustrated in
Preferably, the currents generated by the transistors composing current mirror circuits are delivered by a plurality of transistors. Transistors formed in an IC chip 14 have variations in characteristics. To suppress variations in transistor characteristics, the size of the transistors can be increased. However, if transistor size is increased, the current mirror ratios of the current mirror circuits may deviate. To solve this problem, it is advisable to make current- or voltage-based delivery using a plurality of transistors. The use of multiple transistors decreases overall variations even if there are variations in the characteristics of individual transistors. This also improves the accuracy of current mirror ratios. All in all, the area of the IC chip is reduced as well.
In
The transistor group 681b1, transistor group 681b2, transistor group 681b3, transistor group 681b4, and so on are composed of the same number of transistors 633a. Also, the total area of the transistors 633a is (approximately) equal among the transistor groups 681b (where the total area is the W and L sizes of the transistors 633a in each transistor group 681b multiplied by the number of the transistors 633a). The same applies to the transistor groups 681c.
Let Sc denote the total area of the transistors 633b in each transistor group 681c (where the total area is the W and L sizes of the transistors 633b in each transistor group 681c multiplied by the number of the transistors 633b). Also, let Sb dente the total area of the transistors 633a in each transistor group 681b (where the total area is the W and L sizes of the transistors 633a in each transistor group 681b multiplied by the number of the transistors 633a). Also, let Sa dente the total area of the transistors 632b in each transistor group 681a (where the total area is the W and L sizes of the transistors 632b in the transistor group 681a multiplied by the number of the transistors 632b). Also, let Sd dente the total area of the unit transistors 634 per output.
Preferably, the total area Sc and the total area Sb are approximately equal. Also, it is preferably that the transistors 633a composing each transistor group 681b and the transistors 633b composing each transistor group 681c are equal in number. However, considering layout constraints on the IC chip 14, the transistors 633a composing each transistor group 681b may be made smaller in number and larger in size than the transistors 433b composing each transistor group 681c. An example of the above configuration is shown in
The relationship between the total area Sd and total area Sc is correlated with output variations. This correlation is shown in
Incidentally, A≧B means that A is equal to or larger than B. A>B means that A is larger than B. A≦B means that A is equal to or smaller than B. A<B means that A is smaller than B.
Besides, preferably the total area Sd and total area Sc are approximately equal. Furthermore, preferably the number of the unit transistors 634 per output and the number of the transistors 633b in each transistor group 681c are equal. That is, in the case of 64 gradations, there are 63 unit transistors 634 per output. Thus, there are 63 transistors 633b in the transistor group 681c.
Also, preferably the transistor group 681a, transistor groups 681b, and the transistor groups 681c are composed of unit transistors 634 whose WL area is within a factor of four. More preferably, they are composed of unit transistors 484 whose WL area is within a factor of two. Even more preferably, they are composed of unit transistors 484 of the same size. That is, current mirror circuits and the output current circuit 704 are composed of transistors of approximately the same size.
The total area Sa should be larger than the total area Sb. Preferably, a relationship 200 Sb≧Sa≧4 Sb is satisfied. Also, the total area Sa of the transistors 663a composing all the transistor groups 681b should be approximately equal to Sa.
Incidentally, as illustrated in
In the configuration in
In the configuration shown in
To further improve the stability, it is preferable to form or place a capacitor 1601 on the gate wiring 1261 as illustrated in
The above example is configured to pass a reference current, copy the reference current using a current mirror circuit, and transmit the reference current to the unit transistor 634 in the final stage. When the image display is black display (complete black raster), current does not flow through any unit transistor 634 because every switch 641 is open. Thus, 0 (A) current flows through the source signal line 18, consuming no power.
However, even during black raster display, reference currents flow. Examples include the current Ib and Ic in
To prevent reference current from flowing, a sleep switch 1611 can be opened as shown in
When the sleep switch 1611 is turned off, the reference current Ib stops flowing. Consequently, current does not flow through the transistors 633a in a transistor group 681a1, and the reference current Ic is also reduced to 0 A. Thus, current does not flow through the transistors 633b in a transistor group 681c either. This improves power efficiency.
During a blanking period A when the sleep switch 1611 is off, reference current does not flow. During a period D when the sleep switch 1611 is on, the reference current flows.
Incidentally, on/off control of the sleep switch 1611 may be performed according to image data. For example, when all image data in a pixel row is black image data (for a period of 1 H, the programming currents outputted to all source signal lines 18 are 0), the sleep switch 1611 is turned off to stop reference currents (Ic, Ib, etc.) from flowing. Also, asleep switch may be formed or placed for each source signal line and be subjected to on/off control. For example, when an odd-numbered source signal line 18 is in black display mode (vertical black stripe display), the corresponding sleep switch is turned off.
With the configuration shown in
The parasitic capacitance between the gate wiring 1261 and internal wiring 643 (the source signal line 18) in conjunction with the Vsd in the unit transistors 634 causes potential fluctuations in the gate wiring 1261. The potential fluctuations cause changes to the output current of the unit transistors 634. The changes in the output current produce horizontal streaks and the like in images. The horizontal streaks appear where the images change from white display to black display or from black display to white display.
The resistors in the switches 641 are designed to satisfy the following relations.
R1<R2<R3<R4<R5<R6
D0 is provided by 1 unit transistor 634. D1 is provided by 2 unit transistors 634. D2 is provided by 4 unit transistors 634. D3 is provided by 8 unit transistors 634. D4 is provided by 16 unit transistors 634. D5 is provided by 32 unit transistors 634. Thus, the current flowing through the switches 641 increases with changes from D0 to D5. It is also necessary to lower the on-resistance of the switches accordingly. On the other hand, it is also necessary to reduce linking as illustrated in
The linking of the gate wiring 1261 in
On the other hand, in order for a driver transistor 11a switch from white-display current to black-display current, it is necessary to make a certain amplitude change to the potential of the source signal line 18. The required range of amplitude change is 2.5 V or more. It is lower than the power supply voltage because the output voltage of the source signal line 18 cannot exceed the power supply voltage.
Thus, the power supply voltage of the source driver IC 14 should be from 2.5 V to 12 V (both inclusive). The use of this range makes it possible to keep fluctuations in the gate wiring 1261 within a stipulated range, eliminate horizontal cross-talk, and thus achieve proper image display.
Wiring resistance of the gate wiring 1261 also presents a problem. In
Another method of solving this problem is shown in
The steady-state transistors 1531 pass current Is constantly while the reference current Ib is flowing. Thus, they do not depend on the magnitudes of the programming current Iw. The flow of the current Is reduces potential fluctuations of the gate wiring 1261. Preferably, the current Is is from 2 to 8 times (both inclusive) as large as the current flowing through the unit transistors 634. The steady-state transistors 1531 are constructed of multiple transistors with the same WL as the unit transistors 634. Also, preferably the steady-state transistors 1531 are formed at a location farthest from the transistor 633 which passes the reference current Ib.
Although it has been stated with reference to
In
Dummy transistor groups 681c are formed or placed on outer sides of the transistor groups 681c1 and 681cn located on both ends of the chip IC. Preferably, at least two dummy transistor groups 681c are formed on the left and right (outermost sides) of the chip IC. More preferably, three to six circuits (both inclusive) are formed. Without dummy transistor groups 681c, a diffusion process or etching process during production of the IC will cause the unit transistors 634 in outer transistor groups 681c to differ in Vt from those in the center of the IC chip 14. Difference in the Vt will cause variations in the output current (programming current) of the unit transistors 634.
FIGS. 129 to 133 are block diagrams of a driver IC with a single-stage current mirror configuration. The single-stage configuration will be described further.
The transistor 632b and two transistors 633a compose a current mirror circuit. The transistor 633a1 and transistor 633a2 are of the same size. Thus, current Ic passed by the transistor 633a1 and current Ic passed by the transistor 633a2 are identical.
In
As is the case with
Although it has been stated that the transistor 632b current is specified by the resistance R1, this is not restrictive. Electronic regulators 1503a and 1503b may be used as shown in
The sleep switch 1611 has been described with reference to
Also, it has been stated with reference to
Also, it has been stated with reference to
It has been stated with reference to
Also, let Sc denote the total area of the unit transistors 634 in each transistor group 681c (where the total area is the W and L sizes of the transistors 634 in each transistor group 681c multiplied by the number of the transistors 634). It is assumed that the number of the transistor groups 681c is n. In the case of a QCIF+ panel, n is 176 (a reference current circuit is formed for each of R, G, and B).
In
A small value of Sc×n/Sb means that the total area of the unit transistors 634 in the transistor groups 681c is smaller than the total area of the transistors 633b in the transistor groups 681b when the number n of output terminals is constant. In that case, the fluctuation ratio is small.
An allowable range of fluctuations corresponds to a value of Sc×n/Sb of 50 or less. When Sc×n/Sb is 50 or less, the fluctuation ratio falls within the allowable range and potential fluctuations of the gate wiring 1261 is extremely small. This makes it possible to eliminate horizontal cross-talk, keep output variations within an allowable range, and thus achieve proper image display. It is true that the fluctuation ratio falls within the allowable range when Sc×n/Sb is 50 or less. However, decreasing Sc×n/Sb to 5 or less has almost no effect. On the contrary, Sb becomes large, increasing the chip area of the IC 14. Thus, preferably Sc×n/Sb to 5 should be from 5 to 50 (both inclusive).
Also, placement of unit transistors 634 in the transistor groups 681c has consideration.
The transistor groups 681c should be placed orderly. Any dropout of a unit transistor 634 will make the characteristics of the unit transistors 634 around it different from the characteristics of the other unit transistors 634.
To solve this problem, the present invention forms or places a dummy transistor 1341 in the shaded area. This makes the characteristics of the unit transistors 634a, 634b, and 634c coincide with the characteristics of the other unit transistors 634. That is, by forming the dummy transistors 1341, the present invention arranges the unit transistors 634 in a matrix. Also, the unit transistors 634 are arranged in a matrix without any omission. Also, the unit transistors 634 are arranged axisymmetrically.
Although it has been stated that 63 unit transistors 634 are arranged in each transistor group 681c to represent 64 gradations, the present invention is not limited to this. The unit transistor 634 may be further composed of a plurality of sub-transistors.
In
Changes in the formation direction of the unit transistors 634 or sub-transistors 1352 often change their characteristics. For example, in
Thus, as illustrated in
The above examples involve constructing or forming unit transistors of the same size or same current output in the transistor groups 681c (see
An n-unit (n is an integer) unit transistor can be formed easily by changing the channel width W proportionally (while keeping the channel length L constant). Actually, however, doubling the channel width W often does not double the output current. Thus, the channel width W is determined experimentally by actually building transistors. According to the present invention, however, even if the channel width W deviates more or less from proportionality, it is assumed that the channel width W is proportional.
Reference current circuits will be described below. Output current circuits 704 are formed (placed) individually for R, G, and B. The RGB output current circuits 704R, 704G, and 704B are placed in close vicinity. Also, a reference current INL in a low-current region in
Thus, an output current circuit 704R for R is equipped with a regulator (or an electronic regulator for voltage output or current output) 651RL to adjust the reference current INL in the low-current region and a regulator (or an electronic regulator for voltage output or current output) 651RH to adjust the reference current INH in the high-current region. Similarly, an output current circuit 704G for G is equipped with a regulator (or an electronic regulator for voltage output or current output) 651GL to adjust the reference current INL in the low-current region and a regulator (or an electronic regulator for voltage output or current output) 651GH to adjust the reference current INH in the high-current region. Also, an output current circuit 704B for B is equipped with a regulator (or an electronic regulator for voltage output or current output) 651BL to adjust the reference current INL in the low-current region and a regulator (or an electronic regulator for voltage output or current output) 651BH to adjust the reference current INH in the high-current region.
Preferably, the regulators 651 and the like should be capable of accommodating temperature changes to compensate for temperature characteristics of the EL element 15. Needless to say, if there are two or more breakpoints in gamma characteristics shown in
Output pads 761 are formed or placed on the output terminals of the IC chip. They are connected with the source signal lines 18 of the display panel. A bump is formed on the output pads 761 by a plating technique or ball bonding technique. The bump should be 10 to 40 μm high (both inclusive).
The bumps and the source signal lines 18 are connected electrically via a conductive bonding layer (not shown). The conductive bonding layer is made of an epoxy or phenolic base resin mixed with flakes of silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO2), and the like, or made of an ultraviolet curing resin. The conductive bonding layer is formed on the bump by a transfer or other technique. Also, the bumps and the source signal lines 18 are bonded by thermocompression using an ACF resin. Incidentally, the techniques for connecting the bumps or output pads 761 with the source signal lines 18 are not limited to those described above. Besides, a film carrier technique may be used instead of mounting the IC 14 on the array board. Also, polyimide films and the like may be used for connection with the source signal lines 18 and the like.
Referring to
Main components of an electronic regulator circuit are a fixed resistor R0 (691a) and 16 unit registers r (691b). Output from the decoder circuit 692 is connected to one of 16 analog switches 641 and designed to determine the resistance value of the electronic regulator by the output from the decoder circuit 692. For example, if an output of the decoder circuit 692 is 4, the resistance value of the electronic regulator is R0+5r. The resistance value of the electronic regulator acts as a load on the first-stage current source 631 and is pulled up to an analog power supply AVdd. Thus, changes in the resistance value of the electronic regulator cause changes to the current value of the first-stage current source 631. This in turn causes changes to the current value of the second-stage current source 632, consequently causing changes to the current value of the third-stage current source 633. The output current of the driver IC is controlled in this way.
Incidentally, although it has been assumed for the sake of illustration that 4-bit data is used for current value control, this is not restrictive. Needless to say, the larger the bit count, the larger the number of steps of current. Also, although it has been stated that the multi-stage current mirrors have a three-stage configuration, needless to say, this is not restrictive and any number of stages may be used.
Besides, to deal with the problem of changes in emission brightness of the EL element caused by temperature changes, preferably the electronic regulator circuit is equipped with an external resistor 691a whose resistance changes with temperature.
Preferably, the multi-stage current mirror circuits are divided into three systems for red (R), green (G), and blue (B). Generally, organic EL or other current-driven light-emitting elements have different emission characteristics among R, G, and B. Thus, to obtain the same brightness among R, G, and B, the currents passed through the light-emitting elements should be adjusted separately for R, G, and B. Also, current-driven light-emitting elements such as for organic EL display panel have different temperature characteristics among R, G, and B. Thus, characteristics of auxiliary elements such as thermistors formed or placed to compensate for temperature characteristics should also be adjusted separately for R, G, and B.
Since the multi-stage current mirror circuits are divided into three systems for red (R), green (G), and blue (B), the present invention makes it possible to adjust emission characteristics and temperature characteristics separately for R, G, and B, and thereby obtain an optimum white balance.
As described earlier, in the case of current driving, only a small current is written into pixels during black display. Consequently, if the source signal lines 18 or the like have parasitic capacitance, current cannot be written into the pixels 16 sufficiently during one horizontal scanning period (1 H). Generally, in current-driven light-emitting elements, black-level current is as weak as a few nA, and thus it is difficult to drive parasitic capacitance (load capacitance of wiring) which is assumed to measure tens of pF using the signal value of the black-level current. To solve this problem, it is useful to equalize the black-level current in the pixel transistors 11a (basically, the transistors 11a are off) with the potential level of the source signal lines 18 by applying a precharge voltage before writing image data into the source signal lines 18. In order to form (create) the precharge voltage, it is useful to output the black level at a constant voltage by decoding higher order bits of image data.
Preferably, gradations for which precharging is performed should be limited to a black display region. Specifically, precharging is performed by selecting gradations in a black region (low brightness region, in which only a small (weak) write current flows in the case of current driving) from write image data (selective precharging). If precharging is performed over the entire range of gradations, brightness lowers (a target brightness is not reached) in a white display region. Also, vertical streaks may be displayed in some cases.
Preferably, selective precharging is performed for ⅛ of all the gradations beginning with the 0th gradation (e.g., in the case of 64 gradations, image data is written after precharging for the 0th to 7th gradations). More preferably, selective precharging is performed for 1/16 of all the gradations beginning with the 0th gradation (e.g., in the case of 64 gradations, image data is written after precharging for the 0th to 3rd gradations).
A method which performs precharging by detecting only the 0th gradation is also effective in enhancing contrast, especially in black display. It achieves an extremely good black display. The problem is that the screen appears whitish in hue when the entire screen displays the 1st and second gradations. Thus, selective precharging is performed in a predetermined range: ⅛ of all the gradations beginning with the 0th gradation. The method of performing precharging by extracting only the 0th gradation causes little harm to image display. Thus, it is most preferable to adopt this method as a precharging technique.
Incidentally, it is also useful to vary the precharge voltage and gradation range among R, G, and B because emission start voltage and emission brightness of EL elements 15 vary among R, G, and B. For example, selective precharging is performed for ⅛ of all the gradations beginning with the 0th gradation (e.g., in the case of 64 gradations, image data is written after precharging for the 01th to 7th gradations) in the case of R. In the case of other colors (G and B), selective precharging is performed for 1/16 of all the gradations beginning with the 0th gradation (e.g., in the case of 64 gradations, image data is written after precharging for the 0th to 3rd gradations). Regarding the precharge voltage, if 7 V is written into the source signal lines 18 for R, 7.5 V is written into the source signal lines 18 for the other colors (G and B). Optimum precharge voltage often varies with the production lot of the EL display panel. Thus, preferably precharge voltage is adjustable with an external regulator or the like. Such a regulator circuit can be also implemented easily using an electronic regulator circuit.
Incidentally, it is preferable that the precharge voltage is not higher than the anode voltage Vdd minus 0.5 V and within the anode voltage Vdd minus 2.5 V in
Even with methods which perform precharging only for the 0th gradation, it is useful to perform precharging selecting one or two colors from among R, G, and B. This will cause less harm to image display.
It is preferable to provide several modes which can be switched by command: including a 0th mode in which no precharging is performed, first mode in which precharging is performed only for the 0th gradation, second mode in which precharging is performed in the range of the 0th to 3rd gradations, third mode in which precharging is performed in the range of the 0th to 7th gradations, and fourth mode in which precharging is performed in the entire range of gradations and the like. These modes can be implemented easily by constructing (designing) a logic circuit in the source driver circuit (IC) 14.
Reference character PV denotes an input terminal of precharge voltage. Separate precharge voltages are set for R, G, and B by external inputs or by an electronic regulator circuit. Incidentally, although it has been stated that separate precharge voltages are set for R, G, and B, this is not restrictive. Precharge voltages may be common to R, G, and B because they are correlated with the Vt of the driver transistors 11a of the pixels 16, which do not differ among R, G, and B. If the W/L ratio and the like of the driver transistors 11a of the pixels 16 are varied (designed differently) among R, G, and B, preferably the precharge voltage is adjusted to the different designs. For example, a larger channel length L of the driver transistor 11a lowers diode characteristics of the transistor 11a and increases the source-drain (SD) voltage. Thus, the precharge voltage should be set lower than the source potential (Vdd).
The precharge voltage PV is fed to an analog switch 731. To reduce on-resistance, the W (channel width) of the analog switch 731 should be 10 μm or above. However, it is set to 100 μm or below because too large W will increase parasitic capacitance as well. More preferably, the channel width W should be between 15 μm and 60 μm (both inclusive). The above items also apply to the analog switch 731 in the switch 641b in
The switch 641a is controlled by a precharge enable (PEN) signal, selective precharging (PSL) signal, and the higher order three bits (H5, H4, and H3) of the logic signal in
Incidentally, although selective precharging may be performed for fixed gradations such as only the 0th gradation or a range of the 0th to 7th gradations, it may be performed automatically in any low gradation region specified (gradation 0 to gradation R1 or gradation “R1-1” in
The switch 641a is turned on or off depending on which of the above signals is applied. When the switch 641a is on, the precharge voltage PV is applied to the source signal line 18. Incidentally, the time during which the precharge voltage PV is applied is set by a counter (not shown) formed separately. The counter is configured to be set by command. Preferably, the application duration of the precharge voltage is from 1/100 to ⅕ of one horizontal scanning period (1 H) both inclusive. For example, if 1 H is 100 μsec, the application duration should be from 1 μsec to 20 μsec (from 1/100 to ⅕ of 1 H) both inclusive. More preferably, it should be from 2 μsec to 10 μsec (from 2/100 to 1/10 of 1 H) both inclusive.
The output from the coincidence circuit 1731 and output from the counter circuit 701 are ANDed by the AND circuit 703, and consequently a black level voltage Vp is output for a predetermined period. In other cases, the output current from the current output stage 704 described with reference to
Good results can also be obtained if the duration of application of the precharge voltage PV is varied using the image data applied to the source signal lines 18. For example, the application duration may be increased for the 0th gradation which corresponds to completely black display, and decreased for the 4th gradation. Also, good results can be obtained if the application duration is specified taking into consideration the difference between image data and image data to be applied 1 H later. For example, when writing a current into the source signal lines to put the pixels in black display mode 1 H after writing a current into source signal lines to put the pixels in white display mode, the precharge time should be increased. This is because a weak current is used for black display. Conversely, when writing a current into the source signal lines to put the white pixels in black display mode 1 H after writing a current into source signal lines to put the pixels in black display mode, the precharge time should be decreased or precharging should be stopped (no precharging should be done). This is because a large current is used for white display.
It is also useful to vary the precharge voltage depending on the image data to be applied. This is because a weak current is used for black display and a large current is used for white display. Thus, the precharge voltage is raised (in relation to Vdd) in a lower gradation region (when P-channel transistors are used as pixel transistors 11a) and the precharge voltage is lowered in a higher gradation region (when P-channel transistors are used as pixel transistors 11a).
For ease of understanding, description will be given below mainly with reference to
When a programming current open terminal (PO terminal) is “0,” the switch 1521 is off, disconnecting an IL terminal and IH terminal from the source signal line 18 (an Iout terminal is connected with the source signal line 18). Thus, the programming current Iw does not flow through the source signal line 18.
When the programming current Iw is applied to the source signal line, the PO terminal is “1,” keeping the switch 1521 on to pass the programming current Iw through the source signal line 18. “0” is applied to the PO terminal to open the switch 1521 when no pixel row in the display area is selected. The unit transistor 634 constantly draws current from the source signal line 18 based on input data (D0 to D5). This current flows into the source signal line 18 from the Vdd terminal of the selected pixel 16 via the transistor 11a. Thus, when no pixel row is selected, there is no path for current to flow from the pixel 16 to the source signal line 18. A period when no pixel row is selected occurs after the time when an arbitrary pixel row is selected until the time when the next pixel row is selected. Incidentally, the period during which no pixel (pixel row) is selected and there is no path for current to flow into (flow out into) the source signal line 18 is referred to as total non-selection period.
In this state, if the IOUT terminal is connected to the source signal line 18, current flows to activated unit transistors 634 (actually, what is activated are switches 641 controlled by data from the D0 to D5 terminals).
Consequently, charges in the parasitic capacitance of the source signal line 18 are discharged, lowering the potential of the source signal line 18 sharply. Then, it takes time for the current normally written into the source signal line 18 to restore the potential of the source signal line 18.
To solve this problem, the present invention applies “0” to the PO terminal during the total non-selection period to turn off the switch 1521 in
Consequently, no current flows from the source signal line 18 into the unit transistors 634, and thus the potential of the source signal line 18 does not change during the total non-selection period. In this way, by controlling the PO terminal during the total non-selection period and disconnecting current sources from the source signal line 18, it is possible to write current properly.
It is useful to add a (proper precharging) capability to stop precharging when a white display area (area with a certain brightness) (white area) and a black display area (area with brightness below a predetermined level) (black area) coexist in the screen and the ratio of the white area to the black area falls within a certain range because vertical streaks appear in this range. Conversely, precharging may be done in a range because images may act as noise when they move. Proper precharging can be implemented easily by counting (calculating) pixel data which correspond to the white area and black area using an arithmetic circuit.
It is also useful to vary precharge control among R, G, and B because emission start voltage and emission brightness of EL elements 15 vary among R, G, and B. For example, a possible method involves stopping or starting precharging for R when the ratio of a white area with a predetermined brightness to a black area with a predetermined brightness is 1 to 20 or above and stopping or starting precharging for G and B when the ratio of a white area with a predetermined brightness to a black area with a predetermined brightness is 1 to 16 or above. It has been shown experimentally and analytically that in an organic EL panel, preferably precharging should be stopped when the ratio of a white area with a predetermined brightness to a black area with a predetermined brightness is 1 to 100 or above (i.e., the black area is at least 100 times larger than the white area). More preferably, precharging should be stopped when the ratio of a white area with a predetermined brightness to a black area with a predetermined brightness is 1 to 200 or above (i.e., the black area is at least 200 times larger than the white area). When the driver transistors 11a of the pixels 16 are P-channel transistors, a voltage close to Vdd should be output, as a precharge voltage, from the source driver circuit (IC) 14 (see
However, as the precharge voltage PV gets closer to Vdd, a higher voltage resistance process is required for semiconductors used in the source driver circuit (IC) 14 (the high voltage resistance, however, is only on the order of 5 V to 10 V, but high voltage resistance in excess of 5 V increases the price of the semiconductor process). Thus, adoption of a 5-volt resistance process makes it possible to use high-resolution, inexpensive processes.
If 5 V is not exceeded when the diode characteristics of the driver transistors 11a in pixels 16 are good and on-state current for white display is established, there is no problem because the 5-volt process can also be used for the source driver IC 14. However, a problem arises when the diode characteristics exceed 5 V. During precharging, in particular, since a precharge voltage PV close to the source voltage Vdd of the transistor 11a must be applied, it is not possible to produce output from the IC 14.
The on/off signal is output from the terminal 761a of the IC 14 according to the precharge conditions described earlier (
With the above configuration, a power supply voltage capable of driving the programming current Iw in an operating voltage range is enough for the source driver circuit (IC) 14. The precharge voltage PV poses no problem for an array board 71 with a high operating voltage. Thus, the precharge voltage can be applied sufficiently up to the level of the anode voltage (Vdd).
The switch 1521 in
An example which can solve this problem is shown in
The switch circuit 641 is placed ahead of the output of the IC 14 and in the middle of the source signal line 18. As the switch 641 is turned on, the current Iw used to program the pixels 16 flows into the source driver circuit (IC) 14. As the switch 641 is turned off, the source driver circuit (IC) 14 is cut off from the source signal line 18. By controlling the switch 641, it is possible to implement the drive system and the like illustrated in
The voltage (signal) outputted from the terminal 761a is as low as 5 V or less, as in the case of
With the above configuration, a power supply voltage capable of driving the programming current Iw in an operating voltage range is enough for the source driver circuit (IC) 14. Since the switch 641 also operates on the power supply voltage of the array board 71, neither the switch 641 nor the source driver circuit (IC) 14 is broken even if the voltage Vdd is applied to the source signal line 18 from the pixels 16.
Incidentally, needless to say, both the switch 641 placed (formed) in the middle of the source signal line 18 in the
As described earlier, when the driver transistor 11a and selection transistors (11b and 11c) of the pixel 16 are P-channel transistors as shown in
However, although a completely black display can be achieved in the 0th gradation, it is difficult to display the 1st gradation and the like. In other cases, a large gradation jump may occur between the 0th and 1st gradations or black reproduction may occur in a particular gradation range. To solve this problem, a configuration in
Basically,
The above is a basic overview of the source driver circuit (IC) 14 according to the present invention. Now, the source driver circuit (IC) 14 according to the present invention will be described in more detail.
The current I (A) passed through the EL element 15 and emission brightness B (nt) have a linear relationship. That is, the current I (A) passed through the EL element 15 is proportional to the emission brightness B (nt). In current driving, each step (gradation step) is provided by current (unit transistor 634 (single-unit)).
Human vision with respect to brightness has square-law characteristics. In other words, quadratic brightness changes are perceived to be linear brightness changes. However, according to the relationship shown in
To solve this problem according to the present invention, the slope of output current is decreased in the low gradation region (from gradation 0 (complete black display) to gradation (R1)) and the slope of output current is increased in the high gradation region (from gradation R1 to the highest gradation (R)) as illustrated in
Incidentally, although two current slopes—in the low gradation region and high gradation region—are used in the above example, this is not restrictive. Needless to say, three or more slopes may be used. Needless to say, however, the use of two slopes is preferable because it simplifies circuit configuration. Preferably, a gamma circuit is capable of generating five or more slopes.
A technical idea of the present invention lies in the use of two or more values of current increment per gradation step in a current-driven source driver circuit (IC) and the like (basically, the circuit uses current outputs for gradation display. Thus, display panels are not limited to the active-matrix type and include the simple-matrix type).
In EL and other current-driven display panels, display brightness is proportional to the amount of current applied. Thus, the source driver circuit (IC) 14 according to the present invention can adjust the brightness of the display panel easily by adjusting a reference current which provides a basis for a current flowing through one current source (one unit transistor) 634.
In EL display panels, luminous efficiency varies among R, G, and B and color purity deviates from that of the NTSC standard. Thus, to obtain an optimum white balance, it is necessary to optimize ratios among R, G, and B. The optimization is performed by adjusting the RGB reference currents separately. For example, the reference current for R is set to 2 μA, the reference current for G is set to 1.5 μA, and the reference current for B is set to 3.5 A. Preferably, at least one of the reference currents for different colors can be changed, adjusted, or controlled, as described above.
The source driver circuit (source driver IC) 14 according to the present invention decreases the current mirror factor of the first-stage current source 631 in
Adjustment circuits for reference currents in low gradation regions and adjustment circuits for reference currents in high gradation regions are provided to achieve the gamma curve in
Also, although not shown, adjustment circuits for reference currents in low gradation regions and adjustment circuits for reference currents in high gradation regions are provided separately for R, G, and B so that adjustments can be made separately for R, G, and B. Of course, adjustment circuits for reference currents in low gradation regions and adjustment circuits for reference currents in high gradation regions may be provided for only two colors if white balance is adjusted by fixing one color and adjusting the reference currents for two colors (i.e., R and B if G is fixed).
In the case of current driving, the current I passed through the EL element and brightness have a linear relationship as also illustrated in
The gamma curve in
Thus, the current driving according to the present invention operates on the principle that there is a linear relationship between the current I applied to the pixel 16 and emission brightness of the EL element 15 as illustrated in
The gamma circuit of the present invention increments, for example, 10 nA per gradation in a low gradation region (corresponding to the slope of a gamma curve in the low gradation region). In a high gradation region, it increments 50 nA per gradation (corresponding to the slope of a gamma curve in the high gradation region).
Incidentally, the ratio of the current increment per gradation in the high gradation region to the current increment per gradation in the low gradation region is referred to as a gamma current ratio. According to this example, the gamma current ratio is 50 nA/10 nA=5. The same gamma current ratio should be used for R, G, and B. In other words, the current (programming current) flowing through the EL elements 15 is controlled with the gamma current ratio kept the same for R, G, and B.
If current is adjusted with the gamma current ratio kept the same for R, G, and B in this way, it becomes easier to configure the circuit. Then it suffices to build, for each of R, G, and B, a constant-current circuit which generates a reference current to be applied to the low gradation part and constant-current circuit which generates a reference current to be applied to the high gradation part and build (place) a regulator which relatively adjusts the current passed through the constant-current circuits.
Preferably, temperature of the display panel is detected with a temperature detection circuit 781 formed in the IC chip (circuit) 14 as illustrated in
Incidentally, an appropriate gamma ratio is between 3 and 10 (both inclusive). More preferably, the gamma ratio is between 4 and 8 (both inclusive). Preferably, the gamma current ratio, in particular, is between 5 and 7 (both inclusive). The above relations will be referred to as a first relationship.
It is appropriate to set a transition point (gradation R1 in
Incidentally, the above description concerns gamma current ratios between two current regions. However, the second relationship also applies to gamma current ratios among three or more current regions (i.e., where there are two or more breakpoints). That is, the relationship can be applied to any two of three or more slopes.
By satisfying the first and second relationships, it is possible to achieve proper image display free of loss of shadow detail.
When the S/M terminal is set to high, the source driver circuit 14 operates as a master chip and outputs a reference current through a reference current output terminal (not shown) This current flows to the INL and INH terminals (in
Different reference currents are passed between the reference current input terminal and reference current output terminal for different colors in the two gradation regions: low and high. In the case of RGB three colors, this means 6 (=3×6) kinds of reference current. Incidentally, although two kinds of reference current are used for each color in the above example, this is not restrictive and three or more kinds of reference current may be used for each color.
The current driving according to the present invention allows a breakpoint (gradation R1 and the like) to be changed as illustrated in
Specifically, the present invention can achieve a 64-gradation display. The breakpoint (gradation R1) can be set to any of the following: none, 2nd gradation, 4th gradation, 8th gradation, and 16th gradation. Incidentally, the reason why the breakpoint can be the 2nd, 4th, 8th, or 16th gradation is that completely black display corresponds to the 0th gradation. If completely black display corresponds to the 1st gradation, the breakpoint can be the 3rd, 5th, 9th, 17th, or 33rd gradation. In this way, if the breakpoint is set to the n-th gradation (or (n+1)-th gradation if completely black display corresponds to the 1st gradation) where n is a power of two, circuit configuration is made easier.
Also, as shown in
The same applies to the padder current circuit portion. As shown in
The programming current Iw flowing to the source signal line 18 is given by Iw=IwH+IwL+IwK.
The ratio of IwH to IwL, i.e., the gamma current ratio should satisfy the first relationship described earlier.
As illustrated in
Now, description will be given of the low-current circuit portion in
As described above, the 6-bit input data is converted into 11-bit data (=5+6). According to the present invention, the bit count (H) in the high-current region of the circuit is equal to the bit count of input data (D) while the bit count (L) in the low-current region of the circuit is equal to the bit count of input data (D) minus 1. Incidentally, the bit count (L) in the low-current region of the circuit may be the bit count of input data (D) minus 2. This configuration optimizes the gamma curve in the low-current region and gamma curve in the high-current region for image display on the EL display panel.
A control method for circuit control data (L0 to L4) in the low-current region and circuit control data (H0 to H4) in the high-current region will be described below with reference to
The present invention is characterized by operation of the unit transistor 634a connected to an L4 terminal in
Referring to
In the 1st gradation, (L0 to L4)=(1, 0, 0, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, one unit transistor 634 in the low-current region is connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
In the 2nd gradation, (L0 to L4)=(0, 1, 0, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, two unit transistors 634 in the low-current region are connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
In the 3rd gradation, (L0 to L4)=(1, 1, 0, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, two switches 641La and 641Lb in the low-current region turn on and three unit transistors 634 are connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
In the 4th gradation, (L0 to L4)=(1, 1, 0, 0, 1) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, three switches 641La, 641Lb, and 641Le in the low-current region turn on and four unit transistors 634 are connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
In the 5th and higher gradations, there is no change in the low-current region, i.e., (L0 to L4)=(1, 1, 0, 0, 1). In the high-current region, however, (H0 to H5)=(1, 0, 0, 0, 0) in the 5th gradation. Thus, a switch 641Ha turns on and one unit current source 641 in the high-current region is connected to the source signal line 18. In the 6th gradation, (H0 to H5)=(0, 1, 0, 0, 0). Thus, a switch 641Hb turns on and two unit current sources 641 in the high-current region are connected to the source signal line 18. Similarly, in the 7th gradation, (H0 to H5)=(1, 1, 0, 0, 0). Thus, two switches 641Ha and 641Hb turn on and three unit current sources 641 in the high-current region are connected to the source signal line 18. In the 8th gradation, (H0 to H5)=(0, 0, 1, 0, 0). Thus, a switch 641Hc turns on and four unit current sources 641 in the high-current region are connected to the source signal line 18 as illustrated in
A feature of the above operations is that after the breakpoint, the programming current Iw applied to the high gradation part is composed of the current for the low gradation part plus a current which corresponds to each step (gradation) in the high gradation part. A change point of the low-current region and the high-current region, specifically, in the high-current region, for the programming current Iw, low current IwL is added. Therefore, the reference to “change point” may not be correct. A padding current IwK is also added.
Also, control bits (L) in the low gradation region do not change after a gradation step (a point or location where current changes, to be exact). At this time, the L4 terminal in
Thus, in the 4th gradation in
It can be seen that the unit transistor 634a at the terminal L4 in
This makes it easy to judge whether a weighting signal line by 2 is set to “1.” Consequently, the hardware scale required for the judgment can be reduced. In other words, IC chip logic circuits can be simplified, making it possible to design an IC with a small chip area (resulting in low costs).
Referring to
Similarly, in the 1st gradation, (L0 to L4)=(1, 0, 0, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, one unit transistor 634 in the low-current region is connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
In the 2nd gradation, (L0 to L4)=(0, 1, 0, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, two unit transistors 634 in the low-current region are connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
In the 3rd gradation, (L0 to L4)=(1, 1, 0, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, two switches 641La and 641Lb in the low-current region turn on and three unit transistors 634 are connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
Similarly, in the 4th gradation, (L0 to L4)=(0, 0, 1, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). In the 5th gradation, (L0 to L4)=(1, 0, 1, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). In the 6th gradation, (L0 to L4)=(0, 1, 1, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). In the 7th gradation, (L0 to L4)=(1, 1, 1, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0).
The 8th gradation corresponds to a change point (breakpoint location). In the 8th gradation, (L0 to L4)=(1, 1, 1, 0, 1) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, four switches 641La, 641Lb, 641Lc, and 641Le in the low-current region turn on and eight unit transistors 634 are connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
In the 8th and higher gradations, there is no change in the low-current region, i.e., (L0 to L4)=(1, 1, 1, 0, 1). In the high-current region, however, (H0 to H5)=(1, 0, 0, 0, 0) in the 9th gradation. Thus, the switch 641Ha turns on and one unit current source 641 in the high-current region is connected to the source signal line 18.
Similarly, the number of unit transistors 634 in the high-current region increases one by one with increasing gradation steps. Specifically, in the 10th gradation, (H0 to H5)=(0, 1, 0, 0, 0). The switch 641Hb turns on and two unit current sources 641 in the high-current region are connected to the source signal line 18. Similarly, in the 11th gradation, (H0 to H5)=(1, 1, 0, 0, 0). Two switches 641Ha and 641Hb turn on and three unit current sources 641 in the high-current region are connected to the source signal line 18. In the 12th gradation, (H0 to H5)=(0, 0, 1, 0, 0). The switch 641Hc turns on and four unit current sources 641 in the high-current region are connected to the source signal line 18. Subsequently, switches 641 turn on and off in sequence and the programming current Iw is applied to the source signal line 18 as illustrated in
Specifically, referring to
Specifically, (L0 to L4)=(1, 0, 0, 0, 0) in the 1st gradation, (L0 to L4)=(0, 1, 0, 0, 0) in the 2nd gradation, (L0 to L4)=(1, 1, 0, 0, 0) in the 3rd gradation, and (L0 to L4)=(0, 0, 1, 0, 0) in the 2nd gradation. This continues to the 16th gradation. Specifically, (L0 to L4)=(1, 1, 1, 1, 0) in the 15th gradation and (L0 to L4)=(1, 1, 1, 1, 1) in the 16th gradation. In the 16th gradation, only the 5th bit (D4) out of D0 to D5 which represent gradations turns on, and thus it can be determined from the data signal line (D4) that the data D0 to D5 represent the 16th gradation. This reduces the hardware scale required for logic circuits.
The 16th gradation corresponds to a change point (breakpoint location). Rather, it ought to be said that the 17th gradation corresponds to a change point. In the 16th gradation, (L0 to L4)=(1, 1, 1, 1, 1) and (H0 to H5)=(0, 0, 0, 0, 0). Thus, four switches 641La, 641Lb, 641Lc, 641d, and 641Le in the low-current region turn on and 16 unit transistors 634 are connected to the source signal line 18. No unit current source in the high-current region is connected to the source signal line 18.
In the 16th and higher gradations, there is no change in the low-current region, i.e., (L0 to L4)=(1, 1, 1, 0, 1). In the high-current region, however, (H0 to H5)=(1, 0, 0, 0, 0) in the 17th gradation. Thus, the switch 641Ha turns on and one unit current source 641 in the high-current region is connected to the source signal line 18.
Similarly, the number of unit transistors 634 in the high-current region increases one by one with increasing gradation steps. Specifically, in the 18th gradation, (H0 to H5)=(0, 1, 0, 0, 0). The switch 641Hb turns on and two unit current sources 641 in the high-current region are connected to the source signal line 18. Similarly, in the 19th gradation, (H0 to H5)=(1, 1, 0, 0, 0). Two switches 641Ha and 641Hb turn on and three unit current sources 641 in the high-current region are connected to the source signal line 18. In the 20th gradation, (H0 to H5)=(0, 0, 1, 0, 0). The switch 641Hc turns on and four unit current sources 641 in the high-current region are connected to the source signal line 18.
The above method results in extremely easy logic processing such as turning on (or turning off in an alternative configuration) current sources (single-unit transistors) 634 equal in number to a power of two or connecting them to the source signal line 18 at the change point (breakpoint location).
For example, if the breakpoint location corresponds to the 4th gradation (4 is a power of two) as illustrated in
On the other hand, if the breakpoint location corresponds to the 8th gradation (8 is a power of two) as illustrated in
Incidentally, although in the examples described with reference to
What is important in the present invention is to provide a plurality of current regions (low-current region, high-current region, etc.) and be able to judge (process) a change point between the current regions using a small number of signal inputs. For example, one technical idea behind the present invention is that if a power of two is used, only a single signal line needs to be detected, reducing the hardware scale greatly. Also, a current source 634a is added to ease the processing required for that.
In the case of negative logic, the change point can be set to 1, 3, 7, 15, or the like instead of 2, 4, 8, or the like. Also, although it has been stated that the 0th gradation corresponds to completely black display, this is not restrictive. For example, in the case of 64-gradation display, the 63rd gradation may be designated as completely black display and the 0th gradation may be designated as a maximum white display. In that case, the change point can be processed, taking into consideration the reverse direction. Thus, processing may not be based on powers of two.
The change point (breakpoint location) is not limited to a single gamma curve. The circuits according to the present invention allows existence of two or more breakpoint locations. For example, breakpoint locations may be set to the 4th and 16th gradations. Alternatively, breakpoint locations may be set to more than two locations such as the 4th, 16th, and 32nd gradations.
In the above example, the breakpoint is set to the n-th gradation where n is a power of two, but this is not restrictive. For example, a breakpoint may be set to the gradation given by the sum of 2 and 8 which are powers of two (2+8=10; i.e., two signal lines are needed for judgment). Alternatively, a breakpoint may be set to the gradation given by the sum of 2, 8, and 16 which are powers of two (2+8+16=28; i.e., three signal lines are needed for judgment). In that case, the hardware scale required for judgment or processing is increased more or less, but is not difficult to deal with in terms of circuit configuration. Also, needless to say, the above items are included in the technical scope of the present invention.
As illustrated in
The high-current-region current output circuit 704a and the current-padding current output circuit 704c operate with a reference current source 771a which outputs high current, as reference current, while the low-current-region current output circuit 704b operates with a reference current source 771b which outputs low current, as reference current.
As also described earlier, the number of current output circuits 704 is not limited to three: the high-current-region current output circuit 704a, low-current-region current output circuit 704b, and current-padding current output circuit 704c. The source driver circuit (IC) 14 may consists of two current output circuits 704—the high-current-region current output circuit 704a and low-current-region current output circuit 704b—or three or more current output circuits 704. Also, reference current sources 771 may be placed or formed for respective current output circuits 704 or a common reference current source 771 may be provided for all the current output circuits 704.
The current output circuits 704 respond to gradation data, and unit transistors 634 in them operate by drawing current from the source signal line 18. Said and unit transistors 634 operate in sync with a horizontal scanning period (1 H) signal. That is, current is fed based on appropriate gradation data for a period of 1 H (if the unit transistors 634 are N-channel transistors).
On the other hand, the gate driver circuit 12 selects gate signal lines 17a basically one by one in sync with the 1 H signal. That is, in sync with the 1-H signal, the gate signal line 17a(1) is selected in the first horizontal scanning period, gate signal line 17a(2) is selected in the second horizontal scanning period, gate signal line 17a(3) is selected in the third horizontal scanning period, and gate signal line 17a(4) is selected in the fourth horizontal scanning period.
However, between the time when the first gate signal line 17a is selected and the time when the second gate signal line 17a is selected, there is a period in which no gate signal line 17a is selected (non-selection period; see t1 in
If a turn-on voltage is applied to any of the gate signal lines 17a and the transistor 11b and selection transistor 11c of the pixel 16 are on, programming current Iw flows from the Vdd power supply (anode voltage) to the source signal line 18 via the driver transistor 11a. The programming current Iw flows through the unit transistors 634 (for a period of t2 in
However, when no gate signal line 17a is selected (non-selection period; t1 in
To solve this problem, a switch 641a is formed at an output end of the source terminal 761 as illustrated in
During the non-selection period t1, a control signal is applied to a control terminal S1 and the switch 641a is turned off. During the selection period t2, the switch 641a is turned on (conducting). The programming current Iw=IwH+IwL+IwK flows when the switch 641a is on. When the switch 641a is turned off, the current Iw does not flow. Thus, as illustrated in
The switch 641b performs control only during low gradation display. During low gradation display (black display), the gate potential of the pixel 16 transistor 11a must be close to Vdd (thus, during black display, the potential of the source signal line 18 must be close to Vdd). Also, during black display, the programming current Iw is small, and once the potential falls as indicated by A in
Thus, during low gradation display, non-selection periods t1 must be avoided. In contrast, during high gradation display, since the programming current Iw is large, non-selection periods t1 often do not present a problem. Thus, according to the present invention, when images are written for high gradation display, both switch 641a and switch 641b are kept on even during non-selection periods. Also, the padding current IwK must be shut off to achieve black display to the utmost. When images are written for low gradation display, the switch 641a is kept on and the switch 641b is kept off even during non-selection periods. The switch 641b is controlled via terminal S2.
Incidentally, it is also possible to keep the switch 641a off (non-conducting) and keep the switch 641b on (conducting) for both low gradation display and high gradation display during non-selection periods t1. Off course, both switches 641a and 641b may be kept off (non-conducting) for both low gradation display and high gradation display during non-selection periods t1. In either case, the switches 641 can be controlled by controlling the control terminals S1 and S2. Incidentally, the control terminals S1 and S2 are controlled via command control.
For example, the control terminal S2 sets a t3 period to logic 0 in such a way as to overlap the non-selection period t1. This control eliminates the condition indicated by A in
In a typical driver IC, protective diodes 1671 are formed near the output (see
The protective diodes 1671 are effective for prevention from electrostatic damage. However, static electricity is regarded as a capacitor (parasitic capacitance) in an equivalent circuit diagram. In current driving, presence of parasitic capacitance at an output terminal 643 makes current writing difficult.
The present invention provides a method of solving this problem. The source driver IC 14 is manufactured with the protective diodes 1671 formed in the output stage. The manufactured source driver IC 14 is mounted or placed on an array board 71 and the output terminals 761 are connected to the source signal lines 18. After the output terminals 761 are connected to the source signal lines 18, the output wiring 643 is cut at points a and b with laser light 1502 as illustrated in
In this way, by cutting off the protective diodes 1671 from the output wiring 643 or isolating the protective diodes 1671, it is possible to prevent the protective diodes 1671 from producing parasitic capacitance. Also, since the protective diodes 1671 are cut off from the output wiring 643 or isolated after the IC 14 is mounted, there is no problem of electrostatic damage.
Incidentally, the laser light 1502 is directed at the back surface of the array board 71 as illustrated in
It has been assumed in the above example that one source driver IC 14 is mounted on the display panel. However, the present invention is not limited to this arrangement. A plurality of source driver ICs 14 may be mounted on the display panel. For example,
As also described with reference to
Slave/master switching may be done through commands given to the source driver IC 14. The reference current is transmitted via a cascade current connection line 931. When the S/M terminal is set to low, the IC 14 operates as a slave chip and receives a reference current from a master chip through a reference current input terminal (not shown). This current flows to the INL and INH terminals in
To take an example, the reference current is generated by the current output circuit 704 right at the center of the IC chip 14. The reference current for the master chip is adjusted with an external resistor or an internal step-current electronic regulator before it is applied.
A control circuit (command decoder) and the like are also formed (placed) in the center of the IC chip 14. The reason why the reference current source is formed in the center of the chip is to minimize the distance to the reference current generator circuits and programming current output terminals 761.
In the configuration in
The current (or voltage; see
Based on the current (voltage) applied to the reference current signal lines 932, current sources (631, 632, 633, and 634) are driven in the chip 14. The reference currents produced here are output as reference currents for the slave chips via current mirror circuits. The reference currents for the slave chips are output from terminals 941o. At least one terminal 941o is placed (formed) on each side of the current output circuit 704. In
In the organic EL display panel, although EL elements 15 require a relatively low drive voltage, a large current flows through the EL elements 15. Thus, it is necessary to increase the size of the anode wiring and cathode wiring which supply current to EL element 15. For example, even in a 2-inch class EL display panel, if polymeric EL material is used, 200-mA or higher current must be passed through the anode wiring 951. To reduce voltage drops in the anode wiring 951, the resistance of the anode wiring 951 must be reduced to 1 Ω or below. However, with an array board 71, on which wiring is formed by thin film vapor deposition, it is difficult to reduce resistance. Therefore, it is necessary to increase pattern width. However, to transmit a 200-mA current with minimum voltage drop, the wiring must be at least 2 mm wide.
Built-in gate driver circuits 12a and 12b are formed (placed) on both sides of a display screen 50. A source driver circuit 14p (built-in source driver circuit) is formed through the same process as pixel 16 transistors.
Anode wiring 951 is placed on the right of the panel. A Vdd voltage is applied to the anode wiring 951. The width of the anode wiring 951 is 2 mm or more, for example. The anode wiring 951 running along the bottom of the screen branches to the top of the screen. The number of branches is equal to the number of pixel columns. For example, a QCIF panel has 528 (=176×RGB) pixel columns. On the other hand, source signal lines 18 come out of the built-in source driver circuit 14p. The source signal lines 18 are run (formed) from top to bottom of the screen. Power supply wirings 1051 of the built-in gate driver circuits 12 are also placed on the left and right of the screen.
Thus, bezel width on the right side of the display panel cannot be reduced. Today, reduction of bezel width is important for display panels used for cell phones and the like. It is also important to provide equal bezel width on the left and right of the screen. With the configuration in
To solve this problem, in the display panel according to the present invention, the anode wiring 951 is placed (formed) on the surface of the array behind the source driver IC 14 as illustrated in
As shown in
Also, as illustrated in
If the common anode line 962 is 20 mm long, if wiring width is 150 μm, and if sheet resistance of the wiring is 0.05 Ω/□, the value of resistance is given by 20000 (μm)/150 (μm)×0.05 Ω=approx. 7 Ω. If both ends of the common anode line 962 are connected to the base anode line 951 by a connection anode line 961c, the common anode line 962 is supplied with power from both sides, and consequently an apparent resistance value is 3.5 Ω (=7 Ω/2). If this value is converted into a concentrated distribution multiplier, the apparent resistance value of the common anode line 962 is further halved and becomes 2 Ω or less. Even if anode current is 100 mA, a voltage drop in the common anode line 962 is 0.2 V or less. Furthermore, if the common anode line 962 and base anode line 951 are short-circuited by the connection anode line 961b in the center, there is almost no voltage drop.
The present invention is characterized in that the base anode line 951 is formed under the IC 14, that the common anode line 962 is formed, that the common anode line 962 is electrically connected to the base anode line 951 (the connection anode line 961), and that the anode wires 952 branch off from the common anode line 962.
Incidentally, the pixel configuration according to the present invention is described by taking the pixel configuration in
To reduce the resistance of anode wires (the base anode line 951, common anode line 962, connection anode lines 961, anode wires 952), a thick film may be formed by laminating conductive material using an electroless plating, electrolytic plating, or other technique after laying thin-film wiring or before patterning. The use of a thick film increases the cross-sectional area of wiring, and thereby reduces resistance. The above items similarly apply to the cathode. They also apply to the gate signal lines 17 and source signal lines 18.
The provision and use of common anode line 962 which is supplied with power from both sides via the connection anode lines 961 is effective and the formation of the connection anode line 961b (961c) in the center enhances this effect. Also, the base anode line 951, common anode line 962, and connection anode lines 961 form a loop, which can reduce electric fields produced in the IC 14.
Preferably, the common anode line 962 and base anode line 951 are made of the same metal material and the connection anode lines 961 are also made of the same metal material. Also, these anode lines are implemented using a metal material or construction which forms an array and has a very low resistance value. Generally, they are implemented using the same metal material and construction (SD layer) as the source signal lines 18. The same material cannot be used for the spot where the common anode line 962 and source signal line 18 intersect. Thus, another metal material (the same material and construction as the gate signal lines 17; GE layer) is used at the intersections, which are then electrically insulated with an insulating film. Of course, the anode lines may be constructed by laminating a thin film made of the same material as the source signal lines 18 and a thin film made of the same material as the gate signal lines 17.
Incidentally, although it has been stated that wiring such as a node wiring (cathode wiring) is laid on the back surface of the source driver IC 14 to supply current to EL elements 15, this is not restrictive. For example, the gate driver circuits 12 may be constructed with an IC chip and this IC may be mounted by COG. Then, anode wiring and cathode wiring are laid (formed) on the back surface of the gate driver IC 12.
Thus, the present invention involves fabricating a driver IC with a semiconductor chip, mounting the IC directly on a substrate such as an array board 71, and forming (fabricating) a power supply or ground pattern such as anode wiring and cathode wiring in a space on the back of the IC chip for an EL display apparatus or the like.
The above items will be described in more detail with reference to other drawings.
The IC chip 14 has its current output (current input) terminals 741 connected by COG technology with connection terminals 953 formed on the array board 71. The connection terminal 953 is formed on one end of each source signal line 18. The connection terminals 953 are arranged in a staggered manner with alternating 953a and 953b. The connection terminal 953 is formed on one end of the source signal line, and a terminal electrode for checking is formed on the other end.
Although it has been stated that the IC chip according to the present invention is a current-driven driver IC (by which pixels are programmed with current), this is not restrictive. For example, the present invention is also applicable to EL display panels (apparatus) equipped with a voltage-driven driver IC by which pixels are programmed with voltage as shown in
The anode wires 952 (anode wiring after branching) are placed between the connection terminals 953a and 953b. That is, the anode wires 952 branching off from the thick, low-resistance base anode line 951 is formed between the connection terminals 953 and laid along the pixel 16 columns. Thus, the anode wires 952 and source signal lines 18 are formed (placed) in parallel. This configuration (formation) makes it possible to apply the voltage Vdd to each pixel without routing the base anode line 951 to the side of the screen as shown in
According to the present invention, in the high-current-region current output circuit 704a part in
According to the present invention, connection anode lines 961 are formed in the center of the IC chip 14. Needless to say, however, the connection anode lines 961 are formed on a surface of the array board 71. The width of the connection anode lines 961 is between 50 and 1000 μm (both inclusive) Also, the resistance (the maximum resistance) with respect to the length should be 100 Ω or less.
The base anode line 951 and common anode line 962 should be short-circuited by the connection anode lines 961 to minimize voltage drops caused by current flowing through the common anode line 962. That is, the connection anode lines 961, which are a component of the present invention, take advantage of the absence of output circuits in the center of the IC chip. By removing output terminals 761 conventionally formed as dummy pads in the center of the IC chip, the present invention prevents electrical effects which would be caused if the dummy pads contact the connection anode lines 961.
However, if the dummy pads are electrically insulated from a base substrate of the IC chip (ground of the chip) or other structure, there is no problem at all even if the dummy pads contact the connection anode lines 961. Thus, needless to say, the dummy pads may also be formed in the center of the IC chip.
More specifically, the connection anode lines 961 and common anode line 962 are formed (placed) as shown in
The base anode line 951 and common anode line 962 are short-circuited not only via the central connection anode line 961b, but also via the right and left connection anode lines 961c. That is, the common anode line 962 and base anode line 951 are short-circuited by three connection anode lines 961. With this configuration, the common anode line 962 are less prone to voltage drops even if a large current flows through the common anode line 962. This is because the IC chip 14 is normally 2 mm or more in width, making it possible to increase the line width (decrease the impedance) of the base anode line 951 formed under the IC 14. Consequently, the low-impedance base anode line 951 and common anode line 962 are shorted by the connection anode lines 961 at a few locations, reducing voltage drops in the common anode line 962.
The voltage drops in the common anode line 962 can be reduced in this way, because the base anode line 951 can be placed (formed) under the IC chip 14, the connection anode lines 961c can be placed (formed) on left and right of the IC chip 14, and the connection anode line 961b can be placed (formed) in the center of the IC chip 14.
Also, in
Incidentally, it has been stated in the example in
Thus, the semiconductor chip may be not only a source driver IC 14, but also a gate driver circuit 12 or power supply IC. Also, the technical idea of the present invention includes mounting a semiconductor chip on a flexible board and laying (forming) a power supply or ground pattern for EL elements 15 or the like in a space on the flexible board and on the back of the semiconductor chip. Of course, both source driver IC 14 and gate driver IC 12 may be constructed of semiconductor chips and mounted on the array board 71 by COG. Then, the power supply or ground pattern may be formed on the back surface of the chips. Also, although it has been stated that the power supply or ground pattern is intended for the EL elements 15, this is not restrictive and the power supply may be intended for the source driver circuit 4 or gate driver circuit 12. Besides, the technical idea of the present invention applies not only to EL display apparatus, but also to liquid crystal display apparatus. It is also applicable to FED, PDP, and other display panels. The above items are also true to other examples of the present invention.
The anode lines 961d are connected with the base anode line 951 in contact holes 971a while the anode wires 952 are connected with the common anode line 962 in contact holes 971b. In other respects (the connection anode lines 961a, 961b, 961c and anode capacitor, etc.),
Possible materials for the insulating film 102 include, for example, organic materials such as polyvinyl alcohol (PVA) resin, epoxy resin, polypropylene resin, phenol resin, acrylic resin, polyimide resin as well as inorganic materials such as SiO2 and SiNx. Needless to say, A123, Ta203, and the like are also included in the possible materials. Also, as illustrated in
In
Although it has been stated with reference to
The bumps and the source signal lines 18 are connected electrically via a conductive bonding layer (not shown). The conductive bonding layer is made of an epoxy or phenolic base resin mixed with flakes of silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO2), and the like, or made of an ultraviolet curing resin. The conductive bonding layer (bonding resin) 1001 is formed on the bump by a transfer or other technique. Also, the bumps and the source signal lines 18 are bonded by thermocompression using an ACF resin 1001.
Incidentally, the techniques for connecting the bumps or output pads 761 with the source signal lines 18 are not limited to those described above. Besides, a film carrier technique may be used instead of mounting the IC 14 on the array board. Also, polyimide films or the like may be used for connection with the source signal lines 18.
Anode wires 952 branch off from the common anode line 962. There are 528 (=176×RGB) anode wires 952 in a QCIF panel. The voltage Vdd (anode voltage) illustrated in
Thus, to maintain voltage drops in the common anode line 962 at 0.2 (V) or below, the maximum resistance value of paths through which the current flows must be maintained at or below 2 Ω (assuming that a current of 100 mA flows). According to the present invention, since the connection anode lines 961 are formed at three locations as shown in
A problem is the effect of parasitic capacitance (referred to as common anode parasitic capacitance) in portions where the common anode line 962 and source signal lines 18 overlap. Basically, in current driving, presence of parasitic capacitance in source signal lines 18 makes it difficult to write black display current into the source signal lines 18. Thus, parasitic capacitance needs to be minimized.
The common anode parasitic capacitance must not be larger than 1/10 of parasitic capacitance (referred to as display parasitic capacitance) generated by one source signal line 18 in a display area. For example, if the display parasitic capacitance is 10 (pF), the anode parasitic capacitance must be 1 (pF) or less. More preferably, the anode parasitic capacitance is not larger than 1/20 of the display parasitic capacitance. If the display parasitic capacitance is 10 (pF), the anode parasitic capacitance must be 0.5 (pF) or less. The line width (M in
The base anode line 951 is formed (placed) under the IC chip 14. Needless to say, its line width should be as thick as possible to reduce resistance. Besides, preferably the base anode line 951 is provided with a light shielding function.
An explanatory diagram is shown in
Of course, a reflector plate (sheet) or light-absorbing plate (sheet) made of a metal foil, plate, or sheet may be placed, inserted or formed in the space between the array board 71 and IC chip 14. Needless to say, it is also possible to place, insert or form a reflector plate (sheet) or light-absorbing plate (sheet) made of a foil, plate or sheet of organic or inorganic material rather than a metal foil. Alternatively, light-absorbing material or light-reflecting material in a gel or liquid state may be inserted or formed in the space between the array board 71 and IC chip 14. Preferably, light-absorbing material or light-reflecting material in the gel or liquid state are solidified by heating or by exposure to light. Incidentally, it is assumed for ease of explanation that the base anode line 951 is made of a light-shielding film (light-reflecting film).
As shown in
Although it has been stated with reference to
A large number of transistor elements, such as current sources 634, which pass minute current are formed on the IC chip 14 (circuit forming section 1021 in
To deal with this problem, the present invention constructs the base anode line 951 on the array board 71 and uses it as a light-shielding film. The formation area of the base anode line 951 covers the circuit forming section 1021 as illustrated in
In the case of organic EL or other self-luminous elements, light produced by the EL elements 15 is reflected diffusely within the array board 71, causing intense light to be radiated from places other than the display screen 50. To prevent or reduce the diffusely reflected light, light-absorbing films 1011 are formed in ineffective areas which do not pass light effective for image display as illustrated in
Possible materials for light-absorbing films include, for example, organic material such as acrylic resin containing carbon, organic resin with a black pigment dispersed in it, and gelatin or casein colored with a black acidic dye as with a color filter. Besides, they also include a fluorine-based pigment which singly develops a black color as well as green and red pigments which develop a black color when mixed. Furthermore, they also include PrMnO3 film formed by sputtering, phthalocyanine film formed by plasma polymerization, etc.
All the above materials develop black colors, but materials which develop a color complementary to the color developed by display elements may also be used for the light-absorbing films. For example, light-absorbing materials for color filters can be used by modifying them so as to provide desired light-absorbing characteristics. Basically, natural resin colored by dyes may be used as is the case with the black light-absorbing materials described above. It is also possible to use plastics in which dyes are dispersed. In that case, an available range of pigments is wider than in the case of black pigments and includes azo dyes, anthraquinone dyes, phthalocyanine dyes, and triphenylmethane dyes. An appropriate one of them or a combination of two or more of them may be used.
Besides, metal materials may also be used for the light-absorbing films. Possible materials include, for example, hexavalent chromium. Hexavalent chromium is black in color and functions as a light-absorbing film. Besides, light-scattering materials such as opal glass and titanium oxide are also available. By scattering light, it is often possible to absorb light as a result.
Incidentally, the sealing lid 85 is bonded to the array board 71 using a sealing resin 1031 containing resin beads 1012 from 4 μm to 15 μm (both inclusive) in diameter. The sealing lid 85 is placed without applying pressure and fixed.
The example illustrated in
Preferably, the common anode line 962 is made of the same metal material as the source signal lines 18 to minimize its resistance. According to the present invention, it is made of metal material (SD metal) such as thin Cu film, thin Al film, Ti/Al/Ti laminate, alloy, or amalgam. Thus, this material is replaced by the same metal material (GE metal) as the gate signal lines 17 at intersections of the source signal lines 18 and common anode line 962 to prevent short circuits. The gate signal lines are made of metal material, namely a Mo/W laminate.
Generally, the sheet resistance of gate signal lines 17 is higher than the sheet resistance of source signal lines 18. This is common to liquid crystal display apparatus. However, in organic EL display panels of a current-driving type, the current flowing through source signal lines 18 is as weak as 1 to 5 μA. Thus, even if the source signal lines 18 have a high resistance, almost no voltage drop occurs, and thus proper image display can be achieved. In liquid crystal display apparatus, image data is written into the source signal lines 18 by way of voltage. Thus, if the source signal lines 18 have a high resistance value, it is not possible to write images in one horizontal scanning period.
With the current driving according to the present invention, however, a high resistance value (i.e., a high sheet resistance value) of the source signal lines 18 does not pose a problem. Therefore, the sheet resistance of the source signal lines 18 may be higher than the sheet resistance of the gate signal lines 17. Thus, in the EL display panel of the present invention, the source signal lines 18 may be made (formed) of GE metal and the gate signal lines 17 may be made (formed) of SD metal as illustrated in
A configuration in
Preferably, however, the gate driver circuit 12a which selects the gate signal line 17a (which controls the selection transistors 11b and 11c) and gate driver circuit 12b which selects the gate signal line 17b (which controls the transistor 11d and current flowing through the EL element 15) have different power supply voltages. In particular, it is preferable that the amplitude (difference between turn-on voltage and turn-off voltage) of the gate signal line 17a is small. This is because the smaller the amplitude of the gate signal line 17a, the smaller the penetration voltage to the capacitor 19 in the pixel 16 (see
Thus, as illustrated in
Normally, N-channel transistors and P-channel transistors are used for the gate driver circuits 12, but preferably, only P-channel transistors are used. This is because it will reduce the number of masks used in fabrication of arrays, increase production yields, and improve throughput. Thus, as illustrated in
However, if only P-channel transistors are used for the gate driver circuits 12 and the like, no level shifter circuit can be formed on the array board 71. This is because level shifter circuits employ N-channel transistors and P-channel transistors.
To solve this problem, the present invention incorporates level shifter circuit functions into a power supply IC 1091.
To generate the anode and cathode voltages of the EL elements 15 of the gate driver circuits 12, the power supply IC 1091 needs to employ high voltage semiconductor processes. Such voltage resistance allows a level shift to signal voltage of the gate driver circuits 12. Also, as illustrated in
In
The configurations in
Upon receiving the data signal 1092 for use to control the gate driver circuits 12, the power supply circuit 1091 level-shifts it with a built-in level shifter circuit and outputs the resulting signal as a gate driver circuit control signal 1093 to control the gate driver circuits 12.
Now description will be given of the gate driver circuits 12 according to the present invention which are contained in the array board 71 and employ only P-channel transistors. As described earlier, by employing only P-channel transistors for the pixels 16 and gate driver circuits 12 (i.e., the transistors formed on the array board 71 are only P-channel transistors, meaning that no N-channel transistor is used), it is possible to reduce the number of masks used in fabrication of arrays, increase production yields, and improve throughput. Also, since it is possible to focus on improving performance of only P-channel transistors, characteristics can be improved easily as a result. For example, it is easier to lower threshold voltage (Vt) (bring it closer to 0 (V)) and reduce variations in the Vt than in the case of CMOS structures (an arrangement using P-channel and N-channel transistors).
To take an example, according to the present invention, one gate driver circuit 12 each is placed on a phase basis (shift registers), formed or constructed on the left and right of the display screen 50 as illustrated in
One of the gate driver circuits 12 is a selection-side gate driver circuit 12a. It controls the pixel transistors 11 by applying turn-on voltage or turn-off voltage to the gate signal lines 17a. The other gate driver circuit 12b turns on and off the current passed through the EL elements 15.
Although the examples of the present invention is described by mainly taking the pixel configuration in
Incidentally, the configuration or layout of the gate driver circuit 12 described below is not limited to self-luminous devices such as organic EL display panels. It can also be used for liquid crystal display panels, electromagnetic display panels, etc. For example, liquid crystal display panels may employ the configuration or arrangement of the gate driver circuit 12 according to the present invention to control pixels' selection switching elements. If two gate driver circuits 12 are used, one of them may be used to select pixels' switching elements and the other may be connected to one terminal of a retention capacitance in each pixel. This scheme is referred to as independent CC driving. Needless to say, the configurations described with reference to
Preferably, the gate driver circuit 12 described here is implemented or adopted as the gate driver circuits 12 described earlier with reference to
As illustrated in
Since only P-channel transistors are used for the gate driver circuits 12 here, no level shifter circuit (circuit used to convert a low voltage logic signal into a high voltage logic signal) can be incorporated into the gate driver circuits. Thus, the level shifter circuit is placed or formed in the power supply circuit (IC) 1091 shown in
The power supply circuit (IC) 1091 generates voltages of potentials needed for a turn-on voltage (selection voltage of pixel 16 transistors) and turn-off voltage (non-selection voltage of pixel 16 transistors) to be output from the gate driver circuits 12 to the gate signal lines 17. Consequently, semiconductor processes for the power supply IC (circuit) 1091 have sufficient voltage resistance. Thus, the logic signals can be level-shifted (LS) conveniently by the power supply IC 1091. For this reason, gate driver circuit 12 control signals outputted from a controller (not shown) are fed into the power supply IC 1091 and level-shifted there before it is fed into the gate driver circuits 12 according to the present invention. Source driver circuit 14 control signals outputted from the controller (not shown) are fed into the source driver circuit 14 and the like according to the present invention directly (there is no need for level shifting).
However, the present invention does not limit all the transistors formed on the array board 71 to P-channel transistors. By using only P-channel transistors for the gate driver circuits 12 as described later with reference to
Also, if the pixels 16 are constructed of P-channel transistors, they will match well with the gate driver circuits 12 which employ P-channel transistors. The P-channel transistors (the selection transistors 11b and 11c and transistor 11d in the configuration in
Also, by using P-channel for the driver transistors (transistor 11a in
In this sense, the level shifter (LS) circuit maybe formed directly on the array board 71. That is, N-channel and P-channel transistors are used for the level shifter (LS) circuit. A logic signal from a controller (not shown) is boosted by the level shifter circuit formed directly on the array board 71 so that it will match the logic level of the gate driver circuits 12 constructed from a P-channel transistor. The boosted logic voltage is applied to the gate driver circuits 12.
Incidentally, the level shifter circuit may be constructed from a semiconductor chip and mounted on the array board 71 using COG technology or the like. Also, the source driver circuit 14 is constructed basically from a semiconductor chip and mounted on the array board 71 using COG technology, as illustrated in
Thus, if the driver transistors 11a of the pixels 16 (in the case of
Incidentally, for ease of explanation, the pixel configuration in
The configuration in which P-channel transistors are used as selection transistors of pixels 16 and for gate driver circuits is not limited to organic EL or other self-luminous devices (display panels or display apparatus). For example, it is also applicable to liquid crystal display panels and FEDs (field emission displays).
The inverting terminals (DIRA and DIRB) apply common signals to all the unit gate output circuits 1111. As can be seen from an equivalent circuit diagram in
Incidentally, the circuit configuration in
The clock signals (SCK0, SCK1, SCK2, and SCK3) are fed differently between adjacent unit gate output circuits 1111. For example, in the unit gate output circuit 1111a, OC is fed by the clock terminal SCK0 while RST is fed by the clock terminal SCK2. This is also the case with the unit gate output circuit 1111c. However, in the unit gate output circuit 1111b (the unit gate output circuit in the next stage) adjacent to the unit gate output circuit 1111a, OC is fed by the clock terminal SCK1 while RST is fed by the clock terminal SCK3. In this way, every other unit gate output circuit 1111 is fed by clock terminals in a different manner: OC is fed by SCK0 and RST is fed by SCK2, OC is fed by SCK1 and RST is fed by SCK3 in the next stage, OC is fed by SCK0 and RST is fed by SCK2 in the next stage, and so on.
When driver circuits are built solely of P-channel transistors, it is basically difficult to maintain the gate signal lines 17 at an H level (Vd voltage in
In the circuit configuration in
In the selection-side gate driver circuit 12a,
Incidentally, although 115(b) shows a mode in which adjacent rows of pixels 16 are selected as shown in
Operation of the selection-side gate driver circuit 12a is shown in
As illustrated in
A common anode line 962 is formed or placed on the output side of the source driver IC 14. Anode wires 952 branch off from the common anode line 962. There are 528 (=176×RGB) anode wires 952 in a QCIF panel. The voltage Vdd (anode voltage) illustrated in
To reduce voltage drops in the common connection anode lines 961 and anode wires 952, it is recommended to form a common connection anode line 961a on the upper side of the display screen 50, form a common connection anode line 961b on the lower side of the display screen 50, and short-circuit the anode wires 952 at its top and bottom as illustrated in
It is also preferable to place source driver circuits 14 at the top and bottom of the screen 50 as illustrated in
Anode voltage Vdd has its output voltage adjusted to a resistor 2015b. Vss denotes cathode voltage. One of two voltages can be output selectively as the cathode voltage Vss as illustrated in
The switch 2021 is operated according to output from a temperature sensor 2022. When panel temperature is low, −9(V) is selected as the voltage Vss. When the panel temperature is equal to or higher than a certain level, −6(V) is selected. This is because EL elements 15 have temperature dependence and terminal voltage of the EL elements 15 becomes higher on a low temperature side. Incidentally, although it has been stated with reference to
By allowing a voltage to be selected from a plurality of voltages based on panel temperature as shown in
The turn-off voltage Vgh of the gate driver 12 is set to equal to or higher than the voltage Vdd. Preferably, Vdd+0.5 (V)<Vgh<Vdd+2.5 (V) is satisfied. The turn-on voltage Vgl may be brought to coincide with Vss, but preferably Vss(V)<Vgl<−0.5 (V) is satisfied.
It is important to take measures against heat generation from the EL display panel. As a measure against heat generation, a chassis 2062 made of metal material is mounted on the back of the panel (the side opposite to the illuminating surface of the display screen 50) as illustrated in
Holes 2071 are provided in the back surface of the chassis 2062 as illustrated in
Next, description will be given of examples of display devices according to the present invention which run the drive systems according to the present invention.
The numeric key 572 may be configured to switch among color modes as follows: pressing it once enters 8-color display mode, pressing it again enters 4096-color display mode, and pressing it again enters 260,000-color display mode. The key is a toggle switch which switch among color display modes each time it is pressed. Incidentally, a display color change key may be provided separately. In that case, three (or more) numeric keys 572 are needed.
In addition to a push switch, the numeric key 572 may be a slide switch or other mechanical switch. Speech recognition may also be used for switching. For example, the switch may be configured such that display colors on the display screen 50 of the display panel will change as the user speaks a phrase such as “high-definition display,” “4096-color mode,” or “low-color display mode” into the phone. This can be implemented easily using existing speech recognition technology.
Also, display colors may be switched electrically. It is also possible to employ a touch panel which allows the user to make a selection by touching a menu presented on the display part 21 of the display panel. Besides, display colors may be switched based on the number of times the switch is pressed or based on a rotation or direction as is the case with a click ball.
A key which changes frame rate or a key which switches between moving pictures and still pictures many be used in place of the display color switch key 572. A key may switch two or more items at the same time: for example, among frame rates and between moving pictures and still pictures. Also, the key may be configured to change the frame rate gradually (continuously) when pressed and held. For that, among a capacitor C and a resistor R of an oscillator, the resistor R can be made variable or replaced with an electronic regulator. Alternatively, a trimmer capacitor may be used as a capacitor C of the oscillator. Such a key can also be implemented by forming a plurality of capacitors in a semiconductor chip, selecting one or more capacitors, and connecting the capacitors in parallel.
Furthermore, embodiments which use the EL display panel, EL display apparatus, or drive method according to the present invention will be described with reference to drawings.
Inner surfaces of a casing 573 are dark- or black-colored. This is to prevent stray light emitted from an EL display panel (EL display apparatus) 574 from being reflected diffusely inside the casing 573 and lowering display contrast. A phase plate (λ/4) 108, polarizing plate 109, and the like are placed on an exit side of the display panel. This has also been described with reference to
An eye ring 581 is fitted with a magnifying lens 582. The observer focuses on a display image 50 on the display panel 574 by adjusting the position of the eye ring 581 in the casing 573.
If a convex lens 583 is placed on the exit side of the display panel 574 as required, principal rays entering the magnifying lens 582 can be made to converge. This makes it possible to reduce the diameter of the magnifying lens 1582, and thus reduce the size of the viewfinder.
The EL display panel according to the present invention is also used as a display monitor. The display screen 50 can pivot freely on a point of support 591. The display screen 50 is stored in a storage compartment 593 when not in use.
A switch 594 is a changeover switch or control switch and performs the following functions. The switch 594 is a display mode changeover switch. The switch 594 is also suitable for cell phones and the like. Now the display mode changeover switch 594 will be described.
The drive methods according to the present invention include the one that passes an N times larger current through EL elements 15 to illuminate them for a period equal to 1/M of 1F. By varying this illumination period, it is possible to change brightness digitally. For example, designating that N=4, a four times larger current is passed through the EL elements 15. If the illumination period is 1/M, by switching M among 1, 2, 3, and 4, it is possible to vary brightness from 1 to 4 times. Incidentally, M may be switched among 1, 1.5, 2, 3, 4, 5, 6, and so on.
The switching operation described above is used for cell phones, which display the display screen 50 very brightly at power-on and reduce display brightness after a certain period to save power. It can also be used to allow the user to set a desired brightness. For example, the brightness of the screen is increased greatly outdoors. This is because the screen cannot be seen at all outdoors due to bright surroundings. However, the EL elements 15 deteriorate quickly under conditions of continuous display at high brightness. Thus, the screen 50 is designed to return to normal brightness in a short period of time if it is displayed very brightly. A button which can be pressed to increase display brightness should be provided, in case the user wants to display the screen 50 at high brightness again.
Thus, it is preferable that the user can change display brightness with the switch 594, that the display brightness can be changed automatically according to mode settings, or that the display brightness can be changed automatically by detecting the brightness of extraneous light. Preferably, display brightness settings such as 50%, 60%, 80%, etc. are available to the user.
Preferably, the display screen 50 employs Gaussian display. That is, the center of the display screen 50 is bright and the perimeter is relatively dark. Visually, if the center is bright, the display screen 50 seems to be bright even if the perimeter is dark. According to subjective evaluation, as long as the perimeter is at least 70% as bright as the center, there is not much difference. Even if the brightness of the perimeter is reduced to 50%, there is almost no problem. The self-luminous display panel according to the present invention generates a Gaussian distribution from top to bottom of the screen using the N-fold pulse driving described above (a method which passes an N times larger current through EL elements 15 to illuminate them for a period equal to 1/M of 1F).
Specifically, the value of M is increased in upper and lower parts of the screen and decreased in the center of the screen. This is accomplished by modulating the operating speed of a shift register of the gate driver circuits 12. The brightness at the left and right of the screen is modulated by multiplying video data by table data. By reducing peripheral brightness (at an angle of view of 0.9) to 50% through the above operation, it is possible to reduce power consumption by 20% compared to brightness of 100%. By reducing peripheral brightness (at an angle of view of 0.9) to 70%, it is possible to reduce power consumption by 15% compared to brightness of 100%.
Preferably a changeover switch is provided to enable and disable the Gaussian display. This is because the perimeter of the screen cannot be seen at all outdoors if the Gaussian display is used. Thus, it is preferable that the user can change display brightness with the button switch, that the display brightness can be changed automatically according to mode settings, or that the display brightness can be changed automatically by detecting the brightness of extraneous light. Preferably, display brightness settings such as 50%, 60%, 80%, etc. are available to the user.
Liquid crystal display panels generate a fixed Gaussian distribution using a backlight. Thus, they cannot enable and disable the Gaussian distribution. The capability to enable and disable Gaussian distribution is peculiar to self-luminous display devices.
A fixed frame rate may cause interference with illumination of an indoor fluorescent lamp or the like, resulting in flickering. Specifically, if the EL elements 15 operate on 60-Hz alternating current, a fluorescent lamp illuminating on 60-Hz alternating current may cause subtle interference, making it look as if the screen were flickering slowly. To avoid this situation, the frame rate can be changed. The present invention has a capability to change frame rates. Also, it allows the value of N or M to be changed in N-fold pulse driving (a method which passes an N times larger current through EL elements 15 to illuminate them for a period equal to 1/M of 1F).
The above capabilities are implemented byway of the switch 594. The switch 594 switches among the above capabilities when pressed more than once, following a menu on the screen 50.
Incidentally, the above items are not limited to cell phones. Needless to say, they are applicable to television sets, monitors, etc. Also, it is preferable to provide icons on the display screen to allow the user to know at a glance what display mode he/she is in. The above items similarly apply to the following.
The EL display apparatus and the like according to this embodiment can be applied not only to video cameras, but also to digital cameras such as the one shown in
The display panel described above has a relatively small display area. However, with a display area of 30 inches or larger, the display screen 50 tends to flex. To deal with this situation, the present invention puts the display panel in a frame 611 and attaches a fitting 614 so that the frame 611 can be suspended as shown in
A large screen size increases the weight of the display panel. As a measure against this situation, the display panel is mounted on a stand 613, to which a plurality of legs 612 are attached to support the weight of the display panel.
The legs 612 can be moved from side to side as indicated by A. Also, they can be contracted as indicated by B. Thus, the display apparatus can be installed even in a small space.
A television set in
A space is formed between the protective film and display panel by spraying beads or the like. Fine projections are formed on the rear face of the protective film to maintain the space between the protective film and display panel. The space prevents impacts from being transmitted from the protective film to the display panel.
Also, it is useful to inject an optical coupling agent into the space between the protective film and display panel. The optical coupling agent may be a liquid such as alcohol or ethylene glycol, a gel such as acrylic resin, or a solid resin such as epoxy. The optical coupling agent can prevent interfacial reflection and function as a cushioning material.
The protective film may be, for example, a polycarbonate film (plate), polypropylene film (plate), acrylic film (plate), polyester film (plate), PVA film (plate), etc. Besides, it goes without saying that an engineering resin film (ABS, etc.) may be used. Also, it may be made of an inorganic material such as tempered glass. Instead of using a protective film, the surface of the display panel may be coated with epoxy resin, phenolic resin, and acrylic resin 0.5 mm to 2.0 mm thick (both inclusive) to produce a similar effect. Also, it is useful to emboss surfaces of the resin.
It is also useful to coat surfaces of the protective film or coating material with fluorine. This will make it easy to wipe dirt from the surfaces with a detergent. Also, the protective film may be made thick and used for a front light as well as for the screen surface.
The display panel according to the example of the present invention may be used in combination with the three-side free configuration. The three-side free configuration is useful especially when pixels are built using amorphous silicon technology. Also, in the case of panels formed using amorphous silicon technology, since it is difficult to control variations in the characteristics of transistor elements during production processes, it is preferable to use the N-pulse driving, reset driving, dummy pixel driving, or the like according to the present invention. That is, the transistors according to the present invention are not limited to those produced by polysilicon technology, and they may be produced by amorphous silicon technology.
Incidentally, the N-fold pulse driving (
The duty cycle control driving, reference current control, N-fold pulse driving, and other drive methods and drive circuits according to the present invention described herein are not limited to drive methods and drive circuits for organic EL display panels. Needless to say they are also applicable to other displays such as field emission displays (FEDS) as shown in
In an FED shown in
The pixel configuration in
The technical idea described in the example of the present invention can be applied to video cameras, projectors, 3D television sets, projection television sets, etc. It can also be applied to viewfinders, cell phone monitors, PHS, personal digital assistants and their monitors, and digital cameras and their monitors.
Also, the technical idea is applicable to electrophotographic systems, head-mounted displays, direct view monitors, notebook personal computers, video cameras, electronic still cameras. Also, it is applicable to ATM monitors, publicphones, videophones, personal computers, and wristwatches and its displays.
Furthermore, it goes without saying that the technical idea can be applied to display monitors of household appliances, pocket game machines and their monitors, backlights for display panels, or illuminating devices for home or commercial use. Preferably, illuminating devices are configured such that color temperature can be varied. Color temperature can be changed by forming RGB pixels in stripes or in dot matrix and adjusting currents passed through them. Also, the technical idea can be applied to display apparatus for advertisements or posters, RGB traffic lights, alarm lights, etc.
Also, organic EL display panels are useful as light sources for scanners. An image is read with light directed to an object using an RGB dot matrix as a light source. Needless to say, the light may be monochromatic. Besides, the matrix is not limited to an active matrix and may be a simple matrix. The use of adjustable color temperature will improve imaging accuracy.
Also, organic EL display panels are useful as backlights of liquid crystal display panels. Color temperature can be changed and brightness can be adjusted easily by forming RGB pixels of an EL display panel (backlight) in stripes or in dot matrix and adjusting currents passed through them. Besides, the organic EL display panel, which provides a surface light source, makes it easy to generate Gaussian distribution that makes the center of the screen brighter and perimeter of the screen darker. Also, organic EL display panels are useful as backlights of field-sequential liquid crystal display panels which scan with R, G, and B lights in turns. Also, they can be used as backlights of liquid crystal display panels for movie display by inserting black even if the backlights are turned on and off.
INDUSTRIAL APPLICABILITYThe source driver circuit of the present invention, in which transistors composing a current mirror are formed adjacent to each other, can reduce variations in output current caused by deviations in thresholds. Thus, it can reduce brightness irregularities of an EL display panel and has great practical effect.
Also, the display panels, display apparatus, etc. of the present invention offer distinctive effects, including high quality, high movie display performance, low power consumption, low costs, high brightness, etc., according to their respective configurations.
Incidentally, the present invention does not consume much power because it can provide power-saving information display apparatus. Also, it does not waste resources because it can reduce size and weight. Furthermore, it can adequately support high-resolution display panels. Thus, the present invention is friendly to both global environmental and space environment.
Claims
1. A driver circuit for an EL display panel comprising:
- reference current generating means of generating a reference current;
- a first current source which is fed the reference current from the reference current generating means and outputs a first current which corresponds to the reference current to a plurality of second current sources;
- the second current sources which are fed the first current outputted from the first current source and output a second current which corresponds to the first current to a plurality of third current sources; and
- the third current sources which are fed the second current outputted from the second current sources and output a third current which corresponds to the second current to a plurality of fourth current sources,
- characterize in that among the fourth current sources, an appropriate number of unit current sources are selected according to input image data.
2. A driver circuit for an EL display panel comprising:
- a plurality of current generator circuits each of which includes unit transistors equal in number to a power of two;
- switch circuits connected to the respective current generator circuits;
- internal wiring connected to output terminals; and
- a control circuit configured to turn on and off the switch circuits according to input data,
- wherein a first end of each switch circuit is connected to the current generator circuit and a second end of each switch circuit is connected to the internal wiring.
3. The driver circuit for an EL display panel according to claim 2, wherein:
- channel width W of the unit transistors is from 2 to 9 μm both inclusive, and
- size (WL) of the transistors is 4 square μm or more.
4. The driver circuit for an EL display panel according to claim 2, wherein:
- a ratio of channel length L to channel width W of the unit transistors is two or larger; and
- power supply voltage used is between 2.5 V and 9 V both inclusive.
5. A driver circuit for an EL display panel comprising:
- a first output current circuit including a plurality of unit transistors configured to pass a first unit current;
- a second output current circuit including a plurality of unit transistors configured to pass a second unit current; and
- an output stage configured to produce an output by adding an output current of the first output current circuit and an output current of the second output current circuit,
- wherein the first unit current is smaller than the second unit current,
- the first output current circuit operates in a low gradation region and a high gradation region according to gradations, and
- the second output current circuit operates in the high gradation region according to gradations, and output current values of the first output current circuit do not change in the high gradation region when the second output current circuit operates.
6. A driver circuit for an EL display panel comprising:
- a programming current generator circuit including a plurality of unit transistors corresponding to output terminals;
- first transistors configured to generate a first reference current that defines a current flowing through the unit transistors;
- gate wiring connected to gate terminals of the plurality of first transistors; and
- second and third transistors whose gate terminals are connected to the gate wiring and that form current mirror circuits in conjunction with the first transistors,
- wherein a second reference current is supplied to the second and third transistors.
7. The driver circuit for an EL display panel according to claim 6, further comprising:
- a programming current generator circuit including a plurality of unit transistors corresponding to output terminals;
- a plurality of first transistors configured to form current mirror circuits in conjunction with the unit transistors; and
- a second transistor configured to generate a reference current flowing through the first transistors,
- wherein the reference current generated by the second transistor branches through the plurality of first transistors.
8. The driver circuit for an EL display panel according to claim 6, wherein in a driver IC chip which includes the driver circuit, the third transistor is electrically connected, in an area in which the first reference current supply wirings are placed, to two outermost placed wirings of the reference current supply wiring group placed in the area.
9. The driver circuit for an EL display panel according to claim 7, wherein in a driver IC chip which includes the driver circuit, the third transistor is electrically connected, in an area in which the first reference current supply wirings are placed, to two outermost placed wirings of the reference current supply wiring group placed in the area.
10. An EL display apparatus comprising:
- a first substrate on which driver transistors are placed in a matrix and that contains a display area including EL elements formed corresponding to the driver transistors;
- a source driver IC configured to apply a programming current or voltage to the driver transistors;
- a first wiring formed on the first substrate located under the source driver IC;
- a second wiring electrically connected to the first wiring and formed between the source driver IC and the display area; and
- an anode wiring that branches from the second wiring and applies an anode voltage to pixels in the display area.
11. The EL display apparatus according to claim 10, wherein the first wiring has a light shielding function.
12. An EL display apparatus comprising:
- a display area in which pixels with EL elements are formed in a matrix;
- driver transistors configured to supply light-emitting current to the EL elements; and
- a source driver circuit configured to supply programming current to the driver transistors,
- wherein the driver transistors are P-channel transistors, and
- transistors that generate the programming current in the source driver circuit are N-channel transistors.
13. An EL display apparatus comprising:
- a display area in which EL elements, driver transistors configured to supply light-emitting current to the EL elements, first switching elements configured to form paths between the driver transistors and the EL elements, and second switching elements configured to form paths between the driver transistors and source signal lines are formed in a matrix;
- a first gate driver circuit configured to perform on/off control of the first switching elements;
- a second gate driver circuit configured to perform on/off control of the second switching elements; and
- a source driver circuit configured to supply programming current to the driver transistors,
- wherein the driver transistors are P-channel transistors, and
- transistors that generate the programming current in the source driver circuit are N-channel transistors.
14. An EL display apparatus comprising:
- EL elements;
- P-channel driver transistors configured to supply light-emitting current to the EL elements;
- switching transistors formed between the EL elements and the driver transistors;
- a source driver circuit configured to supply programming current; and
- gate driver circuits configured to keep the switching transistors off for two horizontal scanning periods or longer in one frame period.
Type: Application
Filed: Mar 5, 2003
Publication Date: Aug 18, 2005
Applicant: Toshiba Matsushita Display Technology Co., ltd. (Tokyo)
Inventors: Hiroshi Takahara (Osaka), Hitoshi Tsuge (Osaka)
Application Number: 10/511,448
