Semiconductor structures and manufacturing methods

Abstract

A method of making a semiconductor device includes forming an alignment mark in a semiconductor wafer. The alignment mark includes a fist set of parallel lines and a second set of parallel lines. The parallel lines in the first set overlie and cross the parallel lines in the second set. The alignment mark can be used to determine a location of the semiconductor wafer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 09/733,665, filed on Dec. 8, 2000, which is divisional of the U.S. patent application Ser. No. 09/362,976, filed on Jul. 28, 1999, now abandoned, which applications are hereby incorporated herein by reference.

TECHNICAL FIELD

This invention relates generally to semiconductor structures and manufacturing methods and more particularly to alignment techniques used therein.

BACKGROUND

As is known in the art, semiconductor integrated circuits are manufactured using a series of process steps that require proper alignment of the semiconductor wafer. Many alignment systems use reflected light from profile patterns formed on the surface of the semiconductor wafer to determine the location of the wafer. Such an arrangement is shown in FIG. 1. An alignment illumination 10, here a cross, is focused onto the surface 12 of the semiconductor wafer 14 using an optical system 16. A portion of the light reflected from the surface of the semiconductor wafer is directed by the optical system 16 to a detector arrangement 20. The wafer 14 has formed along one portion thereof an alignment mark 22, here shown diagrammatically as a series of grooves 24 etched into the surface 12 of the wafer 14. As the wafer 14 is scanned horizontally, the detector arrangement 20 produces waveforms, which enable detection of the alignment of the wafer 14 relative to the optical system 16.

More particularly, and referring also to FIG. 2, there are shown four sites, i.e., site 1, site 2, site 3 and site 4, of alignment marks on each of both the upper and lower peripheral portions of a semiconductor wafer 14. Each one of the sites includes two sets of lines 13, one at +45 degrees with respect to the vertical, or Y axis, and the other set of lines 15 being at −45 degrees with respect to the Y axis. The alignment illumination projected by the optical system (FIG. 1) onto the surface of the wafer is a cross, such as used in the MICRASCAN equipment manufactured by Silicon Valley Group (SVG), San Jose, Calif. A “standard” alignment mark, in one half of a site, for the MICRASCAN III equipment is shown in FIG. 3 and consists of wide stripes at a 45 degree angle separated by variable spacing. Another version is shown in FIG. 4 and is made up of lines at the locations where the “standard” mark has the edges of its stripes. The size of both versions is 60×60 micrometers. The alignment marks etched into the surface of the wafer are shown in FIG. 2 as a pair orthogonal sets of a series of parallel lines, only one of the two sets being shown in FIGS. 3 and 4.

Referring again to FIG. 1, the alignment illumination is a cross that is projected onto the surface 12 of wafer 14 with the pair of intersecting arms of the cross being disposed nominally orthogonal to the lines in each of the sites. The cross-shaped light (i.e., the alignment illumination) is projected by the optical system 16 onto, and scanned across, the site (FIG. 2) along the X direction indicated on the surface 12 of the wafer 14. The optical system 16 includes a prism (FIG. 1) that directs a portion of the light reflected surface 12 of the wafer 14 onto a detector arrangement 20 shown diagrammatically in FIG. 1. Thus, as indicated, there are four detectors 22₁, 22₂, 22₃, and 22₄; one pair 22₁ and 22₂ being disposed along an axis +45 degrees with respect to the Y axis and one pair 22₃ and 22₄ being disposed along an axis −45 degrees with respect to the Y axis. The pair of detectors 22₁ (i.e., “Left +45”) and 22₂ (i.e., “Right +45”) is used for detection of light reflected by lines 13 at +45 degrees with respect to the Y axis and the pair of detectors 222₃ (i.e., “Left −45”) and 22₄ (i.e., “Right −45”) are used to detect light reflected by lines 15 at −45 degrees with respect to the Y axis.

More particularly, to determine the location of an alignment site, two marks 13, 15 (FIG. 2), one oriented at +45 degrees and one at −45 degrees with respect to the Y axis, are required. The alignment marks 13, 15 are scanned by the optical system with an X shaped illumination, as described above. The light reflected from the surface of the wafer and the alignment lines is detected in the dark field mode, i.e., only light scattered from the marks at an angle is analyzed. Two detectors 22₁ and 22₂ record simultaneously the reflected light; one detector 22₂ located to the right side and one detector 22₁ to the left side of the mark's edge. When scanning the +45 degree lines 13, the set of detectors 22₁ and 22₂ is activated and when the −45 degree lines 15 are scanned, the set of detectors 22₃, 22₄ are activated. More particularly, referring to FIG. 1, when the alignment illumination is over the +45 degree lines 13 of site 1, the “Left +45” and “Right +45” detectors 22₁ and 22₂ are activated and the “Left −45” and “Right −45” detectors 22₃ and 22₄, are deactivated. When the alignment illumination moves over the −45 degree lines 15 of site 1, the “Left −45” and “Right −45” detectors 22₃ and 22₄ are activated and the “Left +45” and “Right +45” detectors 22₁ and 22₂ are deactivated. It is noted that with such an arrangement, each alignment site is made up of a pair of spatially separated sets 13, 15 of parallel orthogonal lines with two sets in the site being sequentially activated/deactivated detectors. Such spatial separation increases the area required for an alignment site.

SUMMARY OF THE INVENTION

In accordance with the present invention, a semiconductor body is provided having an alignment mark comprising a pair of sets of parallel lines disposed on the semiconductor body. The parallel lines in one of the sets are disposed orthogonal to the parallel lines in the other one of the set. The two sets of parallel lines are in an overlaying relationship.

With such structure, the same amount of wafer surface area enables twice as many alignment sites. Thus, the arrangement allows the alignment system to acquire twice the amount of metrology information during the same alignment scanning process to thereby increase the alignment quality. Further, there is no loss of through-put because the same time is used for scanning the sites as in the system described above.

In accordance with another embodiment, a method is provided for detecting an alignment mark on a semiconductor body. The method includes providing the alignment mark on the semiconductor body. This alignment mark includes a pair of sets of parallel lines disposed on the semiconductor body. The parallel lines in one of the sets are disposed orthogonal to the parallel lines in the other one of the set and the two sets of parallel lines are in an overlaying relationship. The alignment illumination includes a pair of orthogonal, lines of impinging light that is scanned over the surface of the alignment mark. One of such pair of impinging light lines is orthogonal to, and laterally displaced from, the other one of such pair of impinging light lines. Impinging light is reflected by the alignment lines in the surface of the semiconductor when such impinging light is over to provide a pair of laterally displaced beams of reflected light. The method includes detecting in each one of a pair of laterally spaced detectors a corresponding one of the laterally displaced beams of reflected light.

In accordance with another embodiment of the invention an apparatus is provided for detecting an alignment mark on a semiconductor body. The alignment mark comprises a pair of sets of parallel lines disposed on the semiconductor body. The parallel lines in one of the sets are disposed orthogonal to the parallel lines in the other one of the set and the two sets of parallel lines are in an overlaying relationship. The apparatus includes an optical system for scanning an alignment illumination that provides a pair of orthogonal, lines of impinging light over the surface of the alignment mark. One of such pair of impinging light lines is orthogonal to, and laterally displaced from, the other one of such pair of impinging light lines. Impinging light is reflected by the alignment lines in the surface of the semiconductor when such impinging light is over to provide a pair of laterally displaced beams of reflected light. The apparatus also includes a pair of laterally spaced detectors, each being positioned to detect a corresponding one of the laterally displaced beams of reflected light.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the invention will become more readily apparent from the following detailed description when read together with the accompanying drawings, in which:

FIG. 1 is schematic diagram of an alignment system according to the prior art;

FIG. 2 is a plan view of a semiconductor wafer having alignment marks according to the prior art etched into such surface;

FIGS. 3 and 4 are sketches of alignment marks according to the prior art;

FIG. 5 is a plan view of a semiconductor wafer having alignment marks according to the invention etched into such surface;

FIGS. 6 and 7 are sketches of alignment marks according to the invention; and

FIG. 8 is schematic diagram of an alignment system according to the invention, such system being adapted for use with a semiconductor wafer having the alignment marks shown in either FIG. 6 or FIG. 7.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Referring now to FIG. 5, a portion of a semiconductor body 100, here a single crystal silicon body, is shown. The body includes alignment sites. In particular, five sites (i.e., site 1, site 2, site 3, site 4 and site 5) are disposed along the top outer peripheral portion of the wafer and five sites (i.e., site 1, site 2, site 3, site 4, and site 5) along the lower outer peripheral portion. Each one of the sites is identical, an exemplary one thereof being shown in detail in FIG. 6. Another embodiment of one of the sites is shown in FIG. 7. It is noted that the alignment site includes a single, composite alignment mark 102. The alignment mark 102, as noted above, is formed in a portion of the surface 104 of the semiconductor body 102, here as grooves 106. The surface 104 of the semiconductor body 102 is adapted to reflect light energy impinging on such surface with a predetermined wavelength.

More particularly, the semiconductor body 100 has an alignment mark 102 comprising a pair of sets of parallel lines 112, 114 (FIG. 6 or 7) disposed on the semiconductor body 100. The parallel lines 112 in one of the sets are disposed orthogonal to the parallel lines 114 in the other one of the set and the two sets of parallel lines 112, 114 are in an overlaying relationship to provide a composite mark at each one of the sites (FIG. 5).

An apparatus 200 shown in FIG. 8, is provided for detecting the alignment mark 102 (FIG. 6) on a semiconductor body 110. As noted above, the alignment mark 100 comprises a pair of sets of parallel lines 112, 114 (FIG. 6) disposed on the semiconductor body 100. The parallel lines 112, 114 in one of the sets are disposed orthogonal to the parallel lines 112, 114 in the other one of the sets. The alignment mark 102 includes, as noted above, grooves 106 having sidewalls 108 terminating at the surface 104 of the semiconductor body 100, as indicated in FIG. 8. The grooves 106 have bottom portions 110 recessed into the surface portion of the semiconductor body 100. The two sets of parallel lines 112, 114 are in an overlaying relationship.

The apparatus 200 includes an optical system 202 for scanning an alignment illumination 204, which comprises a pair of orthogonal, laterally displaced along the X axis lines 208, 210 of impinging light over the surface of the alignment mark 102. One of the pair of impinging light lines, here line 208, is orthogonal to, and laterally displaced from, the other one of such pair of impinging light lines 210. Here, the line 210 is projected onto the surface of the wafer 100 at an angle of −45 degrees with respect to the Y axis (FIG. 5) and the line 208 is projected onto the surface of the wafer 100 at an angle of +45 degrees with respect to the Y axis (FIG. 5). The impinging light (i.e., the alignment illumination) is reflected by the surface of the semiconductor body 100 when such impinging light is over the composite alignment mark 102 to provide a corresponding pair of laterally displaced beams 211, 213 of reflected light.

The apparatus includes a detector arrangement 220. The detector arrangement 220 includes a pair of detectors configurations 220₁ and 220₂. The projected beams 211, 213 are directed by the optical system 200 to the detector configurations 220₁ and 220₂, respectively, as indicated. The detector configuration 220₁ includes a pair of detectors 222₁ and 222₂, shown in FIG. 8. Shown diagrammatically with the detectors 222₁ and 222₂ is the projection of the illumination 210 (i.e., 210′) if the surface of the wafer 100 were perfectly flat. Thus, detectors 222₁ and 222₂ are positioned to detect energy reflected by lines 112 (FIG. 6).

In like manner, the detector configuration 220₂ includes a pair of detectors 222₃ and 222₄, shown in FIG. 8. Shown diagrammatically with the detectors 222₃ and 222₄ is the projection of the illumination 208 (i.e., 208′) if the surface of the wafer 100 were perfectly flat. Thus, detectors 222₃ and 222₄ are positioned to detect energy reflected by lines 114 (FIG. 6).

With such apparatus, the alignment illumination is scanned over the surface of the alignment mark 102. One pair of impinging light lines 108 is orthogonal to, and laterally displaced from, the other one of such pair of impinging light lines 110. Impinging light is reflected by the alignment lines in the surface of the semiconductor when such impinging light is over to provide a pair of laterally displaced beams 211, 213 lines of reflected light. The detectors 222₁, 222₂, 222₃ and 222₄ detect in each one of a pair of laterally spaced detector configurations 220₁, 220₂, respectively, a corresponding one of the laterally displaced beams 211, 213 of reflected light. The −45 degree and +45 degree oriented alignment lines 208, 210, respectively, of the cross-shaped alignment illumination 204 are separated locally by at least the width W (FIGS. 6 and 8) of the alignment mark 102. This will result in the alignment mark being scanned first by the +45 degree line 208 and subsequently by the −45 degree line 210. This arrangement allows the separation of the alignment detectors 222₁, 222₂ and 222₃, 222₄ for +45 degree and −45 degree orientations, respectively. As a result, each signal, or waveform, produced by the detectors can be recorded without background noise from the other line orientation.

Other embodiments are within the spirit and scope of the appended claims. For example, other types of composite alignment marks may be used such as shown in FIG. 7.

Claims

1. A method of making a semiconductor device, the method comprising:

providing a semiconductor wafer; and

forming an alignment mark in the semiconductor wafer, the alignment mark comprising a first set of parallel lines and a second set of parallel lines, the parallel lines in the first set overlying and crossing the parallel lines in the second set.

2. The method of claim 1 wherein the parallel lines in the first set are aligned orthogonally relative to the parallel lines in the second set.

3. The method of claim 1 wherein both the first set and the second set of parallel lines includes more than, three parallel lines.

4. The method of claim 1 and further comprising using the alignment mark to determine a location of the semiconductor wafer.

5. The method of claim 4 wherein using the alignment mark to determine a location of the semiconductor wafer comprises reflecting energy with a predetermined wavelength from a surface of the semiconductor wafer.

6. The method of claim 4 wherein using the alignment mark to determine a location of the semiconductor wafer comprises:

simultaneously directing a first beam of light and a second beam of light toward the semiconductor wafer, the first beam of light being spaced from the second beam of light;

receiving the first beam of light after the first beam of light has been reflected from the semiconductor wafer; and

receiving the second beam of light after the second beam of light has been reflected from the semiconductor wafer.

7. The method of claim 6 wherein the first beam of light comprises a first line of light and wherein the second beam of light comprises a second line of light, the first line of light being orthogonal to the second light of line.

8. The method of claim 7 wherein the parallel lines in the first set are aligned orthogonally relative to the parallel lines in the second set.

9. The method of claim 6 wherein the first beam of light is received at a first detector and the second beam of light is received at a second detector.

10. The method of claim 1 wherein the semiconductor wafer comprises a semiconductor body of single crystal silicon, and wherein forming an alignment mark comprises etching grooves into the semiconductor body.

11. The method of claim 1 wherein forming an alignment mark comprises forming a plurality of alignment marks.

12. The method of claim 11 wherein the plurality of alignment marks are formed along a line, the method further comprising simultaneously directing a first beam of light and a second beam of light toward the semiconductor wafer, the first beam of light being spaced from the second beam of light.

13. A method of making a semiconductor device, the method comprising:

providing a semiconductor wafer; and

forming an alignment mark in the semiconductor wafer, the alignment mark comprising a first set of parallel lines and a second set of parallel lines, the parallel lines in the first set overlying and crossing the parallel lines in the second set;

using the alignment mark to align the semiconductor wafer; and

performing a process step to form an integrated circuit in the semiconductor wafer.

14. The method of claim 13 wherein the parallel lines in the first set are aligned orthogonally relative to the parallel lines in the second set.

15. The method of claim 13 and further comprising using the alignment mark to determine a location of the semiconductor wafer.

16. The method of claim 15 wherein using the alignment mark to determine a location of the semiconductor wafer comprises reflecting energy with a predetermined wavelength from a surface of the semiconductor wafer.

17. The method of claim 15 wherein using the alignment mark to determine a location of the semiconductor wafer comprises:

simultaneously directing a first beam of light and a second beam of light toward the semiconductor wafer, the first beam of light being spaced from the second beam of light;

receiving the first beam of light after the first beam of light has been reflected from the semiconductor wafer; and

receiving the second beam of light after the second beam of light has been reflected from the semiconductor wafer.

18. The method of claim 17 wherein the first beam of light comprises a first line of light and wherein the second beam of light comprises a second line of light, the first line of light being orthogonal to the second line of light.

19. The method of claim 13 wherein the semiconductor wafer comprises a semiconductor body of single crystal silicon, and wherein forming an alignment mark comprises etching grooves into the semiconductor body.

20. The method of claim 19 wherein forming an alignment mark comprises forming a plurality of alignment marks, each of the alignment marks comprising a first set of parallel grooves and a second set of parallel grooves, the parallel grooves in the first set overlying and crossing the parallel grooves in the second set.