Concentric or nested container capacitor structure for integrated cicuits
Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.
This invention relates to the structure and fabrication of concentric or nested capacitors for integrated circuits, and specifically in one embodiment to the use of such capacitors in dynamic random access memory (DRAM) cells.
BACKGROUND Container capacitors are well known in the art of semiconductor processing, and are particularly well known as a capacitor structure used in dynamic random access memories (DRAMs). A basic DRAM cell is schematically shown in
The container capacitors 18 are generally formed by etching a hole in the dielectric 22 (typically, a silicon dioxide or “oxide”) that overcoats the word lines 14 to expose plugs 17. This hole may extend over the word lines 14, but this is not shown for simplicity. A first layer of polysilicon (or “poly”) 19 is deposited within the hole and planarized or patterned to form a “U” shape in cross section, and which in three dimensions would resemble a “cup” or a “box” with an open top. The capacitor dielectric 21 (e.g., oxide, silicon nitride (“nitride”), silicon oxynitride (“oxynitride”), or any combination of these) is formed, and the second layer of poly 20 is deposited. After these processing steps, the original hole in the dielectric 22 may be completely filled by the poly 20, or may subsequently be intentionally filled by another dielectric layer (not shown).
A container capacitor 18 helps to increase the density of the cells in a DRAM because the capacitors are three-dimensional rather than planar, hence allowing a larger area capacitor in a smaller two-dimensional “footprint” on the silicon 10. However, as fabrication technologies advance, and as structures are made of smaller dimensions and at higher densities, the capacitors 18 can be affected. Smaller capacitor sizes equate to lower capacitances, and hence lower amounts of charge the capacitor can store. Accordingly, and again as a general matter, the sizes of the capacitors in DRAM cell are formed relatively large when compared to other structures of the cell to achieve a suitable capacitance. (Of course, other parameters such as dielectric thickness and dielectric constant also affect capacitance). But relatively large capacitors are disadvantageous to the density and/or area of the overall cell. Attempts to make suitably capacitive container capacitors larger by making them narrower but deeper can be difficult to pattern and etch, and require lithography alignments that can be difficult to achieve. As such, container capacitors can constitute a limiting factor in DRAM cell design. Thus, the art would be benefited by an improved design for such container capacitors, and specifically would be benefited by container capacitor structures that provide suitable capacitances, are easy to fabricate, do not require leading-edge line width processing and alignment, and which take up a limited two-dimensional footprint relative to the silicon substrate. This disclosure presents solutions.
SUMMARYDisclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested container capacitor structure can in one embodiment be used as the capacitors for two DRAM cells, which takes up less space than would individually-formed container capacitors and are easier to fabricate. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back polysilicon (poly 1) to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is then formed on the poly 1, and a second layer of polysilicon (poly 2) is deposited over the sidewall to form an inner capacitor plate in contact with the other plug. The structure is planarized and the sacrificial sidewalls are removed. A capacitor dielectric is formed, and is topped with a cell plate polysilicon layer (poly 3). Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used, which provide design flexibility and add process margin.
BRIEF DESCRIPTION OF THE DRAWINGSEmbodiments of the inventive aspects of this disclosure will be best understood with reference to the following detailed description, when read in conjunction with the accompanying drawings, in which:
Also shown in
Starting with
A hole 60 (roughly corresponding to the container capacitor areas 60 of
After etching the hole 60 and routine cleansing of the exposed surfaces of the plugs 52a, 52b, a first layer of polysilicon (“poly 1”) 64 is deposited, which is preferably followed by the deposition of a titanium nitride (TiN) layer 66, rendering the structure shown in
Thereafter, and as shown in
Note that a portion 65 of the poly 1 64 remains in contact with plug 52a. As will be seen, poly 1 64 will constitute the bottom plate of the outer container capacitor (i.e., for those cells in communication with plugs 52a).
Next, and referring to
Next, the top of the resulting structure is planarized, preferably using Chemical-Mechanical Polishing (CMP), resulting in the structure of
Note that a portion 73 of the poly 2 70 remains in contact with plug 52b. As will be seen, poly 2 70 will constitute the bottom plate of the inner container capacitor (i.e., for those cells in communication with plugs 52b).
The structure of
HF solution is preferable because it will well-clean and prepare the exposed surfaces of the poly 1 64 and poly 2 70 for capacitor dielectric 72 formation, as shown in
As shown, the bottom layer of the outer capacitor (poly 1 64) is primarily proximate to the poly 3 74 along its inner vertical edges, and hence primary establishes a capacitance 71a thereto along this edge. By contrast, the bottom layer of the inner capacitor (poly 2 70) is primarily proximate to the poly 3 74 along its inner and outer vertical edges, and hence primarily establishes a capacitance 71b with respect thereto along these edges. (Additionally, horizontal portions of the poly 1 and poly 2 are also proximate to the poly 3 and hence add to the capacitance, but such additional capacitances are not shown for clarity). Thus, the inner capacitor is in a sense two-sided, whereas the outer capacitor is in a sense one-sided.
In an actual application, it is preferable that the poly 1-to-poly 3 capacitance 71a for outer capacitor and the poly 2-to-poly 3 capacitance 71b for the inner capacitor be equal, so that cells communicating with each of these capacitors will behave similarly from an electrical standpoint. In this regard, the effective surface areas of each of the inner and outer capacitors should be roughly equated, with attention paid to additional capacitive effects due to coupling along non-vertical surfaces. Equating the capacitance between the inner and outer capacitors is not difficult: while the inner capacitor takes up a smaller footprint than does the outer capacitor, it is also two-sided which increases its effective area and capacitance. In any event, should capacitances need adjustment to bring them into parity, the thickness of the TiN 66 and dielectric 68 sidewalls can be tailored to change the effective area of the inner capacitor relative to the outer capacitor.
The disclosed nested container capacitor structure provides many benefits over non-nested container capacitors traditionally used as the capacitors in a DRAM cell. For the most part, the nested structure is self aligned and requires minimal photolithography steps. The only significant alignment step is the pattern and etch step used to form the hole 60 (
Modifications to the basic process disclosed above are possible. For example,
Thereafter, and referring to
Using any of these etching schemes, the nitride 80 will be removed (as shown in dotted lines 80b), thus exposing at least some portion of plug 52b. Because the nitride layer 80 completely covers plug 52b, there is no chance that the poly 1 64 can short to it, which constitutes the primary advantage of this embodiment. Thereafter, poly 2 70 can be deposited, and processing can continue as shown in FIGS. 7 to 10.
Although the hole 60 (see
In another modification, the disclosed nested capacitor container technique can be used even if one of the plugs 52a or 52b are wholly or partially outside of the hole 60, as is shown in
Because the etch chemistries introduced earlier will etch both poly and TiN simultaneously, either of these etch back processes will also clear the conductive layer 90 where it is exposed during etch back, i.e., in regions 90a. It is possible that some amount of poly 1 64 and/or TiN 66 may remain along the edges of the conductive layer 90 during etch back, but this is not problematic as the residuals can be overetched to remove them, or because such residuals would not cause a risk of shorting the poly 1 to the poly 2. In any event, if the poly 1 and TiN 66 are etched back simultaneously (
In another modification, both a protective layer 80 and a conductive layer 90 can be used in conjunction, as shown initially in
In the foregoing embodiments employing the use of protective layers 80 or conductive layers 90, it should be understood that definition of each of these layers requires an additional patterning and etching step, but such additional processing may in some embodiments be sensible to undertake for the benefits they provide, such as added flexibility in designing the cell, provision of extra processing alignment margin, etc. However, in an embodiment in which both a protective layer 80 and conductive layer 90 are used, only one patterning step need be used, as shown in
Next, poly 1 64 is deposited and etched back to form sidewalls, as shown in
In another modification, either of the inner or outer container capacitors, or both, can themselves be formed with a nested structure. This is shown in
In another modification, the disclosed techniques can be used to form more than two nested capacitors. Referring to
Although the disclosed embodiments have to this point all contemplated a common plate layer (e.g., poly 3 74 in
While the disclosed nested container capacitor solutions were developed primarily with the manufacture of DRAM cells in mind, one skilled in the art will appreciate that capacitors have many uses in electronics, and hence that the disclosed solutions can have applicability to other types of integrated circuits.
Although the disclosed capacitor structure is shown as being particularly useful for coupling the capacitors to plugs 52a, 52b, the nested capacitors can be connected to other types of nodes or contacts as well, such as diffusion regions, metallic lines, etc.
It should be understood that the inventive concepts disclosed herein are capable of many modifications. To the extent such modifications fall within the scope of the appended claims and their equivalents, they are intended to be covered by this patent.
Claims
1. A capacitor structure for an integrated circuit, comprising:
- a first capacitor formed on the integrated circuit and having first and second plates, wherein the first plate of the first capacitor is in contact with a first node; and
- a second capacitor nested within the first capacitor on the integrated circuit and having first and second plates, wherein the first plate of the second capacitor is in contact with a second node electrically isolated from the first node.
2. The capacitor structure of claim 1, further comprising a common plate, wherein the common plate comprises a second plate of the first and second capacitors.
3. The capacitor structure of claim 1, wherein each plate comprises a layer of deposited material.
4. The capacitor structure of claim 1, wherein the layers constitute polysilicon.
5. The capacitor structure of claim 1, wherein the first node is coupled to a source or drain region of a first access transistor, and wherein the second node is coupled to a source or drain region of a second access transistor.
6. The capacitor structure of claim 1, wherein a common dielectric layer intervenes between the first and second plates of each capacitor.
7. The capacitor structure of claim 1, wherein the first and second capacitors are concentric.
8. The capacitor structure of claim 1, wherein the first plates of the first and second capacitors comprise substantially vertical portions.
9. The capacitor structure of claim 8, wherein the substantially vertical portions of the first plate of the first capacitor are nested within the substantially vertical portions of first plate of the second capacitor.
10. The capacitor structure of claim 1, wherein the common plate comprises substantially vertical portions.
11. The capacitor structure of claim 1, wherein at least one of the nodes is in contact with one of the first plates via a conductive layer.
12. The capacitor structure of claim 1, wherein at least one of the first plates comprises nested subplates.
13. The capacitor structure of claim 1, wherein the first plates comprise substantially vertical sidewalls.
14. The capacitor structure of claim 1, further comprising a third capacitor nested within the second capacitor on the integrated circuit and having first and second plates, wherein the first plate of the third capacitor is coupled to a third node electrically isolated from the first and second nodes.
15. The capacitor structure of claim 14, wherein common plate comprises a second plate of the first, second, and third capacitors.
16. A capacitor structure for an integrated circuit, comprising:
- a first capacitor plate formed on the integrated circuit;
- a second capacitor plate formed on the integrated circuit within the first capacitor plate; and
- a third capacitor plate, wherein the third capacitor plate is proximate to the first capacitor plates to form a first capacitor, and wherein the third capacitor plate is proximate to the second capacitor plate to form a second capacitor.
17. The capacitor structure of claim 16, wherein each plate comprises a layer of deposited material.
18. The capacitor structure of claim 16, wherein the layers constitute polysilicon.
19. The capacitor structure of claim 16, further comprising a first node in contact with the first capacitor plate, and a second node in contact with the second capacitor plate.
20. The capacitor structure of claim 19, wherein the first node is coupled to a source or drain region of a first access transistor, and wherein the second node is coupled to a source or drain region of a second access transistor.
21. The capacitor structure of claim 19, wherein at least one of the nodes is in contact with one of the first plates via a conductive layer.
22. The capacitor structure of claim 16, wherein a common dielectric layer intervenes between the plates in the first and second capacitors.
23. The capacitor structure of claim 16, wherein the first and second plates are concentric.
24. The capacitor structure of claim 16, wherein the first and second plates comprise substantially vertical portions.
25. The capacitor structure of claim 24, wherein the substantially vertical portions of the second plate are nested within the substantially vertical portions of first plate.
26. The capacitor structure of claim 16, wherein the third plate comprises substantially vertical portions.
27. The capacitor structure of claim 16, wherein at least one of the first or second plates comprises nested subplates.
28. The capacitor structure of claim 16, further comprising a fourth capacitor plate formed on the integrated circuit within the second capacitor plate, and wherein the third capacitor plate is proximate to the fourth capacitor plate to form a third capacitor.
29. The capacitor structure of claim 16, wherein the first and second plates comprise substantially vertical sidewalls.
30. A capacitor structure for an integrated circuit, comprising:
- a first bottom capacitor plate within a hole in the integrated circuit and in contact with a first contact;
- a second bottom capacitor plate within the hole and nested within the first bottom capacitor plate and in contact with a second contact electrically isolated from the first contact; and
- a top capacitor plate over the first and second bottom capacitors plates.
31. The capacitor structure of claim 30, wherein each plate comprises a layer of deposited material.
32. The capacitor structure of claim 30, wherein the layers constitute polysilicon.
33. The capacitor structure of claim 32, wherein the first contact is coupled to a source or drain region of a first access transistor, and wherein the second contact is coupled to a source or drain region of a second access transistor.
34. The capacitor structure of claim 33, wherein at least one of the contacts is in contact with one of the bottom plates via a conductive layer.
35. The capacitor structure of claim 30, wherein a common dielectric layer intervenes between the top plate and each of the bottom plates.
36. The capacitor structure of claim 30, wherein the bottom plates are concentric.
37. The capacitor structure of claim 30, wherein the bottom plates comprise substantially vertical portions.
38. The capacitor structure of claim 37, wherein the substantially vertical portions of first bottom capacitor plate are formed along edges of the hole.
39. The capacitor structure of claim 38, wherein the substantially vertical portions of the second bottom capacitor plate are nested within the substantially vertical portions of first bottom capacitor plate.
40. The capacitor structure of claim 30, wherein the top plate comprises substantially vertical portions.
41. The capacitor structure of claim 30, wherein at least one of the bottom plates comprises nested subplates.
42. The capacitor structure of claim 30, further comprising a third bottom capacitor plate within the hole and nested within the second bottom capacitor plate and in contact with a third contact electrically isolated from the first and second contacts, and wherein the top capacitor plate appears over the third bottom capacitor plate.
43. The capacitor structure of claim 30, wherein the first and second plates comprise substantially vertical sidewalls.
44. The capacitor structure of claim 30, wherein at least one of the contacts appear at partially outside of the hole.
45. The capacitor structure of claim 44, wherein at least one of the contacts appear at completely outside of the hole.
46. A dynamic random access memory, comprising:
- a first access transistor;
- a second access transistor; and
- a capacitor structure formed in an area, comprising: a first capacitor having first and second plates, wherein the first plate of the first capacitor is coupled to the first access transistor, a second capacitor nested within the first capacitor on the integrated circuit and having first and second plates, wherein the first plate of the second capacitor is coupled to the second access transistor, and a common plate, wherein the common plate comprises a second plate of the first and second capacitors.
47. The dynamic random access memory of claim 46, wherein the capacitors are coupled to source or drain regions of the access transistors.
48. The dynamic random access memory of claim 47, wherein the capacitors are coupled to source or drain regions of the access transistors through contacts.
49. The dynamic random access memory of claim 46, wherein at least one of the contacts appear at partially outside of the area.
50. The dynamic random access memory of claim 46, wherein at least one of the contacts appear at completely outside of the area.
51. The dynamic random access memory of claim 46, wherein the common plate is coupled to a reference voltage.
52. The dynamic random access memory of claim 46, wherein a common dielectric layer intervenes between the first and second plates of each capacitor.
53. The dynamic random access memory of claim 46, wherein the first and second capacitors are concentric.
54. The dynamic random access memory of claim 46, wherein the first plates of the first and second capacitors comprise substantially vertical portions.
55. The dynamic random access memory of claim 54, wherein the substantially vertical portions of the first plate of the first capacitor are nested within the substantially vertical portions of first plate of the second capacitor.
56. The dynamic random access memory of claim 46, wherein the common plate comprises substantially vertical portions.
57. The dynamic random access memory of claim 46, wherein at least one of the nodes is in contact with one of the first plates via a conductive layer.
58. The dynamic random access memory of claim 46, wherein at least one of the first plates comprises nested subplates.
59. The dynamic random access memory of claim 46, wherein the first plates comprise substantially vertical sidewalls.
60. A dynamic random access memory, comprising:
- a first access transistor;
- a second access transistor; and
- a capacitor structure formed in an area, comprising: a first capacitor plate coupled to the first access transistor, a second capacitor plate within the first capacitor plate coupled to the second access transistor, and a third capacitor plate, wherein the third capacitor plate is proximate to the first capacitor plates to form a first capacitor, and wherein the third capacitor plate is proximate to the second capacitor plate to form a second capacitor.
61. The dynamic random access memory of claim 60, wherein the plates are coupled to source or drain regions of the access transistors.
62. The dynamic random access memory of claim 61, wherein the plates are coupled to source or drain regions of the access transistors through contacts.
63. The dynamic random access memory of claim 60, wherein at least one of the contacts appear at partially outside of the area.
64. The dynamic random access memory of claim 60, wherein at least one of the contacts appear at completely outside of the area.
65. The dynamic random access memory of claim 60, wherein the third plate is coupled to a reference voltage.
66. The dynamic random access memory of claim 60, wherein a common dielectric layer intervenes between the plates in the first and second capacitors.
67. The dynamic random access memory of claim 60, wherein the first and second plates are concentric.
68. The dynamic random access memory of claim 60, wherein the first and second plates comprise substantially vertical portions.
69. The dynamic random access memory of claim 68, wherein the substantially vertical portions of the second plate are nested within the substantially vertical portions of first plate.
70. The dynamic random access memory of claim 60, wherein the third plate comprises substantially vertical portions.
71. The dynamic random access memory of claim 60, wherein at least one of the first or second plates comprises nested subplates.
72. The dynamic random access memory of claim 60, further comprising a fourth capacitor plate formed on the integrated circuit within the second capacitor plate, and wherein the third capacitor plate is proximate to the fourth capacitor plate to form a third capacitor.
73. The dynamic random access memory of claim 60, wherein the first and second plates comprise substantially vertical sidewalls.
74. A method for forming a capacitor structure for an integrated circuit, comprising:
- forming a hole in a dielectric layer on the integrated circuit to define a capacitor area;
- forming a first bottom capacitor plate within the hole in the integrated circuit and in contact with a first contact;
- forming a second bottom capacitor plate within the hole and nested within the first bottom capacitor plate and in contact with a second contact electrically isolated from the first contact; and
- forming a top capacitor plate over the first and second bottom capacitors plates.
75. The method of claim 74, wherein forming the hole exposes at least one of the first or second contacts.
76. The method of claim 74, wherein the first bottom plate is formed as a sidewall on edges of the hole by etch back processing.
77. The method of claim 76, further comprising forming at least one sidewall on first bottom plate sidewalls.
78. The method of claim 77, wherein the second bottom plate is formed on the at least one sidewall.
79. The method of claim 78, further comprising planarizing the second bottom plate to expose the surface of the dielectric.
80. The method of claim 79, further comprising removing the at least one sidewall after planarization.
81. The method of claim 80, wherein the at least one sidewall is removed by liquid etching.
82. The method of claim 74, wherein a capacitor dielectric is formed on the bottom plates prior to formation of the top plate.
83. The method of claim 74, wherein the dielectric layer overlies the contacts.
84. The method of claim 83, further comprising forming a conductive layer over at least one of the contacts prior to dielectric formation.
85. The method of claim 84, wherein one of the bottom plates is brought in contact with a contact via the conductive layer over that contact.
86. The method of claim 74, wherein at least one of the contacts is outside the area.
87. The method of claim 74, further comprising forming a protective layer over at least one of the contacts prior to dielectric formation.
88. The method of claim 87, further comprising removing at least a portion of the protective later over the contact, and wherein that contact is in contact with the second bottom plate.
89. A method for forming a capacitor structure for an integrated circuit, comprising:
- forming a first capacitor on the integrated circuit having first and second plates, wherein the first plate of the first capacitor is in contact with a first node; and
- forming a second capacitor nested within the first capacitor on the integrated circuit having first and second plates, wherein the first plate of the second capacitor is in contact with a second node electrically isolated from the first node.
90. The method of claim 89, further comprising forming a common plate, wherein the common plate comprises a second plate of the first and second capacitors.
91. The method of claim 89, wherein each plate comprises a layer of deposited material.
92. The method of claim 89, wherein the layers constitute polysilicon.
93. The method of claim 89, wherein the first node is coupled to a source or drain region of a first access transistor, and wherein the second node is coupled to a source or drain region of a second access transistor.
94. The method of claim 89, wherein a common dielectric layer intervenes between the first and second plates of each capacitor.
95. The method of claim 89, wherein the first and second capacitors are concentric.
96. The method of claim 89, wherein the first plates of the first and second capacitors comprise substantially vertical portions.
97. The method of claim 96, wherein the substantially vertical portions of the first plate of the first capacitor are nested within the substantially vertical portions of first plate of the second capacitor.
98. The method of claim 89, wherein the common plate comprises substantially vertical portions.
99. The method of claim 89, wherein at least one of the nodes is in contact with one of the first plates via a conductive layer.
100. The method of claim 89, wherein at least one of the first plates comprises nested subplates.
101. The method of claim 89, wherein the first plates comprise substantially vertical sidewalls.
102. The method of claim 89, further comprising a third capacitor nested within the second capacitor on the integrated circuit and having first and second plates, wherein the first plate of the third capacitor is coupled to a third node electrically isolated from the first and second nodes.
103. The method of claim 102, wherein common plate comprises a second plate of the first, second, and third capacitors.
Type: Application
Filed: Jun 22, 2004
Publication Date: Dec 22, 2005
Inventor: Werner Juengling (Boise, ID)
Application Number: 10/873,008