Method and apparatus for establishing additive differential on surfaces for preferential plating

Abstract

A method and apparatus for establishing additive differential on surfaces for preferential plating of conductive material on the surface of a semiconductor wafer having surface portions and cavities on the surface. An additive is adsorbed on the surface in an auxiliary chamber. Conductive material is electrodeposited on the surface after the wafer is transported from the auxiliary chamber to the plating chamber. A sweeper is used to establish a differential in an adsorbed concentration of the additive between the surface portion and the cavities. The differential affects the rate of deposition of the conductive material.

Description

REFERENCE TO RELATED APPLICATIONS

This application is a CIP continuation-in-part of U.S. patent application Ser. No. 10/358,925, filed Feb. 4, 2003 (attorney docket No. ASMNUT.081DV1, ASM Ref. No. NT-020D), which is a divisional of U.S. Pat. No. 6,534,116 (ASM Ref. No. NT-020), filed Dec. 18, 2000 as U.S. patent application Ser. No. 09/740,701.

FIELD OF THE INVENTION

The present invention relates generally to a semiconductor plating method and apparatus. More particularly, the present invention is directed to a method and apparatus that creates a differential between additive adsorbed on a first portion of a workpiece and additive adsorbed on a second portion of the workpiece using an external influence to enhance plating of a conductive material in the second portion of the workpiece.

BACKGROUND OF THE INVENTION

There are many steps required in manufacturing multi-level integrated circuits (IC). Such steps include depositing conductive and insulator materials on a semiconductor wafer or substrate, followed by full or partial removal of these materials using photo-resist patterning, etching, and the like. After photolithography, patterning and etching steps, the resulting surface is generally non-planar as it contains many cavities or features, such as vias, lines, trenches, channels, bond-pads, and the like that come in a wide variety of dimensions and shapes. These features are typically filled with a highly conductive metal material before additional processing steps, such as etching and/or chemical mechanical polishing (CMP) is/are performed. Accordingly, a low resistance interconnection structure is formed between the various levels/sections of the IC.

Copper (Cu) is quickly becoming the preferred material for interconnections in ICs because of its low electrical resistivity and high resistance to electro-migration. Electrodeposition is one of the most popular methods for depositing Cu into the features on the substrate surface.

As can be expected, there are many different designs of Cu plating systems that have been used in this industry. For example, U.S. Pat. No. 5,516,412, issued on May 14, 1996 to Andricacos et al., discloses a vertical paddle plating cell that is designed to electrodeposit a film on a flat article. Next, U.S. Pat. No. 5,985,123, issued on Nov. 16, 1999 to Koon, discloses yet another vertical electroplating apparatus, which purports to overcome the non-uniform deposition problems associated with varying substrate sizes. Further, U.S. Pat. No. 5,853,559, issued on Dec. 29, 1998 to Tamaki et al., discloses an electroplating apparatus that minimizes waste of the plating electrolyte and accomplishes high recovery of the electrolyte.

During the Cu electrodeposition process, specially formulated plating solutions or electrolyte are used. These solutions or electrolyte contain ionic species of Cu and additives to control the texture, morphology, and the plating behavior of the deposited material. Additives are needed to make the deposited layers smooth and somewhat shiny.

There are many types of Cu plating solution formulations, some of which are commercially available. One such formulation includes Cu-sulfate (CUSO₄) as the copper source (see James Kelly et al., Journal of The Electrochemical Society, Vol. 146, pages 2540-2545, (1999)) and includes water, sulfuric acid (H₂SO₄), and a small amount of chloride ions. As is well known, other chemicals can be added to the Cu plating solution to achieve desired properties of the deposited material.

The additives in the Cu plating solution can be classified under several categories, such as suppressors, levelers, brighteners, grain refiners, wetting agents, stress-reducing agents, accelerators, etc. In many instances, different classifications are often used to describe similar functions of these additives. Today, solutions used in electronic applications, particularly in manufacturing ICs, contain simpler additives consisting of two-component, two-ingredient packages (e.g., see Robert Mikkola and Linlin Chen, “Investigation of the Roles of the Additive Components for Second Generation Copper Electroplating Chemistries used for Advanced Interconnect Metallization”, Proceedings of the International Interconnect Technology Conference, pages 117-119, Jun. 5-7, 2000). These formulations are generically known as suppressors and accelerators.

Suppressors are typically polymers formulated from polyethylene glycol-PEG or polypropylene glycol-PPG and are believed to attach themselves to the substrate surface at high current density regions, thereby forming a high resistance film and suppressing the material deposited thereon. Accelerators are typically organic disulfides that enhance Cu deposition on portions of the substrate surface where they are adsorbed. The interplay between these two additives, and possibly the chloride ions, determines the nature of the Cu deposit.

The following figures are used to more fully describe the conventional electrodeposition method and apparatus. FIG. 1 illustrates a perspective view of a cross-section of a substrate 3 having an insulator 2 formed thereon. Using conventional etching techniques, features such as a row of small vias 4a and a wide trench 4b are formed on the insulator 2 and the substrate 3. In this example, the vias 4a are narrow and deep; in other words, they have high aspect ratios (i.e., their depth to width ratio is large). Typically, the widths of the vias 4a are sub-micron. The trench 4b, on the other hand, is typically wide and has a small aspect ratio. In other words, the width of the trench 4b may be five to fifty times or more greater than its depth.

FIGS. 2A-2C illustrate a conventional method for filling the features with Cu. FIG. 2A illustrates a cross sectional view of the substrate 3 in FIG. 1 having various layers disposed thereon. For example, this figure illustrates the substrate 3 and the insulator 2 having deposited thereon a barrier/glue or adhesion layer 5 and a seed layer 6. The barrier layer 5 may be tantalum, nitrides of tantalum, titanium, tungsten, or TiW, etc., or combinations of any other materials that are commonly used in this field. The barrier layer 5 is generally deposited using any of the various sputtering methods, by chemical vapor deposition (CVD), or by electroless plating methods. Thereafter, the seed layer 6 is deposited over the barrier layer 5. The seed layer 6 material may be copper or copper substitutes and may be deposited on the barrier layer 5 using various sputtering methods, CVD, or electroless deposition or combinations thereof. In certain cases, instead of a seed layer, a nucleation layer, such as a ruthenium (Ru) layer, may be deposited on the barrier and copper may be deposited on this layer. Alternatively, copper may be directly deposited on the barrier layer.

In FIG. 2B, after depositing the seed layer 6, a conductive material 7 (e.g., copper layer) is generally electrodeposited thereon from a suitable acidic or non-acidic plating bath or bath formulation. During this step, an electrical contact is made to the Cu seed layer 6 and/or the barrier layer 5 so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the Cu material 7 is electrodeposited over the substrate surface using the specially formulated plating solutions, as discussed above. By adjusting the amounts of the additives, such as the chloride ions, suppressor/inhibitor, and the accelerator, it is possible to obtain bottom-up Cu film growth in the small features.

The Cu material 7 completely fills the via 4a and is generally uniform in the large trench 4b, but does not completely fill the trench 4b because the additives that are used are not operative in large features. For example, it is believed that the bottom-up deposition into the via 4a occurs because the suppressor/inhibitor molecules attach themselves to the top of the via 4a to suppress the material growth thereabouts. These molecules cannot effectively diffuse to the bottom surface of the via 4a through the narrow opening. Preferential adsorption of the accelerator on the bottom surface of the via 4a results in faster growth in that region, resulting in bottom-up growth and the Cu deposit profile, shown in FIG. 2B. Without the appropriate additives, Cu can grow on the vertical walls as well as the bottom surface of the via 4a at the same rate, thereby causing defects, such as seams and/or voids.

Adsorption characteristics of the suppressor and accelerator additives on the bottom surface of the large trench 4b are not expected to be any different than the adsorption characteristics on the top surface of the field regions 8 of the substrate. Therefore, the Cu thickness t₁ at the bottom surface of the trench 4b is about the same as the Cu thickness t₂ over the field regions 8.

As can be expected, to completely fill the trench 4b with the Cu material 7, further plating is required. FIG. 2C illustrates the resulting structure after additional Cu plating. In this case, the Cu thickness t₃ over the field regions 8 is relatively large and there is a step s₁ from the field regions 8 to the top of the Cu material 7 in the trench 4b. For IC applications, the Cu material 7 needs to be subjected to a CMP or other material removal process so that the Cu material 7 as well as the barrier layer 5 in the field regions 8 are removed, thereby leaving the Cu material 7 only within the features. These removal processes are known to be quite costly.

Thus far, much attention has been focused on the development of Cu plating chemistries and plating techniques that yield bottom-up filling of small features on substrates. This is desirable because, as mentioned above, lack of bottom-up filling can cause defects in the small features. As part of these development efforts, it was discovered that the filling behavior of the small features could be affected not only by the solution chemistry, but also by the type of the power supply used for electrodeposition.

Recent studies suggest that it might be preferable to use pulse or pulse-reverse plating methods to deposit defect free Cu into the small vias (e.g., U.S. Pat. No. 5,972,192, issued to Dubin et al. on Oct. 26, 1999, and Gandikota et al. “Extension of Copper Plating to 0.13 um Nodes by Pulse-Modulated Plating”, Proceedings of the International Interconnect Technology Conference, pages 239-241, Jun. 5-7, 2000). In the pulse-reverse plating process, a cathodic voltage pulse rather than a cathodic DC voltage is applied to the substrate surface. After a short period of plating during the cathodic pulse, the polarity of the voltage is reversed for a brief period causing electrochemical etching from the deposited material. Plating and etching cycles are then repeated until the small features are filled with high quality Cu. A recent study (e.g., C. H. Hsieh et al., “Film Properties and Surface Profile after Gap Fill of Electrochemically Deposited Cu Films by DC and Pulse Reverse Processes”, Proceedings of the International Interconnect Technology Conference, pages 182-184, Jun. 5-7, 2000), shows that the filling of the vias is controlled mainly by the additive diffusion when the DC process is used, whereas it is mainly controlled by additive adsorption when a pulse-reverse process is used.

As described above, the attention in the semiconductor industry has mainly been concentrated on filling the various features on semiconductor wafers with Cu. Both DC and pulsed power supplies have been used in the deposition of these Cu films. Filling properties of Cu into small features was found to be a strong function of the type of the power supply used. Although the exact roles of the plating solution additives and their interaction with the applied voltage waveforms are not well understood, it is clear that the kinetics of the additive adsorption and diffusion processes influence the way metals deposit on non-planar substrate surfaces.

As mentioned above, special bath formulations and pulse plating processes have been developed to obtain bottom-up filling of the small features. However, these techniques have not been found effective in filling the large features. In large features, the additives can freely diffuse in and out of them. The use of standard pulse plating techniques, in conjunction with the commonly used additive systems containing chloride ions, accelerators and suppressors/inhibitors, does not yield accelerated growth from the bottom surface of the features where the width of the feature is considerably larger than its depth. The growth of Cu in such features is conformal and the film thickness deposited on the bottom surface of the large features is approximately the same as that deposited on the field regions.

Methods and apparatuses to achieve accelerated bottom-up plating in small as well as large features on a substrate would be invaluable in terms of process efficiency and cost since such a process would yield a Cu deposit that is generally planar, as illustrated in FIG. 3. The Cu thickness t₅ over the field regions 8 in this example is smaller than the traditional case as shown in FIG. 2C, and the step height s₂ would also be much smaller. Removal of the thinner Cu layer in FIG. 3 by CMP or other methods would be easier, providing important cost savings.

Others have previously recognized attractive features of a plated Cu structure, such as the one shown in FIG. 3. For example, in a PCT application (“Electroplated Interconnection Structures on Integrated Circuit Chips”, WO 98/27585, Jun. 25, 1998), researchers from International Business Machines Corporation state that the plating processes described therein produce super-filling of only the sub-micron size cavities when plating was carried out in a conventional plating cell. However, it also states that a further benefit could be realized when a cup plating cell is used, as described in U.S. Pat. No. 4,339,319, issued on Jul. 13, 1982 to Aigo. In addition, when the substrate surface was held in contact with the meniscus of the electrolyte during plating in a cup plating cell, cavities of greatly different widths could be filled rapidly at the same rate yielding a structure similar to that shown in FIG. 3. The PCT application also mentions that superior performance of the meniscus plating approach was due to the higher concentration of the surface active additive molecules at the air-liquid interface.

In the U.S. Pat. No. 6,176,992, entitled “Method and apparatus for electrochemical mechanical deposition”, commonly owned by the assignee of the present invention and hereby incorporated by reference in its entirety, a technique is disclosed that achieves deposition of the conductive material into the cavities on the substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited. The plating electrolyte in this application is supplied to the small gap between the pad and the substrate surface through a porous pad or through asperities in the pad.

FIG. 4 shows a schematic depiction of an electrochemical mechanical deposition apparatus that can be used for planar or near-planar Cu deposition on a semiconductor wafer. A carrier head 10 holds a semiconductor wafer 16 and provides an electrical lead 17 connected to the conductive portion of the wafer 16. The head 10 can be rotated clockwise or counter-clockwise about a first axis 10b and can be moved in x, y, and z directions. A pad 18 is provided on top of an anode assembly 19, which pad 18 faces the wafer 16. An electrolyte 20 containing the plating material is applied to the wafer 16 surface using the anode assembly 19. The electrolyte 20 can be flowed through the holes/openings in the pad 18, which makes physical contact with the wafer 16 surface. The electrolyte 20 then flows in the narrow gap between the wafer 16 and the pad 18, eventually flowing over the edges of the pad 18 into a chamber 22 to be re-circulated (not shown) after cleaning/filtering/refurbishing. A second electrical lead 24 is connected to the anode assembly 19. Any other known method for providing the electric potentials to the anode assembly 19 and cathode wafer 16 can be used herein.

The anode assembly 19 can also be rotated around a second axis 10c at controlled speeds in both the clockwise and counter-clockwise directions. It is also to be understood that axes 10b and 10c are substantially parallel to each other. The gap between the wafer 16 and the pad 18 is adjustable by moving the carrier head 10 in the z direction. When the wafer 16 surface and the pad 18 are in contact, the pressure that is exerted on the two surfaces can also be adjusted. The U.S. Pat. No. 6,413,388, entitled “Pad Designs and Structures for a Versatile Materials Processing Apparatus”, filed Feb. 23, 2000, describes various shapes and forms of the holes in the pad, through which the electrolyte flows to the wafer surface.

During operation, a potential is applied between the electrical lead 17 to the wafer 16 and the electrical lead 24 to the anode assembly 19, making the wafer 16 surface more negative than the anode assembly 19. The electrolyte 20 can be introduced to the pad 18 from a reservoir (not shown) located in proximity to the anode assembly 19. The anode assembly 19 can have an in-channel and holes that are made therein, which together provide a path for the electrolyte 20 to be fed to the gap between the pad 18 and the wafer 16.

Under applied potential, Cu plates out of the electrolyte 20 onto the wafer 16 surface. The moving pad 18 that is pushed against the wafer 16 surface at a controlled pressure minimizes accumulation of Cu over certain portions of the wafer 16 surface by polishing the same.

The pad 18 is preferably made of nonconductive, hard, porous, or perforated type material so that an electric field can pass through it, while preventing shorting between the anode assembly 19 and the cathode wafer 16. The spacing or gap between the pad 18 and the cathode wafer 16 may range from less than 1 micron up to 2 millimeters. The diameter or cross-sectional length of the pad 18 and the wafer 16 may range from about 5 millimeters to over 300 millimeters. The larger the wafer 16 diameter, the larger the pad 18 diameter.

SUMMARY

In accordance with an aspect of the invention, a system is provided for electrodepositing a conductive material onto a surface of a wafer. The surface includes a surface portion and a cavity portion. The system includes an auxiliary chamber and a plating chamber. The auxiliary chamber is configured for having an additive adsorbed on the upper surface portion and the cavity portion of the surface. The plating chamber is configured to electrodeposit the conductive material to form a conductive layer on the surface.

In accordance with another aspect of the invention, a system is provided for electrodepositing a conductive material onto a surface of a wafer. The surface includes an upper surface portion and a cavity portion. The system includes a first chamber and a second chamber. The first chamber includes additive applying means for having an additive adsorbed on the upper surface portion and the cavity portion of the surface. The second chamber includes a plating means for electrodepositing the conductive material on the surface.

In accordance with yet another aspect of the invention, a method is provided for electrodepositing a conductive material onto a surface of a wafer. The surface includes an upper surface portion and a cavity portion. An additive is adsorbed on the upper surface portion and the cavity portion of the surface in a first chamber. The wafer is transported to a second chamber after adsorbing. The conductive material is electrodeposited to form a conductive layer on the surface in the second chamber.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of the present invention will become apparent and more readily appreciated from the following detailed description of the presently preferred exemplary embodiments of the invention taken in conjunction with the accompanying drawings, of which:

FIG. 1 illustrates a perspective view of a cross section of a substrate having an insulator layer and various features formed thereon;

FIGS. 2A-2C illustrate cross-sectional views of a conventional method for depositing a conductive material on the substrate of FIG. 1;

FIG. 3 illustrates a cross-sectional view of a substrate having a conductive material deposited thereon in accordance with another conventional method;

FIG. 4 illustrates an example of an electrochemical mechanical deposition apparatus;

FIG. 5 illustrates a conventional plating cell having an anode, cathode, and electrolyte disposed therein;

FIG. 6 illustrates a partial view of an apparatus in accordance with a preferred embodiment;

FIGS. 7A-7D illustrate a mask pulsed plating method in accordance with the preferred embodiment;

FIG. 7E illustrates a graph corresponding to FIGS. 7A-7D in accordance with the preferred embodiment;

FIG. 8 illustrates a perspective view of an apparatus in accordance with a first preferred embodiment;

FIG. 9 illustrates a perspective view of an apparatus in accordance with a second preferred embodiment;

FIG. 10 illustrates a side view of an apparatus in accordance with a third preferred embodiment;

FIG. 11A-11B illustrate a system including an auxiliary chamber and a plating chamber; and

FIGS. 12A-12D illustrate a substrate processed using the system of the embodiment shown in FIGS. 11A-11B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments will be described herein with reference to the following figures. By mask-pulsed plating the conductive material on the substrate surface, a more desirable and high quality conductive material can be deposited in the various features therein.

Embodiments described herein can be used with any substrate, such as a semiconductor wafer, flat panel, magnetic film head, packaging substrate, and the like. Further, specific processing parameters, such as time, pressure, mask designs, and the like, are provided herein, which specific parameters are intended to be explanatory rather than limiting.

The plating method described herein is called “mask-pulsed” plating. The embodiments discussed herein describe a method and apparatus for mask-pulse plating conductive material onto a substrate by intermittently moving a mask to make contact with the substrate surface and applying power between an anode and the substrate, the mask being positioned in between the anode and the substrate. Furthermore, embodiments are directed to novel plating methods and apparatuses that provide enhanced electrodeposition of conductive materials into the various features on the substrate surface.

FIG. 5 illustrates a plating cell 30 having therein an anode 31, a cathode 32, and an electrolyte 33. It should be noted that the plating cell 30 is a conventional cell and the exact geometry of the plating cell used can vary. The electrolyte 33 is in contact with the top surface of the cathode 32. The cathode 32 in the examples provided herein is a wafer (substrate) having various features on its top surface. When a DC or pulsed voltage is applied between the cathodic wafer 32 and the anode 31, Cu from the electrolyte 33 is deposited on the wafer 32, as described above. The differences between the DC or pulsed power determines the quality of the Cu that is filled in the small features.

FIG. 6 illustrates a preferred embodiment. In this embodiment, a mask 40 is positioned in close proximity to the cathode wafer 32, where the mask 40 includes an opening 42 through which the electrolyte 33 makes physical contact with a section of the wafer 32. For ease of understanding and explanation, FIG. 6 does not illustrate the electrical connections, the anode, and the plating cell containing the electrolyte. When an appropriate voltage is applied between the cathode wafer 32 and the anode, the opening 42 allows the Cu from the electrolyte to be plated onto the surface of the substrate 32 directly below the opening 42. If the mask 40 makes physical contact with the cathode wafer 32, then the plating would largely be limited to the area of the substrate directly underneath the opening 42. When the mask 40 is moved in a side to side motion as indicated by arrow 43, the electrical current passing through a section on the wafer surface will vary. This is discussed in greater detail later herein.

FIGS. 7A-7D illustrate a mask-pulsed plating method in accordance with the preferred embodiment. The mask 40 is moved to the left with respect to the cathode wafer 32 (or alternatively, the wafer 32 may be moved to the right, or both the mask 40 and the wafer 32 may be moved relative to each other). In FIG. 7A, at time t=t₁, a section 45 on the wafer 32 surface is positioned under the electrically insulating mask 40 and is not directly exposed to the electrolyte. Accordingly, the plating current at the section 45 at t=t₁ is very small or near zero, as depicted in the graph of FIG. 7E. FIG. 7E illustrates a graph depicting the deposition/plating current in relation to time at the section 45.

In FIG. 7B, as the mask 40 and/or the wafer 32 is moved such that the opening 42 is above the section 45, the plating current at the section 45 at time t=t₂ increases sharply as the opening 42 aligns with the section 45. In FIG. 7C, the high current remains steady until t=t₃. Thereafter, when the section 45 is again positioned underneath the non-opened portion of the mask 40, as shown in FIG. 7D, the current density is again very small or near zero.

Referring back to FIG. 7E, the time interval Δt (time between t₂ and t₃) is a function of the speed of the mask 40 as well as the size of the opening 42. In addition, Δt will be a small value if the mask 40 is moved rapidly in relation to the wafer 32. Also, if there are multiple openings in the mask 40 or if the movement of the mask 40 is back and forth, then the corresponding current vs. time plots would consist of multiple pulses. By controlling the size of the opening(s) on the mask 40 and the relative speed of the substrate and the mask, the shape, duration and repetition rate of the current pulses at any section on the substrate can be controlled.

As can be seen from the above example, a DC power supply can be used for this plating technique. By moving the solid insulating mask 40 that makes physical contact with the wafer 32, any section on the wafer surface can be suddenly and briefly exposed to the electrolyte and to the applied plating current. This is quite different from the prior art techniques defined above. For instance, in embodiments described herein, certain sections of the wafer surface are substantially free from the electrolyte. The electrolyte is applied to a section of the wafer when that section is exposed to the electrolyte and a pulse of current is simultaneously applied.

If the current mask-pulsed plating method is used with simple metal deposition electrolytes with no additives (i.e., inhibitors and accelerators), it would not be expected to be much different than conventional plating. This is because the size of the openings 42 in the mask 40 is typically much larger than the feature size on the wafer 32 surface. Therefore, when a section is exposed through the opening 42 to the electrolyte, regular plating would commence. However, if additives are added that influence polarization, then the mask-pulsed plating method can offer advantages that are not existent in conventional pulsed plating techniques.

For example, consider a Cu plating bath containing conventional solutions/chemicals (e.g., Cu sulfate, water, sulfuric acid and chloride ions) and an additive A. The additive A enhances deposition when it is adsorbed on the wafer surface. When this electrolyte is used in a conventional plating cell, such as the one depicted in FIG. 5, the entire surface of the wafer 32 will be exposed to the electrolyte and the additive A. The field regions on the wafer surface, as well as the bottom surface of the large features, would likewise adsorb the additive A and plating begins on these surfaces at comparable rates.

If, however, the mask-pulsed plating technique is used with the same electrolyte, the mask would clear away at least a portion of the additive A from the upper supprt portions or field regions since it makes physical contact with these regions. Both the small and large features, however, will still contain the adsorbed additive A since these features are not in direct physical contact with the mask. When a section of the wafer is suddenly exposed to the electrolyte, the bottom and side surfaces of the features (cavity portions) with the previously adsorbed additive A would immediately start plating at a higher rate than the field regions. If the time period Δt is less than the adsorption period required for the additive A to attach itself to the substrate surface, the applied plating current preferentially flows through the features to be filled, thereby yielding an enhanced deposition rate within the features in relation to the deposition rate on the field regions.

The mask-pulsed plating method described herein utilizes the differences between response times of various additives to achieve enhanced plating into the various features of the substrate surface. The mechanism involves “sweeping” of the top surface of the substrate (field regions) by the mask, which does not make physical contact with the regions inside the features. The sweeping on the field regions establishes a differential between the concentration of the adsorbed species in those regions that are swept away and the regions that are within the features. When the surface is then suddenly exposed to the electrolyte and the electric field, the features with the adsorbed species attracts most of the plating current from the field regions.

This method works equally well using multiple additives. For example, if the plating solution contains an inhibitor B and an accelerator C with the adsorption kinetics of the inhibitor being much faster than that of accelerator, the following mechanism can be used by the mask-pulsed plating method. Both the inhibitor B and the accelerator C would be partially or wholly swept off the field regions of the substrate by the mask. However, both species would still be present in the cavities or features. When the substrate is exposed to the electrolyte and the electric field, the inhibitor B would readily adsorb onto the upper surface portions or field regions, introducing a high resistance path for the plating current. The accelerator C, which is already present within the features, compensates for the action of the inhibitor in those regions and the current can easily flow through these features. Therefore, until the accelerator C is properly adsorbed onto the field regions, the film growth rate within the features will be higher.

This same result can also be expected from yet another chemistry where an inhibitor D has the property of strong adsorption and an accelerator E is weakly bonded to the field regions. In this case, the mask can readily remove the weakly bonded accelerator E from the field regions whereas, the accelerator E remains attached to the surfaces within the features. Upon exposure to the electrolyte and electric field, the plating current flows through the features preferentially until the accelerator E begins to get adsorbed again onto the field regions.

It should be noted that the above descriptions are just some examples of the mechanisms involved in the embodiments described herein and are not meant to be limiting. The embodiments described herein utilize differences between adsorption/de-sorption kinetics of various electrolyte additives. The embodiments described herein accomplish this by applying a solution and power suddenly and simultaneously to a specific section of the substrate surface that has been previously cleared off, partially or wholly, of one or more of the additive species.

In the following section, an exemplary process sequence using a system 100 will be described with reference to FIGS. 11A-11B, and the corresponding changes on the surface of a wafer when such process steps are applied will be shown with reference to FIGS. 12A-12D. FIGS. 12A-12D illustrate an exemplary surface 200 of the wafer W including a feature or cavity portion 202, such as a large via or trench, with a depth-to-width ratio of less than one, surrounded by an upper surface portion or surface region 204 or as often called, a field region, which is an exemplary part of the surface 101 of the wafer W shown in FIGS. 11A and 11B. The surface 200 may be a part of a dielectric layer and may be coated with a conductive layer (not shown), often a bi-layer containing a barrier layer, which is deposited on the exposed surfaces of the dielectric layer and a seed layer, which is deposited on the barrier layer. The barrier layer may be a Ta or TaN layer, and the seed layer is preferably a thin metal layer, such as, for example, a copper seed layer for copper electrodeposition applications. Alternatively, the conductive layer on the wafer surface 101 may be a pre-formed conductive layer and the cavity portions or feature 202 may be a cavity in the pre-formed conductive layer. The pre-formed conductive layer may be obtained by electrodepositing or electroless depositing a conductive material, such as copper, on the wafer surface 101. Such layers may be formed during a predetermined stage of a wet deposition process.

Referring to FIG. 11A, in a first process step, as the wafer W is rotated on the wafer carrier 120, a solution (shown by arrows A) comprising at least one additive is delivered onto the surface 101 of the wafer W in the auxiliary chamber 102. Correspondingly, as shown in FIG. 12A, additives or additive molecules, depicted as small circles, in the solution are attached to, or adsorbed on the walls of the cavity portion or feature 202 and the upper surface portion or surface region 204 of the wafer surface 101. At this stage of the process, additive concentrations on the surface of the cavity portion or feature 202 and on the upper surface portion or surface region 204 are substantially the same. The solution may contain accelerators and/or suppressors and/or levelers. The solution may also comprise inorganic additives, such as Cl ions, other anions and/or cations, buffers, etc. The pH of the solution may be neutral, acidic, or basic. The solution may be aqueous or it may comprise organic solvents. In the case of processing copper layers, the solution may also be a copper plating solution, such as a commonly used copper sulfate-based acidic solution. The solution preferably comprises an accelerator additive and it is preferably an aqueous solution. During the process, the surface 101 is preferably soaked with the solution for about 1-200 seconds, and more preferably about 5-60 seconds. The wafer W is moved during application of the additive to achieve uniform distribution over the surface 101. The wafer W is preferably rotated at 1-100 rpm, and more preferably at 5-50 rpm during the application of the accelerators. It should be noted that the process step that causes additive adsorption on the wafer surface 101 may be carried out by various other ways, including, for example, soaking the wafer surface 101 in a container filled with a solution comprising the desired additive, and delivering the additive to the wafer surface in the form of a mist or vapor so that a thin layer comprising the additive forms on the surface. One exemplary composition of an additive containing solution is a water and SPS solution where SPS content may be, for example, 1-1000 ppm and the pH may be adjusted to a range of 1-5, using sulfuric acid or hydrochloric acid. Alternatively, an aqueous solution with 1-100 ml/l of accelerators commercially available from suppliers, such as Rohm and Haas and Enthone, may be employed.

Once the additives are adsorbed on the surface 101, as shown in FIG. 12A, the separators 106 are opened and the wafer carrier 120 is extended into the plating chamber 104 from the auxiliary chamber 102 (using the same or different nozzles from those spraying the solution A) to perform a deposition process step, as shown in FIG. 11B. It should be noted that the wafer W may be spin dried in the auxiliary chamber 102 before it is lowered into the plating chamber 104. Alternatively, the wafer W may be rinsed first in the auxiliary chamber 102 and then dried before it is lowered into the plating chamber 104. For additives that are not easily desorbed from surfaces, such as accelerators, such rinsing and drying steps do not disturb the additive coverage of the surface shown in FIG. 12A. For additives that can be desorbed easily from the wafer surface 101, such rinsing process steps may be omitted. In the illustrated embodiment, the auxiliary chamber 102 and the plating chamber 104 are contained within a common housing and are vertically integrated. In alternative embodiments, the chambers 102, 104 may be in separate housings and/or horizontally integrated. It should be noted that not all of the steps or functions disclosed herein need to be conducted in one of the two illustrated chambers; in various embodiments, one or more or the disclosed steps or functions can be conducted in other chambers.

As shown in FIG. 11B, in the next step of the process, a conductive material, which is copper in the illustrated embodiment, is electrodeposited on the surface 101 of the wafer W from the electrolyte as the electrolyte is delivered on the surface 101 while physical contact and relative motion are established between the surface 101 and the sweeper 118 and a potential difference is applied between the surface 101 and the electrode 116. The plating chamber 104 comprises a plating cell that is designed to perform a mask-pulsed plating method, as described above. In that respect, the plating cell in the plating chamber 104 may have the features similar to those shown in FIGS. 6, 8, 9 or 10. These features will be described below. In FIGS. 11A and 11B, the simplified plating cell is shown to include an electrode 116, a mask or sweeper 118 and the means (e.g., nozzles or openings in the sweeper) to deliver a plating solution 114 through the openings in the sweeper 118 towards the wafer surface 101 once the wafer W is brought into the plating chamber 104. The sweeper 118 may, for example, correspond to the mask 80 of FIGS. 8, 9, and 10 described below. The electrolyte plating solution 114 may contain at least one additive.

If the additive adsorbed on the surface in the auxiliary chamber (see FIG. 12A) is an accelerator, then the electrolyte in the plating chamber preferably includes at least a suppressor. As described before, the mask-pulsed plating method utilizes the differences between response times of various additives to achieve enhanced plating into the various features of the substrate surface. The mechanism involves “sweeping” of the top surface of the substrate (field regions) by the sweeper or mask, which does not make physical contact with the regions inside the features. The sweeping on the field regions or upper surface portions establishes a differential between the concentration of the adsorbed species in those regions that are swept away and the regions that are within the features (cavity portions). When the surface is then suddenly exposed to the electrolyte and the electric field, the features with the adsorbed species attracts most of the plating current from the field regions. Below is a description of this process for an exemplary case where the adsorbed additive in FIG. 12A is an accelerator and the mask-pulsed plating is carried out in the plating chamber 104 using an electrolyte 114 that contains suppressors.

FIG. 12B schematically shows the status of the surface 200 of FIG. 12A right after it has been swept by the sweeper 118 in the plating chamber 104. If we consider the surface 200 to be at section 45 of FIGS. 7A-7D and the sweeper 118 to be similar to the mask 40 of FIGS. 7A-7D, then the instant right after sweeping the surface portion 200 may be the time t=t₂ shown in FIG. 7E. As can be seen from FIG. 12B, an additive differential, which is an accelerator differential in this illustrated embodiment, is established between the upper surface portion or surface region 204 and the internal cavity walls of the feature 202 by sweeping the surface 200 with the sweeper 118. Although the sweeping action is preferably conducted as the potential difference is applied between the electrode 116 and the surface 101 (FIG. 11B) or the surface 200, sweeping may also be carried out before or after the plating is initiated or intermittently during the plating process. The sweeping action, described in connection with FIG. 11B, removes a significant amount of the accelerators from the upper surface portion or surface region 204 or such sweeping action causes accelerators to desorb from the upper surface portion or surface region 204 leaving, at that instant, a reduced amount distributed across the upper surface portion or surface region 204 in comparison to the accelerator concentration on the internal feature surfaces 202. Therefore, during the time Δt (see FIG. 7E) right after the surface 200 is swept by the mask and then exposed to the plating electrolyte and plating current, deposition of the conductive material into the cavity portion or feature 202 is enhanced compared to deposition onto the upper surface portion or surface region 204, due to the higher accelerator concentration within the cavity portion or feature 202. FIG. 12B does not show any deposited material on the surface 200 since it depicts the situation at instant t=t₂. In fact, the differential in the relative surface concentrations of the adsorbed additives persists during copper deposition as long as the additives are slow to adsorb back onto the upper surface portion or surface region 204. The electrolyte used for plating preferably includes suppressors or may contain just suppressors as organic plating additives.

As described above, deposition is enhanced into the feature 202 as soon as the surface 200 is exposed to the plating electrolyte right after sweeping (FIG. 12B). This corresponds to the instant t₂ in FIG. 7E. Referring to FIG. 7E, plating continues during a period Δt after which, at time t₃, the solid portion of the mask starts again to sweep the surface 200 and substantially blocks the current flow to the surface 200. During the time period Δt, additives present in the plating electrolyte are free to adsorb onto the surface 200 and change the deposition rate of material onto the upper surface portion or surface region 204 and into the cavity portions or features. If the plating electrolyte contains an suppressor (inhibitor) and an accelerator with the adsorption kinetics of the inhibitor being much faster than that of accelerator, then during time Δt when the substrate is exposed to the electrolyte and the electric field, the inhibitor would readily adsorb onto the field regions or upper surface portion 204, introducing a high resistance path for the plating current. The accelerator is already present within the cavity portions or features therefore, the suppressor cannot readily adsorb onto the cavity walls 202. The additive distribution at an exemplary instant during the time period Δt is schematically shown in FIG. 12C, where suppressor additives adsorbed on the surface 200 are shown as small crosses x. Those skilled in the art will appreciate that an additive concentration differential, such as the one shown in FIG. 12C, with high accelerator concentration (o) within the features and high suppressor concentration (x) on the upper surface portion or surface region 204 will provide a higher deposition rate into the cavity portion or feature 202, resulting in a planarized structure, such as the one shown in FIG. 12D. Similar results may be obtained using plating electrolytes containing only a suppressor as organic additives and carrying out the mask-pulsed plating on wafer surfaces containing adsorbed accelerators, as shown in FIG. 12A. In this case, when the swept surface portion of FIG. 12B is exposed to the electrolyte containing suppressors at time t₂ right after sweeping, suppressor molecules start to adsorb on the upper surface region 204 and fill the available surface sites from which some of the accelerators were cleared by the sweeping action of the sweeper, as shown in FIG. 12C. As stated before, suppressors or suppressor molecules adsorbed on the surface region 204 and on the feature or cavity portions 202 are depicted with small ‘x’ signs. Since the internal surfaces 202 of the feature are already heavily populated by adsorbed accelerators, there is limited space to accommodate suppressor molecules on the internal surfaces 202 of the feature. This slows down the kinetics of suppressor adsorption onto the internal surfaces 202 of the feature because desorbing the already adsorbed accelerators from such surfaces and replacing them with suppressor molecules is a relatively slow process. Therefore, even though the suppressors are in the plating environment, they cannot switch sites with the accelerators and be quickly adsorbed on the surfaces occupied by the accelerators. Suppressors, however, can adsorb very quickly onto the swept and activated upper surface portion or surface region 204. For example, in some embodiments, suppressor molecules may adsorb on swept surfaces within time periods in the range of 0.0001-1 second, whereas it may take them 0.1-1000 seconds to be adsorbed on surfaces with a high population of accelerators. These values, of course, are strong functions of the chemicals used as accelerators and suppressors. Commonly used accelerators include chemicals, such as SPS, bis(sodiumsulfopropyl)disulfide, and commonly used suppressors include, for example, polyethylene glycol (PEG) related polymers.

As for the accelerators that are swept off the upper surface portion or surface region 204 during sweeping by the mask or sweeper 118, they become included into the plating electrolyte. Therefore, even if their molecular structure may be different, accelerators could, in principal, come back and re-adsorb onto the upper surface portion or surface region 204 if their adsorption kinetics were as fast as or faster than that of suppressors. But as long as the suppressor concentration of the electrolyte is much larger than the concentration of accelerators introduced from the wafer surface due to sweeping, adsorption is dominated by the suppressors. This is because adsorption of additives from a solution onto a surface is also a function of their respective concentrations in the solution, with higher concentrations giving rise to higher adsorption on the surface. The exemplary plating solution discussed here may contain 1-10000 micromoles of suppressors, such as PEG, whereas the accelerator concentration introduced into the bath due to surface sweeping may be much smaller than 1 micromole. These calculations may be readily made, depending upon the nature and chemistry of the specific accelerator and suppressor additives used in the process, and the suppressor concentration in the plating solution may be adjusted accordingly to assure a much higher suppressor concentration in the plating electrolyte than the swept off accelerator concentration.

As described above and shown in FIG. 12C, the process yields a small accelerator-to-suppressor ratio on the upper surface portion or surface region 204 and a much larger ratio within the cavity portions or feature 202 through the use of a sweeper that sweeps the upper surface portion or surface region 204 of the wafer surface. This means a much higher deposition rate going into the cavity portions or feature 202 compared to onto the upper surface portion or surface region 204 during electrodeposition. As shown in FIG. 12D, an electrodeposition process with enhanced copper deposition into the cavity portions or feature 202 results in a copper layer 206 filling the feature 202 and extending on the upper surface portion or surface region 204. This film is much more planar than a film deposited by regular electroplating techniques, as shown in FIG. 2C. The copper layer 206 is preferably thin over the upper surface portion or surface region 204 and fills the cavity 202 because of the higher rate of deposition into the feature 202 and a reduced rate of deposition onto the upper surface portion or surface region 204. This is because of the accelerator differential present on the surface 200 shown in FIGS. 12B and 12C. Accordingly, as long as an additive differential exists, copper continues to deposit into the cavity portions or feature 202 at a higher rate (typically 1.5-10 times) than it deposits on the upper surface portion or surface region 204. In this application, the additive differential refers to accelerator differential, or suppressor differential, or both.

After completing the electroplating process, the wafer W held by the wafer carrier 120 is preferably retracted into the auxiliary chamber 102, shown in FIGS. 11A and 11B, and the separators 106 are closed. A cleaning solution, such as DI water (de-ionized water), is applied onto the wafer W from some of the nozzles 109 to rinse or clean the wafer W and the copper layer 206. After rinsing, the wafer W is spin-dried by rotating the wafer carrier 120, preferably at a high speed. It will be appreciated that each step of the process is preferably performed while the wafer W is held by the same wafer carrier 120, which eliminates time losses and contamination problems, which may result if the wafer W is transferred by switching carrier heads. Although it is possible to practice this embodiment by transferring the wafer W from one carrier to another, using only one carrier increases process yield and minimizes contamination problems. Further, the process may be performed using chambers integrated horizontally by placing an auxiliary chamber next to a plating chamber. In this horizontal arrangement of the chambers, a wafer may be processed on the same carrier head in both chambers or on different carrier heads by transferring the wafer from an auxiliary chamber carrier head to a plating chamber carrier head.

The geometry of the plating system shown in FIG. 6 is quite simplistic. There are many possible designs that can be used. Some important aspects of the embodiments described herein are as follows.

• • 1. The mask and the wafer surface should be engaged well when in contact. The mask surface facing the wafer may contain abrasives to help “sweep” away the additives more efficiently.
  • 2. There should be a relative movement between the wafer and the mask. The wafer, mask, or both may be moved in linear or orbital manner or combination thereof.
  • 3. There should be substantially no electrolyte between the mask and the wafer surface, i.e., physical contact between the wafer surface and the mask surface should be good. The wafer surface should be exposed to electrolyte through the opening(s) in the mask.
  • 4. The size of the opening(s) in the mask and the speed of the relative motion between the mask and the wafer should be such that any section on the wafer should be exposed to the electrolyte only briefly, typically for less than two seconds, preferably less than one second, e.g., 10-500 msec. This time interval should be adjusted with respect to the adsorption characteristics of the additives being used.

FIG. 8 illustrates a perspective view of an apparatus in accordance with a first preferred embodiment. In FIG. 8, a mask 80 and an electrolyte channel plate 300 are mounted on an anode assembly 90. The electrolyte 82 is supplied to the anode assembly 90 by a conventional pumping system (not shown). The electrolyte 82 is pumped through the holes 92 into the channels 310 in the channel plate 300. In operation, the substrate/cathode is positioned facing the top surface of the mask 80 and the substrate and/or the mask 80 is/are rotated (relative motion is established). The substrate may be pushed against the mask 80 at a pressure in the range of 0.01 psi to 0.5 psi. Higher pressures may be used, but may not be necessary. If the mask 80 is rotated, the entire anode assembly 90 may likewise be rotated. A cathodic voltage is applied to the substrate (not shown) with respect to an anode (not shown) placed within the anode assembly 90. The electrolyte 82 flowing through the channels 310 make physical contact with the substrate surface through the openings 84 in the mask 80. The electrolyte 82 is continuously discharged from the small bleeding holes 320 to be filtered and re-circulated. Very little, if any electrolyte 82 actually flows into the interface between the mask 80 and the substrate surface, which are in intimate contact during operation.

FIG. 9 illustrates a perspective view of an apparatus in accordance with a second preferred embodiment. The apparatus in FIG. 9 is similar to that shown in FIG. 8, except for the holes 510 and the channel plate 600. The channel plate 600 includes different shaped channels 610, which are used to distribute the electrolyte 82 in a serial manner to the openings 84 of the mask 80.

FIG. 10 illustrates a side view of an apparatus in accordance with a third preferred embodiment. In this embodiment, FIG. 10 shows the electrolyte 82 coming into a reservoir 86 that resides on the top portion of the anode assembly 90. The electrolyte 82 makes contact with the surface of the wafer 350 through holes 84 in the mask 80. The electrolyte 82 can be discharged from the reservoir 86 through bleeding holes 91.

The power supply used in these embodiments may be pulsed or a DC power supply, but preferably it is a DC power supply. The power supply can be used in the current controlled or voltage controlled mode, i.e., it either keeps the applied current constant or applied voltage constant. For the case of using a current controlled mode, it is important that the size of the opening(s) in the mask be large enough to cover portions of the field regions as well as portions of the features simultaneously. In other words, when the wafer surface is exposed to the electrolyte through the opening(s), there should not be just the field regions that are exposed to the electrolyte at any given time. For example, if the opening is very small or the number of features on the wafer surface is low (low density features), the field regions are exposed to the electrolyte. In this case, since the power supply pushes through a fixed current, all the current would flow through the field regions and the Cu will be plated on the field region without discrimination. If both field regions and features are exposed simultaneously, then the current would preferentially flow through the features and more Cu would be plated into the features and less on the field regions. This situation can be assured by increasing the number of openings in the mask so that there are always portions of the both regions (field and feature) exposed through some of the holes simultaneously.

If a constant voltage power supply is used, then the current automatically adjusts itself depending upon the resistance on the wafer surface. Therefore, if the mask hole exposes only the field regions of the wafer, less current is supplied to that surface and the plating amount is smaller. When features are exposed to the solution, more current flows into the feature and thus preferential plating takes place into the features. Therefore, it is more appropriate to use a voltage controlled mode of the power supply if wafers with low feature density is coated and/or the number of holes in the mask is limited.

The process described above can be used to fill both small and large features. However, a serial process can also be utilized. In that approach, there are two processing steps. During the first step, the mask is pulled away from the wafer surface, allowing a substantial amount of plating solution between the mask and the wafer surface. In this position, the system acts just like a traditional plating cell. With the help of the additives in the plating solution, the small features are filled during this step and the situation shown in FIG. 2B occurs. During this first step, the mask and the substrate are moved with respect to each other for uniform deposition. Then the mask is brought in contact with the surface, squeezing out the solution from the wafer/mask interface except at the holes/openings on the mask. Mask-pulsed plating then commences to preferentially fill the larger features as described earlier. It is important to note that in the mask-pulsed plating technique, there is substantially no plating solution between the mask and the wafer surface, except where the mask holes/openings are positioned.

Along with using copper and its alloys as the conductive material, other conductive materials, such as copper alloys, iron, nickel, chromium, indium, lead, tin, lead-tin alloys, nonleaded solderable alloys, silver, zinc, cadmium, ruthenium, and their respective alloys, may be used. The process is especially suited for the fabrication of high performance and highly reliable chip interconnect, packaging, magnetic, flat panel and opto-electronic applications.

In the previous descriptions, numerous specific details are set forth, such as specific materials, mask designs, pressures, chemicals, processes, etc., to provide a thorough understanding of the embodiments described herein. However, as one having ordinary skill in the art would recognize, the embodiments can be practiced without resorting to the details specifically set forth.

Although various preferred embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications of the exemplary embodiment are possible without materially departing from the novel teachings and advantages of this invention.

Claims

1. A system for electrodepositing a conductive material onto a surface of a wafer, wherein the surface includes an upper surface portion and a cavity portion, the system comprising:

an auxiliary chamber configured to have an additive adsorbed on the upper surface portion and the cavity portion of the surface; and

a plating chamber configured to electrodeposit the conductive material to form a conductive layer on the surface.

2. The system of claim 1, further comprising a workpiece surface influencing device in the plating chamber, the workpiece surface influencing device configured to establish a differential in an adsorbed concentration of the additive between the upper surface portion and the cavity portion of the surface.

3. The system of claim 2, wherein the additive comprises an accelerator.

4. The system of claim 2, wherein the workpiece surface influencing device includes a sweeper.

5. The system of claim 4, wherein the sweeper includes a pad configured to touch the surface of the wafer while the differential is being established.

6. The system of claim 4, further comprising a moving mechanism configured to move the sweeper relative to the surface.

7. The system of claim 1, wherein the auxiliary chamber includes means for applying the additive to the surface of the wafer.

8. The system of claim 7, wherein the means for applying the additive to the surface are nozzles configured to inject the additive towards the surface.

9. The system of claim 7, wherein the additive comprises an accelerator.

10. The system of claim 1, further including a wafer carrier configured to hold the wafer within the auxiliary chamber.

11. The system of claim 1, wherein the plating chamber includes a plating unit with an electrode.

12. The system of claim 11, wherein the plating chamber is configured to supply a plating solution to the plating unit.

13. The system of claim 12, wherein the plating solution includes suppressor additives.

14. The system of claim 1, wherein the conductive material is copper.

15. A system for electrodepositing a conductive material onto a surface of a wafer, wherein the surface includes an upper surface portion and a cavity portion, the system comprising:

a first chamber including additive applying means for having an additive adsorbed on the upper surface portion and the cavity portion of the surface; and

a second chamber including a plating means for electrodepositing the conductive material on the surface.

16. The system of claim 15, further comprising an additive differential forming means in the second chamber to establish a differential in an adsorbed concentration of the additive between the upper surface portion and the cavity portion of the surface.

17. The system of claim 15, wherein the additive applying means includes nozzles configured to apply the additive to the surface.

18. The system of claim 16, wherein the additive differential forming means includes a sweeper configured to sweep the surface.

19. The system of claim 15, wherein the plating means includes a deposition unit having an electrode immersed in an electrolyte.

20. The system of claim 19, wherein the electrolyte includes a suppressor.

21. The system of claim 17, wherein the additive comprises an accelerator.

22. The system of claim 18, wherein the sweeper includes a pad configured to touch the surface of the wafer while the differential is being established.

23. The system of claim 18, further comprising a moving mechanism configured to move the sweeper relative to the surface.

24. The system of claim 15, further including a wafer carrier configured to hold the wafer within the first chamber.

25. A method of electrodepositing a conductive material onto a surface of a wafer, wherein the surface includes an upper surface portion and a cavity portion, the method comprising:

having an additive adsorbed on the surface portion and the cavity portion of the surface in a first chamber;

transporting the wafer to a second chamber after having the additive adsorbed; and

electrodepositing the conductive material to form a conductive layer on the surface in the second chamber.

26. The method of claim 25, further comprising establishing a differential in an adsorbed concentration of the additive between the surface portion and the cavity portion of the surface in the second chamber.

27. The method of claim 26, wherein establishing a differential comprises sweeping the surface with a sweeper.

28. The method of claim 27, wherein the additive comprises an accelerator.

29. The method of claim 27, wherein the sweeper includes a pad configured to touch the surface of the wafer while the differential is being established.

30. The method of claim 25, further including applying the additive to the surface of the wafer to have the additive adsorbed on the surface.

31. The method of claim 30, wherein applying comprises injecting the additive towards the surface using nozzles.

32. The method of claim 31, wherein the additive comprises an accelerator.

33. The method of claim 25, further including holding the wafer by a wafer carrier.

34. The method of claim 33, wherein transporting is performed with the wafer carrier.

35. The method of claim 33, wherein transporting is performed with another wafer carrier.

36. The method of claim 25, wherein electrodepositing is performed in the second chamber comprising a plating unit with an electrode and a plating solution.

37. The method of claim 36, wherein the plating solution includes suppressor additives.

38. The method of claim 25, wherein the steps of having the additive adsorbed, transporting the wafer and electrodepositing the conductive material are carried out while the wafer is held by a wafer carrier.

39. The method of claim 25, further including rinsing the wafer after adsorbing the additive and before electrodepositing the conductive material.

40. The method of claim 39, further including drying the wafer after rinsing.

41. The method of claim 25, further including cleaning the wafer after electrodepositing.

42. The method of claim 41, wherein cleaning is carried out in the first chamber.

43. The method of claim 25, wherein the conductive material is copper.

44. A method of electrodepositing a conductive material onto a surface of a wafer, wherein the surface includes a first surface portion and a second surface portion, the method comprising:

having an additive adsorbed on the first surface portion and the second surface portion of the surface in a first chamber;

transporting the wafer to a second chamber after having the additive adsorbed; and

electrodepositing the conductive material to form a conductive layer on the surface in the second chamber using a plating solution while sweeping the first surface portion with a sweeper.

45. The method of claim 44, wherein said sweeping establishes a differential in an adsorbed concentration of the additive between the first surface portion and the second surface portion of the surface.

46. The method of claim 45, wherein the additive comprises an accelerator additive.

47. The method of claim 45, wherein the sweeper includes a pad configured to touch the surface of the wafer while the differential is being established.

48. The method of claim 46, wherein electrodepositing deposits thicker conductive material on the second surface portion than on the first surface portion.

49. The method of claim 48, wherein the plating solution includes a suppressor additive.

50. The method of claim 49, wherein the first surface portion is a top surface portion and the second surface portion is a cavity portion.