Polymerization of macrocyclic polyester oligomers using N-heterocyclic carbene catalysts

Abstract

A method, system, and a computer usable program code for reducing the effects of intersymbol interference in a high speed data transmission using various steps. First, a training sequence is established between a transmitter operably connected by a conductor to a receiver. Data is analyzed at the receiver. Transition bits following a stable data stream are skewed by the transmitter. When data is received at the receiver, the variable transition time for the transition bits is adjusted by the transmitter to optimize timing and reduce timing effects of intersymbol interference.

Description

This application claims the benefit of U.S. Provisional Application No. 60/626,189, filed Nov. 9, 2004, which is incorporated in its entirety as a part hereof for all purposes.

TECHNICAL FIELD

This invention relates to the polymerization of macrocyclic polyester oligomers. More particularly, it relates to a genus of catalysts for such polymerizations that provide rapid polymerization with high monomer conversion, producing high molecular weight, mechanically sound polymer.

BACKGROUND

Linear thermoplastic polyesters such as poly(alkylene terephthalate) are generally known and commercially available where the alkylene typically has 2 to 8 carbon atoms. Linear polyesters have many valuable characteristics including strength, toughness, high gloss and solvent resistance. Linear polyesters are conventionally prepared by the reaction of a diol with a dicarboxylic acid or its functional derivative, typically a diacid halide or diester. Linear polyesters may be fabricated into articles of manufacture by a number of known techniques including extrusion, compression molding and injection molding.

Recently, macrocyclic polyester oligomers were developed which have unique properties that make them attractive as matrices for engineering thermoplastic

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention is directed generally toward data processing and particularly, to a method and system, for reducing the timing effects of intersymbol interference in high-speed data transmissions.

2. Description of the Related Art

High speed serial data transfer has grown progressively more important in recent years because of technological improvements and high-speed computing requirements. Complex computer software, circuitry, and peripherals as well as ever-increasing bandwidth and processing speeds have made reliable high-speed data transmissions crucial. As a result, it has become increasingly difficult to maintain signal integrity within technical and cost requirements.

Data transmission lines inherently have some resistance as well as parasitic inductance and capacitance that have degrading effects on high-speed serial transmissions. The longer the line, the more pronounced the effects on a transmission signal and the more difficult it is to properly sample the data. High-speed serial transmission may be seriously affected by the effects of intersymbol interference (ISI). Intersymbol interference in a digital transmission system is distortion of the received signal in which the distortion may prevent a receiver of the signal from being able to correctly distinguish between changes of state between individual signal elements.

For example, deterministic jitter and signal amplitude degradation are two types of intersymbol interference.

First, deterministic jitter is interference or distortion of a transmission signal that can induce errors and loss of data on a transmission line because of the slight movement of a transmission signal in time or phase from its reference timing position. Decreasing tolerance for jitter in terms of technical specifications and cost has made jitter an important issue.

Second, signal amplitude degradation results when the transmission line charges during long periods of stable data due to parasitic capacitance. The charge reduces the achievable amplitude for successive high frequency transition bits following a long steady state pulse, increasing data decoding errors and loss of data.

A current solution to intersymbol interference is a procedure called pre-emphasis or de-emphasis at the transmitter. Emphasis is an intentional reduction in amplitude in order to reduce the charging effects that give rise to intersymbol interference. Emphasis allows the originating signal to be changed or modified at the transmitter to improve signal quality at the receiver after it has passed through the electrical channel connecting transmitter and receiver. Emphasis reduces intersymbol interference but does not eliminate this type of interference.

The problem is further complicated depending on the operational environment which is affected by many elements including conductor composition, cabling, and interconnections. Errors commonly occur when data transferred between the transmitter and receiver has a steady state stream of bits either logic high or logic low followed by fluctuating high frequency data. As a result, intersymbol interference continues to be a problem in high-speed serial data transmissions.

SUMMARY OF THE INVENTION

A method, system, and computer usable program code for reducing the timing effects of intersymbol interference in a high-speed data transmission using various steps. First, a training sequence is established between a transmitter operably connected by a conductor to a receiver. Data is analyzed at the receiver. Transition bits following a stable data stream are skewed by the transmitter. When data is received at the receiver, the variable transition time for the transition bits is adjusted by the transmitter to optimize timing and reduce the timing effects of intersymbol interference.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a pictorial representation of a data processing system in which aspects of the present invention may be implemented;

FIG. 2 is a block diagram of a data processing system shown in which the present invention may be implemented;

FIG. 3 is a block diagram of a transmitter and receiver system in which aspects of the present invention may be implemented;

FIG. 4 is a prior art circuit model for analyzing a transmission line;

FIG. 5 is a prior art simplified circuit model for analyzing a transmission line;

FIG. 6 is a block diagram of a transmitter in accordance with an illustrative embodiment of the present invention;

FIG. 7 is a block diagram of a receiver in accordance with an illustrative embodiment of the present invention;

FIG. 8 is a timing diagram of a received signal due to intersymbol interference and an ideal clock in accordance with an illustrative embodiment of the present invention;

FIG. 9 is a timing diagram of transmitted data with time shifted bits compensating for intersymbol interference, received data, and ideal clock in accordance with an illustrative embodiment of the present invention;

FIG. 10 is a timing diagram of transmitted data with emphasis and time shifted bits compensating for intersymbol interference, received data, and ideal clock in accordance with an illustrative embodiment of the present invention;

FIG. 11 is a flowchart illustrating the operation of a system for training a transmitter to transmit a signal with proper time skew in accordance with an illustrative embodiment of the present invention; and

FIG. 12 is a flowchart illustrating the operation of a receiver in accordance with an illustrative embodiment of the present invention.

DETAILED DESCRIPTION

With reference now to the figures and in particular with reference to FIG. 1, a pictorial representation of a data processing system in which the aspects of the present invention may be implemented. Computer 100 is depicted which includes system unit 102, video display terminal 104, keyboard 106, storage devices 108, which may include floppy drives and other types of permanent and removable storage media, and mouse 110. Additional input devices may be included with personal computer 100, such as, for example, a joystick, touchpad, touch screen, trackball, microphone, and the like. Although the depicted representation shows a computer, other embodiments of the present invention may be implemented in other types of data processing systems, such as a network computer. Computer 100 also preferably includes a graphical user interface (GUI) that may be implemented by means of systems software residing in computer readable media in operation within computer 100.

With reference now to FIG. 2, a block diagram of a data processing system is shown in which the present invention may be implemented. Data processing system 200 is an example of a computer, such as computer 100 in FIG. 1, in which code or instructions implementing the processes of the present invention may be located. Data processing system 200 employs a peripheral component interconnect (PCI) local bus architecture. Although the depicted example employs a SAS and PCI bus, other bus architectures and standards such as Serial Advanced Technology Attachment (SATA) interface, Accelerated Graphics Port (AGP), and Industry Standard Architecture (ISA) may be used. Processor 202 and main memory 204 are connected to PCI local bus 206 through PCI bridge 208. A controller as used herein may refer generally to a processing element or an application specific integrated circuit (ASIC) or the combination thereof.

PCI bridge 208 also may include an integrated memory controller and cache memory for processor 202. Additional connections to PCI local bus 206 may be made through direct component interconnection or through add-in connectors. In the depicted example, local area network (LAN) adapter 210, small computer system interface SCSI host bus adapter 212, and expansion bus interface 214 are connected to PCI local bus 206 by direct component connection. In contrast, audio adapter 216, graphics adapter 218, and audio/video adapter 219 are connected to PCI local bus 206 by add-in boards inserted into expansion slots. Expansion bus interface 214 provides a connection for a keyboard and mouse adapter 220, modem 222, and additional memory 224. SCSI host bus adapter 212 provides a connection for hard disk drive 226, tape drive 228, and CD-ROM drive 230. Hard disk drive 226 and CD-ROM drive 230 may use, for example, a serial advanced technology attachment (SATA) interface, or serial attached small computer system interface (SAS). Typical PCI local bus implementations will support three or four PCI expansion slots or add-in connectors.

An operating system runs on processor 202 and coordinates and provides control of various components within data processing system 200 in FIG. 2. Instructions for the operating system, the object-oriented programming system, and applications or programs are located on storage devices, such as hard disk drive 226, and may be loaded into main memory 204 for execution by processor 202. The processes of the present invention are performed by processor 202 using computer implemented instructions, which may be located in a memory such as, for example, main memory 204, additional memory 224, or in one or more peripheral devices.

Those of ordinary skill in the art will appreciate that the hardware in FIGS. 1-2 may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash memory, equivalent non-volatile memory, or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in FIGS. 1-2. Also, the processes of the present invention may be applied to a multiprocessor data processing system.

In some illustrative examples, data processing system 200 may be a personal digital assistant (PDA), which is configured with flash memory to provide non-volatile memory for storing operating system files and/or user-generated data. A bus system may be comprised of one or more buses, such as a system bus, an I/O bus and a PCI bus. Of course the bus system may be implemented using any type of communications fabric or architecture that provides for a transfer of data between different components or devices attached to the fabric or architecture. A communications unit may include one or more devices used to transmit and receive data, such as a modem or a network adapter. A memory may be, for example, main memory 204 or a cache memory. A processing unit may include one or more processors or CPUs. The depicted examples in FIGS. 1-2 and above-described examples are not meant to imply architectural limitations. For example, data processing system 200 also may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a PDA.

The different embodiments of the present invention provides a method and system that allows data following a steady state stream of bits to be time skewed by the transmitter so that the data is received by the receiver when expected. A steady state stream as herein defined is either a stream of logic high, 1, or logic low, 0, bits that come consecutively in the form of an extended pulse or stream of consecutive bits. Depending on the applicable transmission protocol or rule, the maximum number of steady state bits in a single group varies. The number of bits that must be skewed by the transmitter and the skew amount depends on the number of steady state bits transmitted and their relation to the transition from the steady state stream. High frequency bits following the steady state bits are herein referred to as transition bits. Variable transition timing establishes the amount each transition bit should be skewed, based on a training sequence between the transmitter and receiver in order to reduce the effective jitter and timing delay seen at the receiver. The present invention is particularly applicable to gigahertz serial data transmissions.

FIG. 3 is a block diagram of a transmitter and receiver system in which aspects of the present invention may be implemented. Transmitter 302 and receiver 304 are interconnected by conductor 306. In illustrative embodiments of the present invention, any number of host and target combinations may be used for transmitter 302 and receiver 304. For example, transmitter 302 may be any of a host bus adapter (HBA), root complex, Ethernet host, a Fibre switch, or other transmitting host. The receiving device may be a host bus adapter, expander, peripheral component interconnect (PCI) express device, Ethernet target, Fibre switch, or other receiving target. Transmitter 302 may be integrated or interconnected with a bus interface such as PCI bridge 208 of FIG. 2, and receiver 304 may be an expander or host bus adapter such as SCSI host bus adapter 212 of FIG. 2.

Transmitter 302 and receiver 304 may be used to interconnect any number of devices. For example, transmitter 302 and receiver 304 may indirectly interconnect a processor of a computer with a high-speed disk drive by means of a serial cable. Other types of drives may send and receive data using the method of transmitter 302 and receiver 304 herein described. In another example, conductor 306 may be a backplane of a motherboard connecting embedded or module components.

In one embodiment of the present invention, transmitter 302 and receiver 304 may establish a link wherein transmitter 302 and receiver 304 can communicate with one another. The link is used to train transmitter 302 to send a modified signal in order to reduce the timing effects of intersymbol interference and errors at receiver 304. Receiver 304 analyzes the time differential or delta from the ideal delay in receiving bits after a steady state stream of bits. Receiver 304 may use various techniques to analyze the time delay and received bits including using a phase-locked loop and oversampling. This data may be relayed back to the transmitter in order to compensate by phase shifting or transmitting the bits earlier than expected. Receiver 304 may analyze the transmitted signal to quantify parameters such as eye-diagram openings, edge-speeds, and power or voltage levels in order to instruct transmitter 302 how to send a signal with a low bit-error-ratio. Receiver 304 may receive and interpret data so long as minimum signal performance parameters are met.

The training sequence or link preferably occurs before any operating system is even aware of the sequence. For example, most transmission protocols utilize some type of out-of-band (OOB) sequence to establish a connection at device start up. The out-of-band sequence typically involves speed negotiation if the different devices are capable of multiple speeds. Once a link is established between devices at start up, there is typically a relatively large dead time during which the devices are waiting for the operating system to boot and other systems to initialize. It is during this unused start up time when only idle data is being transferred between connected devices that a training sequence may occur.

In an illustrative embodiment, a training sequence may occur even if receiver 304 is unaware or unable to participate. For example, most high-speed serial receivers 304 implement protocols that provide a hardware error recovery method and signal that signals back to transmitter 302 that the data just sent was improperly received and that the data needs to be resent. Transmitter 302 may modify and compensate for the timing effects of intersymbol interference based on the error message from receiver 304. In another illustrative embodiment, the serial communications between transmitter 302 and receiver 304 are full duplex allowing each to compensate for the effects of intersymbol interference during start up or at any time.

In many cases, communications standards, transmission protocols, or encoding schemes such as 8b10b are used to govern serial transmissions. 8b10b is an industry standard data transfer protocol for serial links established by the Institute of Electronics and Electrical Engineers (IEEE) as IEEE 802.3 §36.2.4. 8b10b specifies that information to be transmitted across a physical link, such as conductor 306, is encoded eight bits at a time into a 10-bit transmission character and then transmitted serially bit by bit across the link. Information received over the link is collected ten bits at a time and those transmission characters that are used for data, called data characters, shall be decoded into the correct eight bit codes. The encodings defined by the transmission code ensure that sufficient transitions are present in the serial bit stream to make clock recovery possible at the receiver. Such encodings also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. For example, in the case where the 8b10b standard is applicable, the maximum stable data stream is set at five bit times. The stable data stream or steady state stream is a portion of a data signal in which the signal is logic high or logic low for two or more data bits or is high or low for sufficient time to charge or discharge the parasitic capacitance of the transmission line. For example, under the 8b10b standard the steady state stream could be high for a maximum of five bits before a transition must necessarily occur.

As a result, transmitter 302 and receiver 304 only need to adjust for steady state streams of between two to five bits. In most cases, the effects of intersymbol interference clear up by the third pulse, and as a result, the variable timing following a steady state bit stream only needs to be done for three bits.

FIG. 4 is a prior art circuit model for analyzing a transmission line. In transmission line 400, series resistors 402 represent the direct current (DC) resistance of conductors 404, while inductors 406 and capacitors 408 represent the alternating current (AC) reactance of transmission line 400. Conductors 404 as herein defined is any wire, path, trace, backplane, etch, pad, channel, medium, or material that allows an electric data transmission to pass through it in the form of transmission line 400. The parallel capacitance of capacitors 408 and series inductance of inductors 406 are parasitic effects inherent in all transmission lines, due to their design, construction, and imperfections.

Any transmission line 400 will have a degrading effect on high-speed serial data streams. Furthermore, the longer transmission line 400, the more these effects add up. Intersymbol interference becomes an increasingly difficult issue because of parasitic capacitance from capacitors 408.

FIG. 5 is a prior art simplified circuit model for analyzing a transmission line. Transmission line 500 has series resistance within conductors 502 represented by resistor 504 and parallel capacitance represented by capacitor 506. Intersymbol interference becomes an issue when a signal stays at one level for a long time previously described as a steady state stream. The length of time is longer relative to the resistance-capacitance (RC) time constant of transmission line 500 defined by the parasitic effects of resistor 504 and capacitor 506. The resistance-capacitance time constant characterizes the frequency response of a resistance-capacitance circuit and is associated with the time required for an instrument, a receiver in this case, to indicate a given percentage of the final reading resulting from an input signal such as a transmitter. Using circuit analysis for this model of the transmission line will arrive at a differential equation, that when solved, gives the following equation:
V=Vo−Vs[1−eˆ(−t/RC)]

Vs is the supply voltage, Vo is the initial voltage, t is time, and RC is defined as the time constant for an RC network. As a steady state stream is transmitted across transmission line 500, capacitor 506 charges or discharges so that when subsequent high frequency bits are transmitted, the received bits have a reduced signal amplitude and time delay. Transmission line 400 and 500 of FIG. 4 and FIG. 5 respectively are conductors such as conductor 306 of FIG. 3.

FIG. 6 is a block diagram of a transmitter in accordance with an illustrative embodiment of the present invention. In transmitter 600, transmit first in first out (FIFO) 602 is a transmit buffer. Transmit FIFO 602 receives parallel data which it buffers before passing the parallel data on to shift register 604. Shift register 604 converts the parallel data into a serial stream which is fed to differential transmitter 606. Serial data is fed to differential transmitter 606 based on a clock which comes from multi-phase clock module 608.

An illustrative embodiment of the present invention optimally selects the phase of the clock data transmission by picking the buffer tap point using multiplexer 610. The buffer tap point is picked based on hardware pre-skew logic 612. Hardware pre-skew logic 612 analyzes parallel data being passed from transmit FIFO 602 to shift register 604 in order to determine which bits require pre-skew. For example, a steady state stream of logic high bits followed by a number of high frequency bits may require that the high frequency bits following the steady state stream be pre-skewed. Hardware pre-skew logic 612 instructs multi-phase clock module 608 to skew the phase of the clock for selected bits by selecting the appropriate control line to multiplexer 610.

In another illustrative embodiment, hardware pre-skew logic 612 and multi-phase clock module 608 run at twice the speed of a clock going to differential transmitter 606 in order to allow hardware pre-skew logic 612 sufficient time to phase shift the transmit clock. Transmitter 600 may be integrated or connected to a bus interface such as PCI Bridge 208 of FIG. 2.

FIG. 7 is a block diagram of a receiver in accordance with an illustrative embodiment of the present invention. In receiver 700, clock recovery unit 702 recovers the clock from the incoming signal. Clock recovery unit 702 may be a phase-locked loop or oversampling device.

Once a clock is recovered from the incoming signal, word synchronization logic 704 looks for special characters which separate and define words within the transmitted bits. A word is a fixed-sized group of bits that are handled together by the machine. For example, “k” characters within the transmitted signal may be used by word synchronization logic 704 to acquire word synchronization.

Once the data bits have been synchronized into words, the data moves into elasticity buffer 706 where buffering characters can be removed in order to match the speed of incoming data with the clock of receiver 700 as received from clock recovery unit 702. Data is passed from elasticity buffer 706 to shift register 708 which converts the modified serial stream back into a parallel stream before passing it to a different layer for data decoding and error handling. Receiver 700 may be an expander or host bus adapter such as PCI Bridge 208 of FIG. 2.

FIG. 8 is a timing diagram of a received signal due to intersymbol interference and an ideal clock in accordance with an illustrative embodiment of the present invention. Received data 800 is shown as received and without any emphasis or other compensation. In one example, received data 800 is shown with steady state stream 802 of logic high bits followed by a number of high-frequency data bits. As previously described, intersymbol interference can affect the amplitude and timing of transmitted data bits. For example, the amplitude of data bit 804 and data bit 806 are less than the ideal level. Additionally, data bit 804 and data bit 806 are delayed by interference so that they are received by the receiver later than expected based on an ideal signal and ideal clock 808. Received data 800 is more prone to errors because of time shift and reduced amplitude.

In order to function properly, the receiver must know when to decide whether a bit is a logic 0 or a logic 1. Timing is most critical. The decision is most appropriately made at the center of the bit period where the signal is most stable and not at the data edge where the signal is rising or falling. If the decision occurs near the transition or signal edge, the likelihood of a bit error increases substantially. Bit-errors are more likely to occur when a time delay results in bits, such as data bit 804 and data bit 806 arriving late.

In serial streams, ideal clock 808 extracted from the incoming data stream is used to tell the receiver when to decide whether a bit is a logic 0 or a logic 1. Receivers may use various forms of clock-extraction circuitry and methods. In one example, the receiver uses a phase-locked loop (PLL) to recover the ideal clock timing information from the serial data stream. A voltage-controlled oscillator (VCO) or current controlled oscillator initially runs at a frequency close to the expected data rate. Part of the signal from the voltage-controlled oscillator is routed to a phase detector, which compares the phase of the voltage-controlled oscillator signal with the incoming data stream. If the voltage-controlled oscillator is not at the same rate as the data signal, the phase detector will produce an error signal that is proportional to the frequency difference. The error signal is used as a controlling signal at the voltage-controlled oscillator to adjust its frequency and force the voltage-controlled oscillator to match, or lock to, the incoming data signal. The receiver circuit now has the critical capability of timing its decision circuit at exactly the rate of the data and in the center of the pit period for optimal bit-error-rate performance. The exemplary timing diagram illustrated in FIG. 8 may occur between communicating devices, such as transmitter 302 and receiver 304 in FIG. 3.

FIG. 9 is a timing diagram of transmitted data 900 with time shifted bits compensating for intersymbol interference, received data 902, and ideal clock 904 in accordance with an illustrative embodiment of the present invention. The transmitter has been trained by the receiver to transmit a signal that is properly modified for interference so that a more accurate signal is received at the receiver. As previously shown, an exemplary steady state stream of bits 906 is followed by a number of high frequency data bits or transition bits. Bits 908, 910, and 912 are optimally time shifted or skewed so that they are sent by the transmitter earlier than expected. Because of the parasitic effects of the transmission line, bits 908, 910, and 912 arrive and are read by the receiver when expected. In this example, transmitted data 900 and particularly bits 908, 910, and 912 are not modified for emphasis but instead are time shifted. The amount of phase shift that is applied to each bit is a variable transition time and may vary from bit to bit. For example, bit 908 may be time shifted 15 nanoseconds with bit 910 time shifted 12 nanoseconds and bit 912 time shifted 10 nanoseconds early. Bits 908, 910, and 912 have a reduced amplitude because of the amplitude effects of intersymbol interference when transmitted and received but are transmitted so that received data 902 is received with proper timing for bit and clock extraction from the transmitted signal.

Because transmitted data 900 is modified, the present invention allows the receiver to recover a more ideal clock from the data stream. Additionally, the receiver does not have to employ any additional intelligence or complex receiver algorithms to extract bits from the transmitted signal which cost money in development time, implementation, and processing resources. The exemplary timing diagram illustrated in FIG. 9 may occur between communicating devices, such as transmitter 302 and receiver 304 in FIG. 3.

FIG. 10 is a timing diagram of transmitted data 1000 with emphasis and time shifted bits compensating for intersymbol interference, received data 1002, and ideal clock 1004 in accordance with an illustrative embodiment of the present invention. In this example, steady state data 1006 is transmitted with emphasis shown by decreasing signal amplitude. This reduces the charging effect of the parasitic capacitance so that data bits 1008, 1010, and 1012 in received data 1002 reaches the optimal voltage amplitude more quickly. The exemplary timing diagram illustrated in FIG. 10 may occur between communicating devices, such as transmitter 302 and receiver 304 in FIG. 3.

FIG. 11 is a flowchart illustrating the operation of a system for training a transmitter to transmit a signal with proper time skew in accordance with an illustrative embodiment of the present invention. The process or logic of FIG. 11 may be implemented in a transmitting host such as transmitter 302 of FIG. 3. The training link or training sequence described occurs between the transmitter and receiver or host and target. In one example, the training sequence may occur after the amplitude and emphasis settings are optimized. The process begins as an out-of-band sequence and is established with the host (step 1100). A target is operably connected to a host and the host begins to transmit idle data correctly (step 1102). The host and target are interconnected by a conductor so that a signal may be transmitted and received between them.

Next, the host begins to transmit data with excessive late skew (step 1104). The data is skewed incrementally so that the data is sent just slightly late initially. By sending the data later than expected, the host is able to simulate the timing delays of intersymbol interference. The host then determines whether an error has been received (step 1106). If an error has not been received in step 1106, the host begins to transmit data with late skew (step 1104). Each time step 1104 is repeated, the skew value increases until an error is received (step 1106).

Once an error is received in step 1106, the host begins to transmit data normally (step 1108) to allow the target to recover. Next, the host begins to transmit data with excessive early skew (step 1110). The data is skewed incrementally so that the data is sent just barely early initially. By sending the data earlier than expected, the host is able to determine at what threshold the skewed data will cause errors in the target device. The host then determines whether an error has been received (step 1112). If an error has not been received in step 1112, the host begins to transmit data with early skew (step 1110). Each time step 1110 is repeated, the skew value increases incrementally until an error is received (step 1112).

Once an error is received in step 1112, the host begins to transmit data normally (step 1114). The host then sets pre-skew values (step 1116). The pre-skew values are based on the skewing steps and the host knows the limits of the receiver based on the late and early skew values required to induce errors from the target device.

The training sequence preferably covers all potential transmitting and receiving conditions that are susceptible to intersymbol interference. The test data stream will preferably include steady state streams of logic high and logic low with different pulse lengths and the worst case transmissions for inducing intersymbol interference. For example, one bit sequence used withint the training sequence used to evaluate the time effects of intersymbol interference may be the maximum length logic high steady state stream allowed by the transmission protocol followed by a series of high frequency bits. By analyzing the received data and noting the late and early settings, adjustments can be made to the variable transition time to optimize the timing for transition bits. This allows transmitted data bits and the clock to be more effectively extracted from the received signal.

For example, the process described in FIG. 11 may be implemented by time shifting data bits such as bits 908, 910, and 912 of FIG. 9. The transition bits are time shifted so that these bits are sent by the transmitter earlier than expected. Because of the timing effects of intersymbol interference on the transmission line, the transition bits arrive when expected. As a result, the ideal clock is more easily extracted, words within the stream are better defined, and the receiver knows when to make to accurately determine whether a bit is logic high or logic low according to the ideal clock. Each bit determination is best sampled in the middle of the bit where the signal tends to be more stable rather than at the bit edges.

FIG. 12 is a flowchart illustrating the operation of a receiver in accordance with an illustrative embodiment of the present invention. The process begins as an out-of-band sequence established with the host step 1200). The target transmits idle data to the host (step 1202). The target must then determine whether the data is properly received (step 1204). If the data is properly received in step 1204, the target transmits idle data to the host (step 1202). If the data is not properly received in step 1204, the target indicates a problem has occurred and continues to send idle data (step 1206). The process then returns to step 1204 and the target must then determine whether the data is properly received (step 1204). The process or logic of FIG. 12 may be implemented in a target receiver such as receiver 302 of FIG. 3.

The invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc.

Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any tangible apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk—read only memory (CD-ROM), compact disk—read/write (CD-R/W) and DVD.

A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers.

Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.

The description of the preferred embodiment of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention the practical application to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A method for reducing timing effects of intersymbol interference in a high-speed data transmission, comprising the steps of:

establishing a training sequence between a transmitter operably connected by a conductor to a receiver;

analyzing data received at the receiver;

skewing the timing of transition bits sent following a stable data stream by the transmitter; and

responsive to analyzing data received at the receiver, adjusting a variable transition time for the transition bits by the transmitter to optimize timing and reduce timing effects of intersymbol interference.

2. The method of claim 1, wherein analyzing step comprises sending an error message when transmitted data is improperly received at the receiver.

3. The method of claim 1, wherein the method is performed automatically by the transmitter and receiver in order to minimize the effect of intersymbol interference.

4. The method of claim 1, wherein the analyzing step comprises analyzing a time differential in order to calculate a bit time delay for the transition bits.

5. The method of claim 1, wherein the skewing step comprises sending the transition bits later than expected until bit errors occur.

6. The method of claim 1, wherein the skewing step comprises sending the transition bits earlier than expected until bit errors occur.

7. The method of claim 1, wherein the adjusting step comprises sending the transition bits earlier than expected based on information from the analyzing step to compensate for a delay in timing due to intersymbol interference so that the receiver recovers a more ideal clock from the serial data transmission.

8. The method of claim 1, further comprising optimizing amplitude and emphasis settings to reduce timing effects of intersymbol interference.

9. The method of claim 1, wherein the establishing step occurs during a start up sequence of the transmitter and receiver.

10. The method of claim 1, further comprising analyzing data and adjusting variable transition timing during the normal operation of the transmitter and receiver.

11. The method of claim 1, wherein the adjusting step comprises adjusting the variable transition time for three transition bits following the steady state stream.

12. The method of claim 1, comprising sending actual data with optimized variable transition timing from the transmitter to the receiver after the training sequence has been completed.

13. A system for reducing intersymbol interference in a serial data transmission, comprising:

a transmitter for transmitting data bits, wherein the transmitter skews transition bits following a steady state stream of bits during a training sequence to induce errors, and adjust variable transition timing for transition bits following the steady state stream of bits for a data signal; and

a receiver operably connected to the transmitter by a conductor, wherein the receiver analyzes bits transferred from the transmitter during the training sequence, and instructs the transmitter how to adjust the variable transition timing for transition bits in order to minimize the timing effects of intersymbol interference.

14. The system of claim 13, wherein a communication standard establishes a maximum number of bits making up the steady state stream of bits.

15. The system of claim 13, wherein the conductor for conveying a signal is any of a wire, path, trace, backplane, etch, pad, and channel.

16. The system of claim 13, wherein the receiver is operably connected to a drive.

17. The system of claim 13, wherein the transmitter includes pre-skew logic for skewing the phase of a transmitting clock in order to adjust the variable transition timing.

18. A computer program product comprising a computer usable medium including computer usable program code for reducing the timing effects of intersymbol interference in a high-speed data transmission, said computer program product comprising:

computer usable program code for establishing the training sequence between a transmitter and a receiver operably connected by a conductor, wherein the transmitter transmits data;

computer usable program code for skewing timing of transition bits; and

computer usable program code for modifying the variable transition time for the transition bits of data in order to optimize timing and minimize intersymbol interference of the data when received by the receiver.

19. The computer program product of claim 18, comprising:

computer usable program code, for analyzing data received at the receiver; and

computer usable program code for instructing a transmitter to adjust a variable transition time for transition bits by skewing the timing in order to optimize timing and minimize timing effects of intersymbol interference.

20. A computer program product of claim 18, further comprising:

computer usable program code for skewing the transition bits early and late until an error is induced in the receiver for the transmitter optimally adjust the variable transition time.