High density direct connect loc assembly
An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternately, a connector may contact a portion of the conductive trace to make contact therewith.
This application is a divisional of application Ser. No. 11/109,133, filed Apr. 5, 2005, pending, which is a continuation of application Ser. No. 10/366,769, filed Feb. 14, 2003, now U.S. Pat. No. 6,882,033, issued Apr. 19, 2005, which is a continuation of application Ser. No. 09/649,803, filed Aug. 28, 2000, now U.S. Pat. No. 6,531,761, issued Mar. 11, 2003, which is a divisional of application Ser. No. 09/026,839, filed Feb. 20, 1998, now U.S. Pat. No. 6,335,225, issued Jan. 1, 2002.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to an apparatus and method for attaching a semiconductor die to a lead frame or other type of connector. More particularly, the present invention relates to relocating electric contact points of a semiconductor die to the periphery of the semiconductor die through a plurality of conductive traces. The leads of the lead frame extend over the conductive traces proximate the semiconductor periphery and directly attach to and make electrical contact with the conductive traces in a variety of arrangements or configurations. Alternately, a connector may be used to contact a portion of the end of a conductive trace located at the periphery of a semiconductor die.
2. State of the Art
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are goals of the computer industry. Greater integrated circuit density is primarily limited by the space or “real estate” available for mounting a semiconductor die on a substrate such as a printed circuit board. Conventional lead frame design inherently limits package density for a given semiconductor die size because the die-attach paddle of the lead frame must be larger than the die to which it is bonded. The larger the semiconductor die, the less space that remains around the periphery of the die-bonding pad for wire bonding. Furthermore, the wire bonding pads on the standard lead frame provide anchorage for the leads when the leads and the semiconductor die are encapsulated in plastic. Therefore, as the die size is increased in relation to a given package size, there is a corresponding reduction in the space along the sides of the package for the encapsulating plastic which joins the top and bottom of the plastic body at the mold part line and anchors the leads. Thus, as the leads and encapsulant are subjected to the normal stresses of subsequent forming and assembly operations, the encapsulating plastic may crack, compromising package integrity and substantially increasing the probability of premature device failure.
Also, since lead frames are designed for use with a semiconductor die having a specific pattern of bond pads located on the active surface thereof, it is desirable to have the flexibility of changing the bond pad locations of a die so that an existing lead frame design may be used with differing types of die material.
For example, one method of chip attachment which reduces the die size is a so-called “leads-over-chip” (“LOC”) arrangement. Conventional LOC devices have a plurality of leads disposed on and attached to an active surface of a semiconductor die, thus the name leads-over-chip. A primary advantage of LOC is that the ratio between the size of the semiconductor die and the size of a package which encapsulates the semiconductor die is high. This advantage is achieved because the die-attach paddle is not required since the semiconductor die is instead attached to the leads.
U.S. Pat. No. 4,862,245 issued Aug. 29, 1989 to Pashby et al. (“the '245 patent”) illustrates a LOC arrangement on a semiconductor die (see
U.S. Pat. No. 5,252,853 issued Oct. 12, 1993 to Michii illustrates a LOC arrangement on the semiconductor die which does not use bond wires (see
Therefore, it would be advantageous to develop a technique and a device for increasing integrated circuit density by reducing lead width and reducing bond pad size, using non-complex lead frame configurations and eliminating bond wires, while using commercially available, widely practiced semiconductor device fabrication techniques.
BRIEF SUMMARY OF THE INVENTIONThe present invention relates to an apparatus and method for attaching a semiconductor die to a lead frame or other type of connector, such as a clip type. Electric contact points of the semiconductor die of the present invention are relocated to the periphery of a semiconductor die and are in electrical contact with a lead frame or connector. The semiconductor die may be in electrical contact with a lead frame through at least one lead which extends over and directly attaches to its respective electric contact point on the semiconductor die periphery, or through one lead which extends over and is attached to a die contact point with electrical contact being made to the electrical contact point of the die by means of a wire bond, or through one lead which extends adjacent the edge of a die with electrical contact being made to the electrical contact point of the die by means of a wire bond.
The apparatus is constructed by first forming a semiconductor die on a semiconductor wafer. A plurality of electric contact points, such as bond pads, is disposed on an active surface of the semiconductor die. A plurality of conductive traces is formed on the semiconductor die active surface to make a conductive route between each electric contact point and a position proximate to the semiconductor die periphery. A plurality of edge electric contact points may be formed on the periphery of the semiconductor die active surface during the formation of the conductive traces.
The conductive traces can be formed by a number of industry standard techniques, such as: depositing a conductive material on the active surface of the semiconductor die, patterning, and etching the conductive material; depositing a conductive paste on the semiconductor die active surface by silk screening the conductive traces directly thereon; directly extruding a conductive paste to form the conductive traces, or applying an insulative material on the semiconductor die active surface, etching a trough in the insulative material, filling the trough with a conductive material, and removing the excess material. These methods are less expensive than relocating the electric contact points during the semiconductor die fabrication process.
Although the formation of the conductive traces is preferably carried out on the semiconductor wafer, it is understood that the traces can be formed on each semiconductor die after the semiconductor dice have been cut from the semiconductor wafer.
After the electrical traces have been formed on the semiconductor die and the semiconductor die has been cut from the semiconductor wafer, a lead frame is attached to the semiconductor die. In one instance, a plurality of leads from the lead frame is attached directly to and forms an electrical contact with the edge electric contact points of the semiconductor die. The direct attachment of the leads eliminates the need for bond wires, which reduces the cost of the apparatus. In another instance, a plurality of leads from the lead frame is directly attached to the die with electrical contact being made to the contact points of the semiconductor die by means of wire bonds. In yet another instance, a plurality of leads from the lead frame are terminated adjacent an edge of the semiconductor die with electrical contact being made with contact points of the semiconductor die by means of connectors.
In one instance, since the present invention provides neither a die-attach paddle nor a plurality of lengthy leads to provide support for both the semiconductor die and attached lead frame, the semiconductor device fabrication technique for the semiconductor die of the present invention may have to be slightly modified over present semiconductor device fabrication techniques to ensure that no stresses on the lead frame attached semiconductor die occur prior to the encapsulation step. Such a fabrication technique modification may include providing clips on the lead frame to hold the semiconductor die. Although modifying the fabrication process is a disadvantage, the disadvantage is far outweighed by the benefits realized by the present invention. Since the leads are not required to provide support, they can be designed to be narrower in width. The narrower lead width allows the edge electric contact points to be smaller than relocated electrical contact points. The smaller edge electric contact points allow the semiconductor die size to be reduced or allow a greater number of edge electric contact points to be placed on the semiconductor die periphery. The narrower lead width also results in a smaller lead pitch which serves to reduce the cost of the apparatus. Furthermore, attachment of the leads at the semiconductor die periphery eliminates the need for a film-type alpha barrier between the semiconductor die and the lead, which further reduces the semiconductor die cost.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGSWhile the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings, in which:
Referring to drawing
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Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof.
Claims
1. A method of producing a semiconductor die from a wafer having a plurality of semiconductor dice, the method comprising:
- forming a semiconductor die having a periphery and an active surface having at least one electric contact point disposed on the active surface; and
- forming at least one conductive trace directly on the semiconductor die active surface, the at least one conductive trace comprising a first end electrically contacting at least a portion of the at least one semiconductor die electric contact point and a second end terminating proximate the semiconductor die periphery to expose a portion of the at least one conductive trace at a portion of the periphery of the semiconductor die, the at least one conductive trace formed by extruding a conductive material onto the semiconductor die active surface between the at least one electrical contact point making electrical contact therewith and the semiconductor die periphery to form the at least one conductive trace.
2. The method of claim 1, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- applying an extruded layer of viscous conductive material over the semiconductor die active surface, the viscous conductive material making electrical contact with the at least one semiconductor die electric contact point;
- applying a layer of etch resist material over the conductive material layer;
- masking and etching the etch resist material layer to form a trace pattern, the trace pattern extending from the at least one semiconductor die electric contact point to the semiconductor die periphery; and
- etching the conductive material layer to form the at least one conductive trace.
3. The method of claim 2, wherein forming the at least one conductive trace on the semiconductor die active surface further comprises stripping the etch resist material forming the trace pattern to expose the at least one conductive trace.
4. The method of claim 1, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- placing a silk screen over the semiconductor die active surface, the silk screen comprising a permeable portion in a shape of at least one desired conductive trace; and
- applying a substantially liquid viscous conductive material to the silk screen, the liquid viscous conductive material passing through the silk screen permeable portion to form the at least one conductive trace.
5. The method of claim 1, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- applying a layer of etch resist material over the semiconductor die active surface;
- masking and etching the etch resist material layer to form the at least one recessed conductive trace pattern exposing at least a portion of the at least one semiconductor die electric contact point and extending to the semiconductor die periphery; and
- disposing an extruded viscous conductive material within the at least one recessed conductive trace pattern to form the at least one conductive trace.
6. A method of producing a semiconductor die from a wafer having a plurality of semiconductor dice, the method comprising:
- forming a semiconductor die having a periphery and an active surface having at least one electric contact point disposed on the active surface; and
- forming at least one conductive trace directly on the semiconductor die active surface, the at least one conductive trace comprising a first end electrically contacting at least a portion of the at least one semiconductor die electric contact point and a second end terminating adjacent the periphery of the semiconductor die for exposing a portion of the at least one conductive trace at a portion of the periphery of the semiconductor die, the at least one conductive trace formed for an extruded conductive material onto the semiconductor die active surface at a location between the at least one electrical contact point making electrical contact therewith and the semiconductor die periphery to form the at least one conductive trace.
7. The method of claim 6, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- applying an extruded layer of viscous conductive material over the semiconductor die active surface, the viscous conductive material making electrical contact with the at least one semiconductor die electric contact point;
- applying a layer of etch resist material over the conductive material layer;
- masking and etching the etch resist material layer to form a trace pattern, the trace pattern extending from the at least one semiconductor die electric contact point to the semiconductor die periphery; and
- etching the conductive material layer to form the at least one conductive trace.
8. The method of claim 7, wherein forming the at least one conductive trace on the semiconductor die active surface further comprises stripping the etch resist material forming the trace pattern to expose the at least one conductive trace.
9. The method of claim 6, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- placing a silk screen over the semiconductor die active surface, the silk screen comprising a permeable portion in a shape of at least one desired conductive trace; and
- applying a substantially liquid viscous conductive material to the silk screen, the liquid viscous conductive material passing through the silk screen permeable portion to form the at least one conductive trace.
10. The method of claim 6, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- applying a layer of etch resist material over the semiconductor die active surface;
- masking and etching the etch resist material layer to form the at least one recessed conductive trace pattern exposing at least a portion of the at least one semiconductor die electric contact point and extending to the semiconductor die periphery; and
- disposing an extruded viscous conductive material within the at least one recessed conductive trace pattern to form the at least one conductive trace.
11. A contact formation method for a semiconductor die from a wafer having a plurality of semiconductor dice, the method comprising:
- forming a semiconductor die having a periphery and an active surface having at least one electric contact point disposed on the active surface; and
- forming at least one conductive trace directly on the semiconductor die active surface, the at least one conductive trace comprising a first end electrically contacting at least a portion of the at least one semiconductor die electric contact point and a second end terminating adjacent a portion of the periphery of the semiconductor die for exposing a portion of the at least one conductive trace at a portion of the periphery of the semiconductor die, the at least one conductive trace formed by extruding a conductive material onto the semiconductor die active surface between the at least one electrical contact point making electrical contact therewith and the semiconductor die periphery to form the at least one conductive trace.
12. The method of claim 11, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- applying an extruded layer of viscous conductive material over the semiconductor die active surface, the viscous conductive material making electrical contact with the at least one semiconductor die electric contact point;
- applying a layer of etch resist material over the conductive material layer;
- masking and etching the etch resist material layer to form a trace pattern, the trace pattern extending from the at least one semiconductor die electric contact point to the semiconductor die periphery; and
- etching the conductive material layer to form the at least one conductive trace.
13. The method of claim 12, wherein forming the at least one conductive trace on the semiconductor die active surface further comprises stripping the etch resist material forming the trace pattern to expose the at least one conductive trace.
14. The method of claim 11, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- placing a silk screen over the semiconductor die active surface, the silk screen comprising a permeable portion in a shape of at least one desired conductive trace; and
- applying a substantially liquid viscous conductive material to the silk screen, the liquid viscous conductive material passing through the silk screen permeable portion to form the at least one conductive trace.
15. The method of claim 11, wherein forming the at least one conductive trace on the semiconductor die active surface comprises:
- applying a layer of etch resist material over the semiconductor die active surface;
- masking and etching the etch resist material layer to form the at least one recessed conductive trace pattern exposing at least a portion of the at least one semiconductor die electric contact point and extending to the semiconductor die periphery; and
- disposing an extruded viscous conductive material within the at least one recessed conductive trace pattern to form the at least one conductive trace.
Type: Application
Filed: Dec 20, 2005
Publication Date: May 11, 2006
Inventor: Trung Doan (Boise, ID)
Application Number: 11/316,627
International Classification: H01L 21/50 (20060101);