Test card assembly
A space transformer and a method for making the space transformer. An electrically conductive material is placed in an inner region located in a silicon medium, the silicon medium defining both a first side and a second side at an outer region thereof Electrical contact is established between the electrically conductive material in the inner region and both the first side and the second side of the silicon medium at the outer region to provide double-sided electrical contacts for the space transformer.
The instant application is a Continuation Application of and claims the priority date of U.S. patent application Ser. No. 10/074,003 entitled “Silicon Space Transformer and Method of Manufacturing Same,” filed Feb. 14, 2002 and assigned to the assignee of the present invention.
BACKGROUND OF THE INVENTIONThe present invention generally relates to space transformers and to methods of manufacturing space transformers.
Before integrated circuits, such as those including microelectronic dies, are packaged in an electronic component, such as a computer, they must be tested. Testing is essential to determine whether a circuit's electrical characteristics conform to its design specifications.
In order to perform such testing, test card assemblies typically include three major components. The first component is a test card printed circuit board, the second component is a space transformer and the third component is a probe head. The test card printed circuit board is electrically coupled to a test system on a macro pitch scale, while the probe head is electrically coupled to a microelectronic die being tested, such as a semiconductor chip, on a micro pitch scale. The space transformer is the device that allows interconnection between the two physical scales mentioned above. The space transformer thus translates the macro pitch scale of the printed circuit board to the micro pitch scale of the probe head, providing electrical connection of these devices and enabling microelectronic dies to be tested by allowing signal and power/ground connections to be made. A space transformer may be used to probe either contact locations on a single microelectronic die, or contact locations on a silicon having a plurality of microelectronic dies thereon. Individual space transformers are generally produced by creating several such space transformers on a semiconductor wafer or substrate, using conventional processes such as deposition and photolithography. The space transformers are tested prior to singulating (separating) the wafer into individual space transformers.
Conventional space transformers are typically provided in the form of multi-layer substrates involving alternating layers of an insulating material, such as ceramic, and patterned layers of an electrically conductive material, such as copper. Existing technology for making space transformers generally involves the build-up of the necessary circuitry on ceramic, such a process requiring multiple deposition and a co-firing process. The known techniques for making space transformers are both costly and time consuming.
The prior art fails to offer a space-saving a space transformer that can be manufactured in a cost-effective and efficient manner.
BRIEF DESCRIPTION OF DRAWINGSThe present invention is illustrated by way of example and not limitation in the figures in the accompanying drawings in which like references indicate similar elements, and in which:
Embodiments of the present invention contemplate the use of silicon as a medium for space transformation. Silicon advantageously provides an identical coefficient of thermal expansion as the conventional silicon dies being tested. Space transformers of the prior art, however, such as those using ceramics as the substrate, disadvantageously present coefficients of expansion that are occasionally mismatched with respect to silicon dies that they are coupled to. In addition, working with silicon advantageously involves well-defined processes that do not require multiple co-firing steps as in the case of ceramics. The fabrication of silicon-based space transformers can be performed utilizing standard semiconductor fabrication equipment and processes. Ceramic processing, on the other hand, is typically very expensive, as ceramic itself is much more expensive than silicon. In addition, ceramic processing is relatively lengthy, since it requires that, for each layer of the space transformer, an amount of precursor material be applied then fired to form the ceramic, this process being known as co-firing.
Given the capabilities of existing semiconductor fabrication equipment, according to embodiments of the present invention, the generation of the device-level features on a space transformer using silicon and the development of the land grid array features on the transformer are simplified. Using silicon as the medium for space transformation reduces device thicknesses, radically reduces the cost and lead-time for the devices, and improves device reliability.
In the context of embodiments of the present invention, “land grid array” geometries refer to the size and spacing of surface features of the space transformer, typically measured in mils (10.sup.-3 inch) as opposed to semi-conductor geometries which are typically measured in microns. Conventional land grid array pads and spacing are at least an order of magnitude larger than semi-conductor pads and spacing. For example, typical pads for a land grid array might be, in a largest dimension thereof, between about 10 to 50 mils, with a pitch substantially equal to the pad size. However, typical pads for semiconductor devices might be between about 10 to 100 microns in their largest dimension, with a pitch substantially equal to about twice the pad size. The “largest dimension” mentioned above may, for example, be a diameter of a pad if the pad is circular, or a side dimension of the pad if the pad is square or rectangular. Ceramics are manufactured on an order of magnitude similar to that of circuit boards, that is, the metal and dielectric layers are mils in thickness. However, semi-conductors utilize metal and dielectric layers that are microns in thickness. Therefore, space transformers with a given number of layers in silicon can theoretically be about twenty five times thinner than their ceramic counterparts.
Device reliability is improved by manufacturing space transformers with silicon among other things because, while silicon processing is well understood and widely practiced, ceramic processing is less well understood and not nearly as widely practiced. The problems inherent in manufacturing reliable silicon devices are relatively well understood and are being addressed more readily than those inherent in manufacturing reliable ceramic devices.
According to an embodiment of the present invention, as will be described in further detail with respect to
It is to be noted that embodiments of the present invention are not limited to the provision of a plurality of vias in the silicon substrate, but that they include within their scope the provision of a single via as well, the number and configuration of vias being a function of the electrical contact configuration to be provided on the side of the space transformer where the vias are to be exposed.
Silicon has not been used to date as the medium for space transformers at least due to the inability of the silicon to provide double-sided electrical contacts. The use of the vias, the provision of a layer of an electrically conducting material such as copper on the silicon, and the selective etch back of the silicon to expose the copper at the bottom of the vias, enable the use of silicon as the medium for space transformers according to an embodiment of the present invention by providing double-sided electrical contacts on the silicon. By “double-sided electrical contacts,” what is meant in the context of embodiments of the present invention is that the medium used for the space transformer is provided with electrical contacts at a land grid array side thereof adapted to be coupled to a land grid array, and at another, die side thereof adapted to be coupled to the microelectronic die to be tested. At least some of the pads on the land grid array side are electrically coupled to at least some of the pads on the die side of the space transformer. Double-sided electrical contacts are essential for a space transformer to function. Although one embodiment of the present invention contemplates the use of copper to establish double-sided electrical contacts, it is to be understood that embodiments of the present invention encompass the use of other electrical conductors, such as, for example, aluminum.
Turning now to the drawings,
After creating the vias in the silicon wafer or space transformer medium 12, according to an embodiment of the present invention as depicted in
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Thus, according to one embodiment of the present invention, two-sided contact in a silicon wafer for a space transformer is established by providing an electrically conductive layer, such as a layer of copper, in between layers of silicon. Space transformers using ceramic material as their substrate are difficult and costly to manufacture, and, in addition, are bulky relative to silicon components. In addition, they disadvantageously tend to have different coefficients of expansion when compared with silicon, and thus tend to present problems in the testing of dies made of silicon. Embodiments of the present invention substantially eliminate the above problems of the prior art by providing a space transformer that uses silicon as its substrate, and that provides for double-sided electrical contact by creating a layer of an electrically conductive material within the silicon layers. The above may be achieved by laser drilling vias in a silicon wafer, depositing a layer of electrically conductive material, such as copper, in the wafer, building up the circuit for the space transformer, and thereafter thinning a back side of the built up wafer to expose pads of the electrically conductive material at the bottom of the vias with selective etch technology to allow for the silicon to provide the double-sided electrical contact typically seen in ceramic space transformers.
Embodiments of the present invention further encompass a space transformer comprising: a first silicon layer; a second silicon layer mounted to the first silicon layer; and means disposed in an inner region located between the first silicon layer and the second silicon layer for providing double-sided electrical contacts for the space transformer. An example of the means for providing comprises the layer of copper 8 shown in
The invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident to persons having the benefit of this disclosure, that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
Claims
1-17. (canceled)
18. A test card assembly comprising:
- a test card printed circuit board having first contacts thereon;
- a probe head having second contacts thereon; and
- a space transformer comprising:
- a silicon medium having a land grid array side and a semiconductor side opposite the land grid array side; and
- a predetermined contact pattern comprising electrically conductive material disposed in an inner region of the silicon medium and defining electrical contact zones providing double-sided electrical contacts for the space transformer, the contacts comprising:
- land grid array side contacts disposed on the land grid array side of the silicon medium and having their largest dimension and their pitch in the order of mils to define a macro-pitch scale, the land grid array side contacts further being adapted to be connected to corresponding ones of the first contacts; and
- semiconductor side contacts disposed on the semiconductor side of the silicon medium and having their largest dimension and their pitch in the order of microns to define a micro-pitch scale, the semiconductor side contacts further being adapted to be connected to corresponding ones of the second contacts, the electrical contact zones further being disposed to convert a macro-pitch scale of the land grid array side contacts to the micro-pitch scale of the semiconductor side contacts.
19. The assembly according to claim 18, wherein the silicon medium comprises a first silicon layer and a second silicon layer, the contact pattern being disposed between the first silicon layer and the second silicon layer.
20. The assembly according to claim 18, wherein the second silicon layer defines at least one via therein, at least some of the electrically conductive material being located in the at least one via.
21. The assembly according to claim 18, further comprising an adhesion promoter disposed between the electrically conductive material and the first silicon layer.
Type: Application
Filed: Feb 14, 2006
Publication Date: Jul 27, 2006
Inventor: Warren Crippen (Mesa, AZ)
Application Number: 11/354,556
International Classification: H05K 1/03 (20060101); H05K 1/00 (20060101);