Coding of FPGA and standard cell logic in a tiling structure
A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.
1. Technical Field
The present invention relates in general to a field of logic design, and in particular to the partitioning and synthesis of field programmable gate array (FPGA) and standard cell logic. Still more particularly, the present invention relates to a method and system for dynamically shifting the boundary between FPGA and standard cell logic within a physically placeable block that can simultaneously hold both FPGA and standard cell elements
2. Description of the Related Art
Building computer logic takes many steps before the computer logic is physically manufactured. The logic designer typically uses synthesis tools, such as register transfer languages (RTL) such as Verilog® and VHDL (Very-high-speed-integrated-circuit Hardware Descriptor Language) to describe, design and document electronic circuits. A typical RTL file includes a description of the interfaces to the logic and its behavior.
Two types of devices that can implement logic are FPGA (Field Programmable Gate Arrays) and Standard Cell. FPGAs use a 2-dimensional array of logic cells that are programmable, such that the FPGA functions as a custom integrated circuit (IC) that is modified by program code. Thus, a same FPGA can be alternately programmed to selectively perform the function of many different logic circuits. Typically, the programming of the FPGA is persistent until re-programmed at a later time. The persistent nature may be permanent (e.g., by blowing fuses in gates) or modifiable (by storing the programming code in a programmable memory). Standard cell, on the other hand, is hard-wired logic that is not modifiable after it is manufactured. Although it does not have the flexibility of a FPGA, standard cells is usually much faster than FPGA. Furthermore, FPGAs typically have many more gates and logic components than standard cells, since only a part of the FPGA circuit is typically used in any selected
A tile is a physically placeable block that contains some portion of FPGA (0% to 100%) and another portion of standard cell (0% to 100°%). By having the technology vendor's library offer several variations of tiles, all of which have the same outline size but different portions of FPGA and standard cell, the designer can repartition logic with a tile and replace it during the physical design phase with an alternate tile that represents the new partition. In addition, the library preferably contains tiles of smaller and larger sizes that can be selected to implement the logic in the appropriate amount of area on the IC.
The above, as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
BRIEF DESCRIPTION OF DRAWINGSThe novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, where:
With reference now to
With reference now to
Unlike prior art RTL files in which only a single wire type (“wire”) was defined without regard to whether the design was targeted to FPGA or standard cell technology, the present invention defines multiple wire types, as shown in
Extension 302 (Swire) describes/defines a standard cell fixed wire, which cannot be modified to become an FPGA wire. Extension 304 (Fwire) describes/defines an FPGA wire, which cannot be modified to become a standard cell wire. Extension 306 (sFwire) describes an intermediate wire type, which, as described in more detail below, is an FPGA wire that can later be modified to become a standard cell wire. Extension 308 (fSwire) describes another intermediate wire type, which, as described below, is a standard cell wire that can later be modified to become an FPGA wire. Extension 310 (Sfwire) describes a standard cell wire, which can be modified to become an FPGA wire. Extension 312 (Fswire) describes an FPGA wire, which can be modified to become a standard cell wire.
With reference now to
Sfwire 310a is input into logic 2a, which is a standard cell logic. Also input into logic 2a is a control line (cntl3) identified and described as Sfwire 310b. Analogous to an FPGA logic, a standard cell logic can take only standard cell inputs. Logic 2a has an output at node2 identified and described as Fswire 312f, which is one of the inputs to FPGA logic 4. The other input to FPGA logic 4a is Fswire 312g, coming from the node3 output of standard cell logic 1. The output from logic 4 is the outbus identified/described as Sfwire 310c. Also shown in
As each of the wires shown in
The process shown in
Referring now to
The iterative process described above allows the logic designer to dynamically change the structure of the logic without manually having to delete wires and constructs from one RTL file (such as an FPGA file) and then re-building the deleted wires/constructs for the new logic in another RTL file (such as a standard cell file). The process described in
Claims
1-21. (canceled)
22. An array of placeable logic tiles, said array comprising:
- a plurality of placeable logic tiles, each of said plurality of placeable logic tiles having a same outline size by a different amount of field programmable gate array (FPGA) and standard cell logic, wherein a first placeable logic tile from said plurality can replace a second placeable logic tile from said plurality to effectively more a boundary between the FPGA and standard cell logic within the tile.
23. A set of placeable logic tiles comprising:
- a plurality of placeable logic tiles, each of said plurality of placeable logic tiles having a different outline size and a different amount of field programmable gate array (FPGA) and standard cell logic, wherein a first placeable logic tile can replace a second placeable logic tile of different outline size.
Type: Application
Filed: Mar 15, 2006
Publication Date: Aug 24, 2006
Inventors: Stanislav Bajuk (Colchester, VT), Jack Smith (South Burlington, VT), Sebastian Ventrone (South Burlington, VT)
Application Number: 11/375,891
International Classification: G06F 17/50 (20060101);