Method for producing a micromechanical device and a micromechanical device
A method for manufacturing a micromechanical device and a resulting micromechanical device are provided, the device having a substrate material, a membrane, and a cavity situated between the substrate and the membrane in a membrane cavity area. In this method, holes are first produced through the membrane in a first etching step, and the cavity is subsequently produced using a second etching step.
The present invention is directed to a method for producing a micromechanical device including a substrate and a membrane.
BACKGROUND INFORMATIONA micromechanical device in which the components and the substrate material are thermally insulated from one another, the device being manufactured by a bulk micromechanical process, is described in an article by D. Moser and H. Baltes, “A high sensitivity CMOS gas flow sensor on a thin dielectric membrane,” and in the journal Sensors and Actuators A 37-38 (1993), pp. 33-37. A complex front- and back-side process is required for this method. The membrane needed for thermal insulation, on which temperature sensors and heaters are situated, for example, is produced via a bulk micromechanical process from the back side. The membrane is structured using a wet chemical etching process, for example, with the aid of KOH. In doing so, the entire substrate must be etched in the area of the membrane starting from the back side, which results in long process times. Since wet chemical etching solutions attack the functional layers on the front side, the wafer must be embedded in an etching box to protect the front during the etching process. This conventional method involving the back-side process is therefore very complex and costly.
SUMMARYThe method and device according to the present invention have the advantage over the related art that a method in which only front-side processes are needed is provided for manufacturing the membranes. A surface micromechanical process (SMM) may therefore be used for the method and device according to the present invention. Furthermore, the method and device according to the present invention make it possible to provide thermal insulation between components on or in the membrane and the substrate material. Such components in or on the membrane may include temperature sensors and/or heating elements; however, any component whose manufacture is integratable in the manufacturing process of the device is possible and conceivable according to the present invention. Thermal insulation is needed in thermal sensors such as thermocouples, chemical sensors, and air mass sensors, for example. The method and device according to the present invention have the advantage over the related art that only surface micromechanical processes, i.e., only front-side processes, are needed for manufacturing the device. This makes complex back-side processes such as KOH etching using an etching box for structuring the membrane unnecessary. Particles and scratches on the front of the wafer are minimized or avoided due to the omission of the back-side processes in which the wafer must be turned over and deposited on the front side. A surface micromechanical sacrificial layer method is used for producing the thermal insulation according to the present invention, and the method has high selectivity both with respect to thermally insulating materials such as oxides and nitrides and with respect to metals. Silicon may be used as the sacrificial layer in the method according to the present invention. The area of the sacrificial layer is initially deep structured according to the present invention via a first (anisotropic) etching step, e.g., a DRIE (deep reactive ion etching) process, and it is subsequently fully etched laterally in a second (isotropic) etching step using, e.g., a XeF2, ClF3, BrF3 process in such a way that a cavity is formed underneath the membrane. A membrane cavity area, i.e., the substrate area in which the membrane layer is unsupported and thus spans the cavity, is thus formed. According to the present invention, the membrane layer includes a thermally poorly conductive material, for example, silicon oxide or silicon nitride. The combined sacrificial etching layer process of the present invention makes it possible to produce thick sacrificial layers. The compatibility of the etching media used in the sacrificial layer etching with the customary materials used in the standard CMOS processes makes it possible, according to the present invention, for the manufacture of the device according to the present invention and the manufacture of an integrated circuit (IC) using CMOS technology to be performed in an integrated manner, i.e., single manufacturing process (including a plurality of steps).
It is advantageous that the holes in the membrane are sealed after the second etching step, e.g., using a cover layer or a cap. This makes it possible to protect the structures, for example, during a subsequent sawing process. According to the present invention, a PECVD oxide layer or a spin-on glass layer or a combination of different layers is conceivable here as a sealing layer. A cap as a cover is also conceivable as a seal for the holes. It is furthermore advantageous that a component to be thermally insulated from the substrate material is produced on or in the membrane before the first etching step. As a result, no further steps for producing a component are needed after the second etching step, and thus no problems occur due to the fact that, for example, after the two etching steps there are holes in the membrane into which the material to be applied to the membrane may penetrate and the material may attack or damage the membrane from its back side. It is furthermore advantageous that the membrane is well insulated from the substrate material. This is achieved according to the present invention by a relatively great depth of the cavity which is provided in the membrane area over the substrate material. This results, via different heat transport mechanisms, in reduced heat transport from the membrane to the substrate material and thus good thermal insulation. It is furthermore advantageous that a silicon substrate or a SOI/EOI substrate (silicon-on-insulator/epipoly-on-insulator substrate), which may be monocrystalline, is provided as the substrate material. An SOI/EOI substrate according to the present invention is usable in an advantageous manner due to the fact that the oxide layer of the SOI/EOI substrate is used as a vertical etch stop during sacrificial layer etching, which makes it possible to set a defined sacrificial layer thickness. A SOI/EOI substrate is based on a layer structure in which an oxide layer and subsequently a silicon layer are applied to a monocrystalline silicon substrate.
All in all, the method according to the present invention allows simple manufacture of a device according to the present invention, e.g., sensor elements, in which thermal insulation between temperature sensors and/or heating elements and the substrate material is needed. According to the present invention, only a few layers and photolitographic steps are needed for carrying out the method according to the present invention, so that the method is implementable in a simple and cost-effective manner.
BRIEF DESCRIPTION OF THE DRAWINGS
Claims
1-12. (canceled)
13. A method for manufacturing a micromechanical device having a substrate material and a membrane layer provided on the substrate material, wherein a cavity is provided between the substrate material and the membrane layer in a membrane cavity area, comprising:
- providing holes in the membrane layer via a first anisotropic etching process; and
- providing the cavity via a second isotropic etching process.
14. The method as recited in claim 13, wherein a portion of the substrate material is provided as a sacrificial layer, and wherein, in the first anisotropic etching process, the holes are provided to extend into the sacrificial layer.
15. The method as recited in claim 14, wherein the method is CMOS-compatible.
16. The method as recited in claim 15, wherein the first anisotropic etching process includes a deep reactive ion etching.
17. The method as recited in claim 15, wherein the second isotropic etching process includes one of: a) use of one XeF2, ClF3, BrF3 and SF6 plasma; and b) a wet chemical etching using one of tetramethylammonium hydroxide, KOH, and a combination of HNO3 and HF.
18. The method as recited in claim 16, further comprising:
- sealing the holes in the membrane layer after the second isotropic etching process, using one of a cover layer placed directly on the membrane layer surface and a cover positioned over the membrane layer.
19. The method as recited in claim 18, further comprising:
- providing one of on and in the membrane layer, before the first anisotropic etching process, a component to be thermally insulated from the substrate material.
20. The method as recited in claim 17, further comprising:
- sealing the holes in the membrane layer after the second isotropic etching process, using one of a cover layer placed directly on the membrane layer surface and a cover positioned over the membrane layer.
21. The method as recited in claim 20, further comprising:
- providing one of on and in the membrane layer, before the first anisotropic etching process, a component to be thermally insulated from the substrate material.
22. A micromechanical device, comprising:
- a substrate material; and
- a membrane layer provided on the substrate material;
- wherein a cavity is provided between the substrate material and the membrane layer in a membrane cavity area, the cavity being provided by producing holes via a first anisotropic etching process in the membrane layer and a portion of the substrate material provided as a sacrificial layer and subsequently performing a second isotropic etching process, and wherein the first anisotropic etching process includes a deep reactive ion etching, and wherein the second isotropic etching process includes one of: a) use of one XeF2, ClF3, BrF3 and SF6 plasma; and b) a wet chemical etching using one of tetramethylammonium hydroxide, KOH, and a combination of HNO3 and HF.
23. The device as recited in claim 22, wherein the membrane layer is insulated thermally from the substrate material.
24. The device as recited in claim 23, wherein the substrate material is one of a silicon substrate and a silicon-on-insulator substrate.
25. The device as recited in claim 24, wherein the depth of the cavity substantially corresponds to the depth of the holes within the substrate material.
26. The device as recited in claim 24, further comprising at least one thermally insulated component provided one of on and in the membrane layer.
Type: Application
Filed: Sep 25, 2003
Publication Date: Oct 12, 2006
Inventors: Frank Fischer (Gomaringen), Lars Metzger (Moessingen-Belsen)
Application Number: 10/543,357
International Classification: C23F 1/00 (20060101);