GATE DIELECTRIC LAYER AND METHOD OF FORMING THE SAME
A method of forming a gate dielectric is described. A plasma treatment process is performed to form a dielectric structure on a substrate, wherein the dielectric structure having a graded dielectric constant value that decreases gradually in a direction toward the substrate.
1. Field of the Invention
The present invention generally relates to a fabrication process of semiconductors. More particularly, the present invention relates to a gate dielectric layer and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development in the Ultra-Large Scale Integration (ULSI) industry in recent years, circuit design is directed to a continuously reducing the size of devices. In order to increase the level of integration and the driving capacity, the line width of the gate is shorten and the thickness of gate dielectric layer is minimized correspondingly. In particular, as the semiconductor industry enters the era of deep submicron, the thickness of a gate dielectric layer is reduced from a couple hundred Å to about 40 Å. The fabrication of the gate dielectric layer in the ultra-Large Scale Integration (ULSI) technology is always an important matter. To produce an ultra thin gate dielectric layer with high quality while the process window is being reduced is an imminent problem to be resolved.
Applying thermal oxidation to fabricate a silicon oxide layer as a gate dielectric layer is well known in the art. However, pin holes are always present inside the structure of the silicon oxide layer leading to problems, such as the direct-tunnelling current . . . etc. Therefore, the aforementioned approach can not be used to form a thin gate dielectric layer. Other fabrication method known in the art includes performing a nitration treatment by introducing silicon nitride into a gate dielectric layer, which mainly contains silicon dioxide, to form a nitride oxide (NO) layer. The nitride oxide layer can reduce the leakage current and improve the reliability of the process. However, there are other problems existed with a stacked nitride oxide layer, formed with a silicon oxide layer and a nitride silicon layer, serving as a gate dielectric layer. For example, nitrogen atoms can easily diffuse through the interface between the silicon substrate and the silicon oxide layer during the nitration process to affect the efficiency and the stability of the devices. Besides, the interface between the silicon oxide layer and the silicon nitride layer can easily reduce the density of the trapped charges. Therefore, the efficiency and the stability of the devices are affected together with the reliability of the fabrication process.
SUMMARY OF THE INVENTIONBroadly speaking, the present invention is directed to a fabricating method for a gate dielectric layer, wherein the interface characteristics between the gate dielectric layer and the substrate, and the between the internal layers of the stacked gate dielectric layer are improved to improve the film layer qualities of the gate dielectric layer.
In accordance with one aspect of the present invention, a fabrication method for a gate is provided to improve the stability of the devices and the reliability of the fabrication method.
In accordance with another aspect of the present invention, a gate dielectric layer is provided to improve the quality of the dielectric layer and the liability of the fabrication method.
In accordance with yet another aspect of the present invention, a gate is provided to improve the stability of the devices and the reliability of the fabrication method.
The present invention provides a fabrication method for a gate dielectric layer, and the method includes performing a plasma process on the substrate to form a dielectric layer thereon, wherein the dielectric layer has a graded dielectric constant value that decreases towards the substrate.
According to an embodiment of the present invention, the above mentioned method further includes performing a thermal treatment process on the substrate after the plasma process.
According to an embodiment of the present invention, the above mentioned graded dielectric constant is between 3.9˜7.
According to an embodiment of the present invention, the above mentioned plasma process is operated at about 400° C.
According to an embodiment of the present invention, the above mentioned plasma process includes performing an oxygen-containing plasma process followed by a nitrogen-containing plasma process. Furthermore, the plasma process is conducted by adjusting the flow rate ratio of the reacting gas of the oxygen-containing plasma treatment process and the nitrogen-containing plasma treatment process to have the flow rate ratio increases from low to high. The above mentioned flow ratio for the reacting gas is between 0˜∞.
According to an embodiment of the present invention, the above mentioned plasma process is operated under a temperature of about 400° C.
According to an embodiment of the present invention, the surface of the above mentioned dielectric structure in contact with the substrate contains a higher concentration of the oxygen atoms than the nitrogen atoms.
According to and embodiment of the present invention, the top surface of the above mentioned dielectric layer contains a higher concentration of the nitrogen atoms than the oxygen atoms.
The present invention provides another fabrication method for a gate, and the method includes performing a plasma process on the substrate to form a dielectric layer thereon, wherein the dielectric layer has a graded dielectric constant value that decreases towards the substrate. The following process includes forming a conducting layer, and then defining the conducting layer structure to form a stacked gate structure.
According to an embodiment of the present invention, the above mentioned method further includes performing a thermal process after the plasma treatment process.
According to an embodiment of the present invention, the above mentioned graded dielectric constant is between 3.9˜7.
According to an embodiment of the present invention, the above mentioned plasma treatment process is initially conducted with an oxygen-containing plasma process, follow by a nitrogen-containing plasma process. Furthermore, the plasma treatment process is conducted by the adjusting the flow rate ratio of the reacting gases of the oxygen plasma treatment process and the nitrogen plasma treatment process to have the flow rate ratio to increase from low to high. The above mentioned flow rate ratio for the reacting gases is between 0˜∞.
According to an embodiment of the present invention, the above mentioned plasma process is conducted under a temperature of about 400° C.
According to an embodiment of the present invention, the contact surface between the above mentioned dielectric structure and the substrate contains a higher concentration of the oxygen atoms than the nitrogen atoms.
According to an embodiment of the present invention, the top surface of the above mentioned dielectric layer contains a higher concentration of the nitrogen atoms than the oxygen atoms.
According to an embodiment of the present invention, the above mentioned conducting layer is a polysilicon layer.
The present invention again provides another gate dielectric layer having a dielectric layer with a graded dielectric constant value that decreases towards the substrate.
According to an embodiment of the present invention, the above mentioned graded dielectric constant is between 3.9˜7.
According to an embodiment of the present invention, the surface of the above mentioned dielectric layer in contact with the substrate can be silicon oxide.
According to an embodiment of the present invention, the top surface of the above mentioned dielectric layer can be silicon nitride.
The present invention further provides another gate, which includes a substrate, a dielectric layer and a conducting layer. The dielectric layer has a graded dielectric constant value that decreases towards the substrate, and the conducting layer is disposed on the dielectric layer.
According to an embodiment of the present invention, the above mentioned graded dielectric constant is between 3.9˜7.
According to an embodiment of the present invention, the above mentioned conducting layer is polysilicon.
According to an embodiment of the present invention, the surface of above mentioned dielectric layer in contact with the substrate can be silicon oxide.
According to an embodiment of the present invention, the top surface of the above mentioned dielectric layer can be silicon nitride.
The present invention applies a plasma treatment process on the substrate to form a dielectric layer structure, wherein the quality of the interface between the dielectric structure and the substrate is desirable. Further, the quality of the internal film layer of the dielectric layer structure can be improved, in addition to improving the reliability of the fabrication process. Besides, the above mentioned plasma treatment process can be performed at a low temperature. No damages to the surface of the substrate will occur. Furthermore, the plasma treatment process includes an adjustment of the flow rate ratio of the reacting gases of the oxygen-containing plasma process and the nitrogen-containing plasma process, which can be conducted in the same operation chamber to concurrently save the queue-time and the fabrication cost.
Several exemplary embodiments of the invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the foregoing general description and the following detailed description of preferred purposes, features, and merits are exemplary and explanatory towards the principles of the invention only and are not restrictive of the invention, as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
Turning to
Thereafter, referring next to
In particular, the whole plasma treatment process 102 can be implemented under a low temperature; therefore no damages will be induced on the surface of the film layer on the substrate 100.
Besides, the above mentioned plasma treatment process 102 is adjusting the flow rate ratio of the reacting gases of the oxygen-containing plasma process and the nitrogen-containing plasma process from a low value to a high value. The above mentioned flow rate ratio for the reacting gases (N2/O2) is between 0˜∞. In one embodiment of the present invention, plasma treatment process 102 can be conducted in the same operation chamber for both the oxygen-containing plasma process and the nitrogen-containing plasma process to minimize the queue-time.
In another embodiment of the present invention, a thermal process can be conducted on the substrate 100 after the plasma processes 102, wherein the thermal process can be, for example, an annealing process to refine the pre-formed film layer and to enhance the quality of the layer.
Thereafter, continuing to
According to the above description, the material of the dielectric layer structure 104 that is adjacent to the substrate 100 is silicon oxide, which has better interface characteristics. The defects problems at the interface between the gate dielectric layer 104 and the substrate 100 can be resolved. In addition, the dielectric layer structure 104 can prevent any defects at the interface inside the dielectric layer structure (silicon oxide layer and silicon nitride layer) as often occurred in the prior art. In addition, the internal part of the dielectric layer structure 104 has a higher nitrogen content; therefore, the dielectric constant is higher.
As shown in
With reference to
In addition, the above mentioned structure for the gate is comprised of a dielectric layer structure 104a and a conducting layer 106a. The dielectric layer structure 104a is disposed on the substrate 100, and the dielectric layer structure 104a has a graded dielectric constant value that decreases towards the substrate 100. The conducting layer 106a is disposed on the dielectric layer structure 104a. The surface of the dielectric layer structure 104a in contact with the substrate 100 can be silicon oxide and the material of the surface of the dielectric layer structure 104a in contact with the conducting layer 106a can be silicon nitride.
According to above description, the dielectric structure 104 as the gate dielectric layer for the gate serves to decrease the equivalent oxide thickness (EOT) and avoid the degradation of the gate dielectric layer and an electrical breakdown. Furthermore, the reliability of the process is improved.
Turning to the
According to
Referring to
Turning to
Referring next to the
According to the above-mentioned description, the present invention can effectively reduce the equivalent oxide thickness. Further, the problem of leakage current of a device can be improved.
Accordingly, the present invention provides at least the following advantages.
1. The present invention effectively reduces the equivalent oxide thickness (EOT) of the gate dielectric layer without affecting the electrical characteristics of the device.
2. The plasma processes of the present invention will not damage the surface of the film layers and can be conducted in the same reaction chamber to reduce the queue-time and production cost.
3. The present invention improves the interface characteristics between the gate dielectric layer and the substrate, and the interface characteristics inside the film layers; therefore, the reliability of the process is also improved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims
1-19. (canceled)
20. A gate dielectric layer, comprising a single-layered dielectric layer structure, wherein the single-layered dielectric layer structure has a graded dielectric constant value that decreases from a top of the single-layered dielectric layer structure towards a bottom of the single-layered dielectric layer structure.
21. The gate dielectric layer as recited in claim 20, wherein the graded dielectric constant value is between 3.9˜7.
22. The gate dielectric layer as recited in claim 20, wherein a surface of the single-layered dielectric layer structure in contact with the substrate comprises silicon oxide.
23. The gate dielectric layer as recited in claim 20, wherein a top surface of the single-layered dielectric layer structure comprises silicon nitride.
24. A gate, comprising:
- a substrate;
- a single-layered dielectric layer disposed on the substrate, wherein the single-layered dielectric layer has a graded dielectric constant value that decreases toward the substrate; and
- a conducting layer disposed on the single-layered dielectric layer.
25. The gate as recited in claim 24, wherein the graded dielectric constant value is between 3.9˜7.
26. The gate as recited in claim 24, wherein a material constituting the conducting layer comprises polysilicon.
27. The gate as recited in claim 24, wherein a surface of the single-layered dielectric layer in contact with the substrate comprises silicon oxide.
28. The gate as recited in claim 24, wherein a surface of the single-layered dielectric layer in contact with the conducting layer comprises silicon nitride.
29. A gate dielectric layer, comprising a single-layered dielectric layer structure, wherein the single-layered dielectric layer structure has a graded oxygen-atom concentration increasing from the top of the single-layered dielectric layer structure toward the bottom of the single-layered dielectric layer structure and has a graded nitrogen-atom concentration decreasing from a top of the dielectric layer structure towards a bottom of the dielectric layer structure.
30. The gate dielectric layer as recited in claim 29, wherein the single-layered dielectric layer structure has a graded dielectric constant between 3.9˜7 from the bottom of the single-layered dielectric layer structure toward the top of the single-layered dielectric layer structure.
31. The gate dielectric layer as recited in claim 29, wherein a surface of the single-layered dielectric layer in contact with the substrate is made of silicon oxide.
32. The gate dielectric layer as recited in claim 29, wherein a top surface of the single-layered dielectric layer is made of silicon nitride.
33. The gate dielectric layer as recited in claim 20, wherein a ratio of nitrogen atoms to oxygen atoms (N2/O2) in the single-layered dielectric layer structure decreases from the top of the dielectric layer structure towards the bottom of the dielectric layer structure.
34. The gate as recited in claim 24, wherein a ratio of nitrogen atoms to oxygen atoms (N2/O2) in the single-layered dielectric layer decreases from the top of the dielectric structure towards the bottom of the dielectric structure.
Type: Application
Filed: Apr 6, 2005
Publication Date: Oct 12, 2006
Inventors: Po-Lun Cheng (Kaohsiung County), Li-Wei Cheng (Hsinchu City)
Application Number: 10/907,560
International Classification: H01L 29/94 (20060101);