High-Q digital active power factor correction device and its IC
A method for digitally processing high-quality active PFC includes a step of regulating PFC reference signal at a predetermined ending point of each cycle; wherein the cycle is integer multiple of the half cycle of the commercial power, and the ending point of the cycle is synchronized with the edge of the half cycle.
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This is a Divisional application of a non-provisional application having an application Ser. No. 10/510,198 and filing date of Sep. 29, 2004.
BACKGROUND OF THE PRESENT INVENTION1. Field of Invention
The present invention relates to switch power supply, and more particularly, relates to a kind of digital high-Q active power factor correcting (i.e. PFC) method, device and its IC.
2. Description of Related Arts
PFC (Power Factor Correction) could be classified into the single phase PFC and three phases PFC, CCM (Continuous Current Mode) PFC, DCM (Discontinuous Current Mode) PFC, boost PFC, boost/buck PFC converter, and flyback PFC converter. Further, there are constant frequency controlling techniques, constant conduction time controlling technique, and equal area control techniques associated with the DCM mode. And there are peak value current controlling technique, average current controlling technique, lag loop current controlling technique, hard switch and soft switch technique associated with the CCM mode.
Regardless what kinds of converter and switching circuits are being used, a PFC device generally comprises a converter circuit having one or more power tubes, a transformer or an induction, and an output circuit. In case of a soft switch is applied, at least one supplemental power tube and a soft switch circuit are employed. And in case of flyback converting mode is used, a transformer would be necessary.
The PFC device further comprises a feedback circuit having a sample circuit, an error amplifier wherein the sample circuit is adapted for sampling the current signal from the output circuit and then sending the sampled current signal to the error amplifier to generate an error signal.
The PFC further comprises a control circuit including an adjustable pulse circuit and a driven circuit, wherein the error signal is send to the adjustable pulse circuit and the driven circuit is adapted for driving the power tube. It is noted that there is a variety of adjustable pulse circuits available depending which kind of converter circuits and the controlling techniques being used. Commonly, the most used control circuits include constant conduction time control circuit (for example, UC3852, after the power tube is conducted, the induction current will be increased and the conduction time will be determined by the error signal outputted by the error amplifier, after the power tube is shut off, the induction current will be decreased; if the induction current is fallen down to zero, the power tube will be conducted again indicating that the circuit is performing at a transition point between DCM and CCM). Some popular control circuits also include average time control circuit (for example, UC3854 comprising a multiplicator, a current error amplifier, PWM, and an oscillator), flyback converter control circuit, soft switching control circuit, and so on.
Finally, the PFC device also comprises a supplemental circuit which is selected from a group consisting of initiating circuit, protective circuit, voltage reference circuit, EMC circuit, alternate rectifying filter circuit. To prevent the PFC outputting voltage being excess the upper limit, designers within the art have to balance the following factors, such as the outputting capacity of the capacitor, power factors, and total harmonic distortion. In other words, users have to sacrifice some factors to achieve a feedback function. For instance, when the circuit is under a heavy load, the power factor will be reduced and the total harmonic distortion will be accordingly increased. However, sacrifice could solve all troubles, in case of the outputting voltage excesses the design value, or the outputting is converted from a heavy load to a light load suddenly, the control circuit sometimes is unaware or unable to judge whether the outputting voltage being over the upper limit. This is due to some inherent factors of voltage error feedback and input voltage filter waves. As a result, there still exist potential risks in conventional PFC circuits.
SUMMARY OF THE PRESENT INVENTIONA primary object of the present invention is to provide a method for digitally processing high quality PFC.
Another object of the present invention is to provide a device for digitally processing high quality PFC as well as its IC.
Another object of the present invention is to provide a digital process and high quality PFC method, wherein a reference circuit and a PFC reference signal are applied for replacing the conventional feedback circuit and error signal. The reference circuit comprises a series of voltage signal sample circuit of the output circuit, voltage signal detection or module converter (A/D) circuit, reference logic circuit and reference output circuit. The reference logic circuit is adapted for digitally processing the voltage signal so as to generate a digital PFC reference signal, and for regulating PFC reference signal at a predetermined ending point of each cycle, wherein during each cycle, PFC reference signal is kept constant. Said cycle is integer multiple of the half cycle of the commercial power, and the ending point of said cycle is synchronized with the edge of said half cycle. Or, said cycle is much larger than said half cycle, and the ending point of said cycle is not synchronized with the edge of said half cycle. Or, said cycle is neither synchronized with the edge of said half cycle nor be much larger than said half cycle, but is required to have a relatively small adjusting volume with respect to PFC reference signal for satisfying IEC1000-3-2 and IEC1000-3-4 standards.
Accordingly, the present invention further provides a PFC device based on the above digital process and high quality PFC method, comprising:
a converter circuit having one or more power tubes, a transformer or an inductance, and an output circuit;
a reference circuit;
a control circuit having a pulse adjustable circuit and a driven circuit, wherein the PFC reference signal is feed into the pulse adjustable circuit for controlling a generation of a pulse; and
a supplemental circuit selected from a group consisting of initiating circuit, protective circuit, voltage reference circuit, EMC circuit and so on.
According to the present invention, the pulse adjustable circuit comprises a proportional current circuit, a timing circuit, a pulse width adjustable logic circuit, a current amplifier and an oscillator wherein the PFC reference signal is applied as the input of the proportional current circuit, a pair of proportional current of said proportional current circuit are send to said timing circuit, a pair of digital signal of said timing circuit are send to the pulse width adjustable logic circuit which in turn is adapted for outputting a pair of digital signal to said timing circuit, the output signal of the current amplifier is send to the timing circuit, the output signal from the oscillator is send to the pulse width adjustable logic circuit, finally the pulse width adjustable logic circuit will output a pulse signal. The different portion of the pulse adjustable circuit will be discussed in details later.
The PFC device of the present invention utilizes power factor to correct IC which comprises a portion of reference circuit and control circuit.
The digitally processing high quality PFC have distinguished characteristics and effects thus generating advantageous edge and quality, and will ultimately save the costs as well as improve the overall quality.
These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
Referring to the
As shown in
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As shown in
The logic unit generated from PFC current reference shown in
PFC shown in the
VA voltage signal detection shown in the
Accordingly, the digital processing PFC control circuit of the present invention has a desirable power factor and an ideal total harmonic distortion, and is deemed as a high quality PFC control circuit.
One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.
It will thus be seen that the objects of the present invention have been fully and effectively accomplished. It embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure form such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.
Claims
1. A method for digitally processing high-quality active PFC, comprising a step for regulating PFC reference signal at a predetermined ending point of each cycle; wherein said cycle is integer multiple of the half cycle of the commercial power, and the ending point of said cycle is synchronized with the edge of said half cycle.
2. The method, as recited in claim 1, wherein said cycle is much larger than said half cycle, and the ending point of said cycle is not synchronized with the edge of said half cycle.
3. The method, as recited in claim 1, wherein said cycle is neither synchronized with the edge of said half cycle nor be much larger than said half cycle, but is required to have a relatively small adjusting volume with respect to PFC reference signal for satisfying IEC 1000-3-2 and IEC 1000-3-4 standards.
4. A PFC device, comprising:
- a converter circuit having one or more power tubes, a transformer or an inductance, and an output circuit;
- a control circuit;
- a PFC reference signal, regulating PFC reference signal at a predetermined ending point of each cycle; wherein said cycle is integer multiple of the half cycle of the commercial power, and the ending point of said cycle is synchronized with the edge of said half cycle;
- a reference circuit, comprising a series of voltage signal sample circuit of an output circuit, a voltage signal detection circuit, a reference logic circuit and a reference output circuit, wherein PFC reference signal of said reference output circuit is send to said control circuit to generate a pulse; and
- a supplemental circuit.
5. The PFC device, as recited in claim 4, wherein said cycle is much larger than said half cycle, and the ending point of said cycle is not synchronized with the edge of said half cycle.
6. The PFC device, as recited in claim 4, wherein said cycle is neither synchronized with the edge of said half cycle nor be much larger than said half cycle, but is required to have a relatively small adjusting volume with respect to PFC reference signal for satisfying IEC 1000-3-2 and IEC 1000-3-4 standards.
7. A PFC IC, comprising:
- a PFC reference signal, regulating PFC reference signal at a predetermined ending point of each cycle; wherein said cycle is integer multiple of the half cycle of the commercial power, and the ending point of said cycle is synchronized with the edge of said half cycle; and
- a portion of a reference circuit, comprising a voltage signal detection circuit, a reference logic circuit and a reference output circuit, wherein PFC reference signal of said reference output circuit is send to the control circuit to generate a pulse.
8. The PFC IC, as recited in claim 7, wherein said cycle is much larger than said half cycle, and the ending point of said cycle is not synchronized with the edge of said half cycle.
9. The PFC IC, as recited in claim 7, wherein said cycle is neither synchronized with the edge of said half cycle nor be much larger than said half cycle, but is required to have a relatively small adjusting volume with respect to PFC reference signal for satisfying IEC1000-3-2 and IEC1000-3-4 standards.
10. The PFC IC, as recited in claim 7 or 8 or 9, further comprising a pulse adjustable circuit comprising a proportional current circuit, a timing circuit, a pulse width adjustable logic circuit, a current amplifier and an oscillator wherein the PFC reference signal is applied as the input of the proportional current circuit, a pair of proportional current of said proportional current circuit are send to said timing circuit, a pair of digital signal of said timing circuit are send to the pulse width adjustable logic circuit which in turn is adapted for outputting a pair of digital signal to said timing circuit, the output signal of the current amplifier is send to the timing circuit, the output signal from the oscillator is send to the pulse width adjustable logic circuit, finally the pulse width adjustable logic circuit will output a pulse signal.
Type: Application
Filed: Jul 18, 2006
Publication Date: Nov 16, 2006
Applicants: ,
Inventor: Weibin Chen (Nanjing)
Application Number: 11/488,991
International Classification: G05F 1/70 (20060101);