Integrated circuit with adjusting elements and method for its manufacture
An integrated circuit is disclosed with adjusting elements, which in a first manufacturing stage are connected via tracks to terminal pads lying outside the integrated circuit. At least one of the tracks of the integrated circuit lies on a surface of a region, which includes semiconductor material and in a second manufacturing stage is isolated by a pn junction from additional semiconductor material, which is adjacent to the region. Furthermore, a method for manufacturing this type of integrated circuit is also disclosed.
This nonprovisional application claims priority under 35 U.S.C. § 119(a) on German Patent Application No. DE 2005022600, which was filed in Germany on May 10, 2005, and which is herein incorporated by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to an integrated circuit with adjusting elements, which are connected in a first manufacturing stage via tracks to terminal pads lying outside the integrated circuit. Furthermore, the invention also relates to a method for manufacturing such an integrated circuit.
2. Description of the Background Art
Integrated circuits with adjusting elements are known in the conventional art. The adjusting elements typically have, for example, a parallel connection of a resistor and a diode, whereby the adjusting element lies between a positive potential, prevailing within the integrated circuit, and a reference potential, which prevails in the semiconductor substrate of the integrated circuit. The adjusting element is connected via the track to a terminal pad lying outside the integrated circuit, a so-called zap pad. Current pulses, with which the diode is shifted optionally to a permanently conductive state, are supplied if appropriate via the terminal pad and the track to the adjusting elements, so that the resistor lying parallel to the diode is optionally bypassed. Electrical parameters of the integrated circuit are adjusted once bit-by-bit by this one-time process within the scope of the manufacturing process, whereby the conductivity state of the diode (permanently conducting or permanently blocking) corresponds to a bit.
After the adjustment, the integrated circuit produced together with other integrated circuits on a wafer is diced. The dicing usually occurs by a mechanical separating process, for example, by a saw cut, which is made through the terminal pads lying outside the integrated circuit. For dicing, the integrated circuits produced on a wafer are separated from one another by a scribe line. The saw cut is made within the scribe line. During the dicing, it can happen that the metal of the terminal pads in the separation plane is smeared by chip formation or by plastic deformation resulting from mechanical stress, so that dielectric layers lying between the semiconductor material and the terminal pads are bridged within the depth of the semiconductor material of the integrated circuit. In this case, the potentials prevailing in the semiconductor substrate can act within the adjusting element via the metal bridge formed, for example, by a metal chip and in an undesirable way alter the electrical parameters, which were in fact to be set by the adjusting process. Metal bridges of this type therefore produce a shunt between the reference potential in the semiconductor substrate and the affected adjusting element.
SUMMARY OF THE INVENTIONIt is therefore an object of the present invention to provide an integrated circuit with adjusting elements, in which such a shunt risk is minimized. Furthermore, the object of the invention is to provide a method for manufacturing this type of integrated circuit with a minimized shunt risk between the adjusting elements and the semiconductor material of the integrated circuit during dicing of integrated circuits.
This object is achieved in an integrated circuit, in that at least one of the tracks lies on a surface of a region, which includes semiconductor material and is isolated by a pn junction from additional semiconductor material, which is adjacent to the region.
Furthermore, this object is achieved by a method of the aforementioned type in that at least one region of semiconductor material is produced, which is isolated by a pn junction from additional semiconductor material, which is adjacent to the region, and a track is produced on the region of semiconductor material. The aforementioned shunt risk is minimized by these features. The pn junction represents an additional isolation structure, which is integrated within the depth of the semiconductor substrate and requires no additional volume. Also, no additional manufacturing steps are necessary, because the region can be produced more or less alongside the lithography, masking, and doping steps taking place in any event for structuring the integrated circuit. The expansion of the region and thereby the distancing of the isolating pn junction from cut-through metal cross sections can be adjusted both in the lateral and vertical direction by control of process parameters in the aforementioned steps without negatively impacting the area available for the integrated circuit. In view of embodiments of the circuit, the at least one track can run between the integrated circuit and an edge of the terminal pad, whose distance to the integrated circuit is smaller than the distances between other edges of the terminal pad and the integrated circuit.
In other words, the track in this embodiment runs between the terminal pad and the integrated circuit. Due to this space-saving arrangement, at a given lateral expansion of the integrated circuit and the terminal pads, a maximum number of terminal pads can be placed on a side of the integrated circuit, which results in a corresponding maximum number of adjustment options.
Also, a remainder of the terminal pad and/or the track still connected to the integrated circuit after dicing of the integrated circuit can be completely isolated from the neighboring semiconductor material by the region and the pn junction.
The region therefore extends under the track at least up to one of the separation planes forming during the dicing. The risk of shunts, which could arise as a result of metal smearing occurring during the dicing in the separation planes, is minimized thereby.
In an alternative embodiment, the at least one track runs partially beside a terminal pad and in the first manufacturing stage is connected to the terminal pad and in a second manufacturing stage is separated from the terminal pad.
This embodiment already represents an alternative solution to the aforementioned object in conjunction with the category-defining features.
The track in the separating plane has a smaller cross section than the terminal pad. Because the track in the second manufacturing stage is separated from the terminal pad, the metal cross section causing the potential shunts is limited to the smaller cross section of the track, which further reduces the probability of shunts. The cross section of the track can be smaller by three powers of ten than the cross section of the terminal pad. Because the larger cross section of the terminal pad in the second manufacturing stage is no longer connected via the track to the adjusting element, metal bridges from the cross section of the terminal pad can have no effect on the adjusting element. For this reason, the features of this embodiment can achieve the aforementioned object both in addition to the blocking layer isolation and also alone.
It is preferred, furthermore, that the track is covered at least partially by a passivating layer.
The passivating layer, which can include, for example, an oxide or nitride of the semiconductor material, reduces the mechanical stress, which acts on the cross section of the track during the dicing step. The likelihood of the occurrence of metal smearing is already reduced by reduction of the mechanical stress.
The terminal pads and the at least one track in an integrated circuit with a first metallization level, which is at a small distance to the semiconductor material of the circuit, and a second metallization level, which is at a greater distance to the semiconductor material, can have only the metal of the second metallization level.
In contrast, in the conventional integrated circuit, the terminal pad is realized by an arrangement of the first metallization level and the second metallization level one on top of the other. Because in the embodiment mentioned here only the second metallization level, which is at a greater distance to the semiconductor material, is used for the outward connection of the adjusting element, reduction of the metal cross section in the separation plane occurs and thereby a reduction of the size of possible metal bridges, which could cause shunts.
In view of alternatives and/or embodiments of the manufacturing process, the track can be produced between the integrated circuit and an edge of the terminal pad, whose distance to the integrated circuit is smaller than the distances between the other edges of the terminal pad and the integrated circuit, so that at least one subsection, facing the track, of the terminal pad also lies within the region.
Further, in the first manufacturing stage the circuit is placed on a wafer together with other integrated circuits and is separated by a dicing step from the other integrated circuits in such a way that in a second manufacturing stage the subsection is totally isolated by the pn junction from the neighboring semiconductor material.
Furthermore, the track can be covered at least partially by a passivating layer before the dicing step.
Also, the at least one track is produced in such a way that it runs partially beside a terminal pad, in the first manufacturing stage the circuit is placed on a wafer together with other integrated circuits, and in a second manufacturing stage is separated by a dicing step from the other integrated circuits in such a way that a remainder of the track is separated from the terminal pad.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:
The track 22.1 leads to a terminal pad 24.1, by means of which second terminal 20 can be connected to a measuring and adjusting device, which is not shown in
In this way, integrated circuit 10 parameters, which can be influenced via first terminal 18 of adjusting element 12 are set bit by bit. It is understood here that an adjusting element 12 may also have a different structure than the one shown in
In the embodiment of
Integrated circuit 10 in the presentation of
However, the mechanical stress occurring during sawing in fact causes structural changes, as they are shown in the left half of
In the embodiment of the left half of
To produce this desired effect, region 38 must have a sufficient expansion. It must therefore in each case lie within the plane of the saw cut II-II in
The region is preferably expanded so far in the direction of track 22.1 of
In contrast to the subject of
Due to the separation, metal bridges 34.1, 36.1, 34.2, 36.2 of terminal pads 24.1, 24.2 can no longer have a negative effect on integrated circuit 10. Leak currents can still be carried at all only by plastic deformations, forming metal bridges 37.1, 37.2, of cross sections of tracks 22.1 and 22.2.
Because the cross-sectional areas of tracks 22.1, 22.2, however, are still smaller than the cross sections of terminal pads 24.1, 24.2, a reduced shunt probability results, so that the routing of tracks 22.1, 22.2 according to
Another advantage of the subject of
Overall, in the subject of
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.
Claims
1. An integrated circuit having adjusting elements, which in a first manufacturing, stage are connected via tracks to terminal pads that are provided external to the integrated circuit, wherein at least one of the tracks is provided on a region, which includes semiconductor material and is isolated by a pn junction from additional semiconductor material, which is adjacent to the region.
2. The integrated circuit according to claim 1, wherein the at least one track is provided between the integrated circuit and an edge of one of the terminal pads, a distance of the at least one track to the integrated circuit being smaller than a distance between an outer edge of the terminal pad and the integrated circuit.
3. The integrated circuit according to claim 2, wherein a remainder of the terminal pad and/or the track that are connected to the integrated circuit after dicing of the integrated circuit are completely isolated from a neighboring semiconductor material by the region and the pn junction.
4. The integrated circuit according to claim 1, wherein the at least one track is provided at least partially along terminal pad and in the first manufacturing stage is connected to the terminal pad and in a second manufacturing stage is separated from the terminal pad.
5. The integrated circuit according to claim 4, wherein the at least one track is covered at least partially by a passivating layer.
6. The integrated circuit according to claim 1, wherein the terminal pads and the at least one track with a first metallization level, which is at a smaller distance to the semiconductor material of the integrated circuit, and a second metallization level, which is at a greater distance to the semiconductor material, have only the metal of the second metallization level.
7. An integrated circuit having adjusting elements, which are connected in a first manufacturing stage via tracks to terminal pads that are provided external to the integrated circuit, wherein at least one of the tracks runs partially along a terminal pad and, wherein, in the first manufacturing stage, is connected to the terminal pad and in a second manufacturing stage is separated from the terminal pad.
8. A method of manufacturing an integrated circuit, the method comprising the steps of:
- providing adjusting elements, which are connected in a first manufacturing stage via tracks to terminal pads that are provided external to the integrated circuit;
- isolating at least one region, which is formed of semiconductor material, by a pn junction from additional semiconductor material, which is adjacent to the region; and
- providing a track on the region of semiconductor material.
9. The method according to claim 8, wherein the track extends between the integrated circuit and an edge of the terminal pad, whose distance to the integrated circuit is smaller than a distances between outer edges of the terminal pad and the integrated circuit, so that at least one subsection that faces the track of the terminal pad is also provided within the region.
10. The method according to claim 9, wherein the at least one track is provided so that it runs at least partially along a terminal pad, wherein, in a first manufacturing stage the integrated circuit is placed on a wafer together with other integrated circuits, and wherein in a second manufacturing stage the integrated circuit is separated by a dicing step from the other integrated circuits so that a remainder of the track is separated from the terminal pad.
11. The method according to claim 10, wherein the track is covered at least partially by a passivating layer before the dicing step.
Type: Application
Filed: May 10, 2006
Publication Date: Nov 16, 2006
Inventors: Juergen Haefner (Untereisesheim), Alexander Kurz (Schwaebisch Hall), Wolfgang Sinderhauf (Neckarsulm), Matthias Tortschanoff (Villach), Ulrich Wicke (Heilbronn)
Application Number: 11/431,061
International Classification: H03H 11/00 (20060101);