Fabrication of macroporous silicon

Abstract

A process for the fabrication of macroporous silicon from silicon wafers. Preferred embodiments include a two-step-etch process that results in a single, macroporous layer of silicon with pore depths of several microns and relatively uniform equivalent diameters with an operator chosen mean equivalent diameter. The mean diameter determined by the operator is a mean diameter within the range of about 40 nm to about 250 nm and is determined, at least in part, by selection of an applied current density. Uniformity of equivalent pore diameter is greatly improved as compared to prior art porous silicon fabrication techniques. In a first electrochemical anodisation step, a macroporous layer is created that is covered by a shallower combination microporous-mesoporous layer. The wafer is removed and the top surface of the wafer is dissolved under alkaline conditions, producing “pits”. These “pits” serve as defect sites during a second electrochemical anodisation step, resulting in a single, uniform, macroporous layer in the silicon wafer. Preferably, the wafer with its porous silicon surface is quickly rinsed in acetone and then pentane to preserve the structure of the pores and prevent collapsing of pore walls. The process of the present invention eliminates the upper, nanoporous region produced by prior art processes. In a preferred embodiment, utilizing a current density of 181.8 mA/cm2 in the two-etch-step process, the resulting mean equivalent pore diameter is about 100 nm with more than half of the equivalent pores diameters within about ±50 nm of the mean equivalent pore diameter. By increasing or decreasing the anodisation current, porous layers with mean diameters within the range of about 40 nm to about 250 nm can be created.

Description

This invention relates to processes for the fabrication of porous silicon products and in particular to techniques for the fabrication of such products with average equivalent pore diameters in the range of about 40 to 250 nanometers.

BACKGROUND OF THE INVENTION

Porous Silicon

Porous silicon parts are produced by electrochemically etching silicon wafers in a hydrofluoric acid bath, which yields porous layers on one of the surfaces of the wafer. The first experiments at producing these layers were more than 40 years ago. In the etching process, silicon atoms are dissolved from the bulk material forming tiny pores and the original crystal structure remains unaffected. Dependent on the experimental conditions (doping density of bulk material, electrolyte concentration, current density, etching voltage, temperature) different modifications of porous silicon can be formed. With the different pore etching techniques it is possible to vary pore sizes in the silicon on a scale from millimeters to nanometers. A very large number of technical applications of porous silicon have been proposed. These include optical components, electronic components and electro-optical components.

In a typical prior art process, a silicon wafer is immersed in an ethanolic hydrofluoric acid solution between a platinum cathode and a platinum anode and a constant electric current is applied to the wafer. The silicon atoms at the silicon/electrolyte interface facing the cathode are polarized, and are subject to attack by the fluoride ions in solution. Silicon atoms are released in the form of silicon hexafluoride. Porous silicon tends to etch as a distribution of approximately cylindrical pores with very small diameters that tend to be much deeper than they are wide. The approximately cylindrical shape of the pores and their depths can be amazingly uniform. The distribution of pore diameters and the depth of the pores are controlled by adjusting the current density and the etching time. Additional details relating to these processes are contained in U.S. Pat. No. 6,248,539 that is incorporated herein by reference.

The International Union of Pure and Applied Chemistry (IUPAC) guidelines define ranges of pore sizes as shown in Table 1 below:

TABLE 1
IUPAC Classification of Pore Size.
Pore Width
(nm) Type of Pore
<2   micro
2-50 meso
>50  macro

Single Step Fabrication Results

Prior art fabrication techniques to produce porous silicon parts included a single-step, electrochemical dissolution of very highly-doped, p-type porous silicon. The disadvantages of this method are:

• • 1) requirements for a very limited wafer-resistivity range (ρ=0.00065-0.00075 Ωcm);
  • 2) difficulty and cost associated with obtaining such wafers; and
  • 3) uncertain results.

In addition, SEM imaging of the etched silicon revealed an upper shallow layer of micropores and mesopores (with equivalent diameters generally much less than 50 nanometers) covering a mixed, macroporous layer (a deeper layer of pores having pores with equivalent diameters generally greater than 50 nanometers). The upper layer appeared to vary in depth from several hundred nanometers to several microns.

What is needed is a better method for making porous silicon products with uniform average pore diameters in the range of about 50 nanometers to about 250 or greater.

SUMMARY OF THE INVENTION

This invention provides a process for the fabrication of macroporous silicon from silicon wafers. Preferred embodiments include a two-etch-step process that results in a single, macroporous layer of silicon with pore depths of several microns and relatively uniform equivalent diameters with an operator chosen mean equivalent diameter. The mean diameter determined by the operator is a mean diameter within the range of about 40 nm to about 250 nm and is determined at least in part by a selection of an applied current density. Uniformity of equivalent pore diameter is greatly improved as compared to prior art porous silicon fabrication techniques. In a first electrochemical anodisation step a macroporous layer is created that is covered by a shallower combination microporous-mesoporous layer. The wafer is removed and the top surface of the wafer is dissolved under alkaline conditions, producing “pits”. These “pits” serve as defect sites during a second electrochemical anodisation step, resulting in a single, uniform macroporous layer in the silicon wafer. Preferably, the wafer with its porous silicon surface is quickly rinsed in acetone and then pentane to preserve the structure of the pores and prevent collapsing of pore walls. The process of the present invention eliminates the upper, nanoporous region produced by prior art processes. In a preferred embodiment, utilizing a current density of 181.8 mA/cm² in the two-etch-step process, the resulting mean equivalent pore diameter is about 100 nm with more than half of the equivalent pores diameters within about ±50 nm of the mean equivalent pore diameter. By increasing or decreasing the current porous layers with mean diameters within the range of about 40 mu to about 250 nm can be created.

In addition to the elimination of the upper, nanoporous layer, the new method also has the advantages of:

• • 1) utilizing lower concentrations of hydrofluoric acid, thereby decreasing safety hazards;
  • 2) utilizing silicon wafers with wider, less expensive and more readily available resistivity ranges (ρ=0.001-0.0035 Ω-cm); and
  • 3) increasing anodisation times to allow for better control and better reproducibility. In addition, the process according to the present invention permits the reproducible fabrication of porous silicon products with relatively uniform equivalent pore diameters with average equivalent pore diameters ranging from about 50 nm to about 250 nm with defined depths up to several microns. These varieties of average pore diameters and depths are produced with the proper choice of anodisation current density and etch time.

In preferred embodiments for producing wafers for use in a molecular sensor, the porous structure is surface modified by molecular vapor deposition of silane compounds to increase wettability, stability and confer functionality.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a scanning electron micrograph of electrochemically etched porous silicon that results from the prior art utilizing p-type silicon (ρ=0.00065 Ω-cm).

FIG. 2 is a scanning electron micrograph of electrochemically etched porous silicon utilizing lower-resistivity, more readily available, p-type silicon (ρ=0.0011 Ω-cm).

FIG. 3 is a scanning electron micrograph of electrochemically etched porous silicon utilizing lower-resistivity, more readily available, p-type silicon (ρ=0.0011 Ω-cm), post KOH-dissolution.

FIG. 4A is a scanning electron micrograph (cross-sectional view) of an upside down electrochemically etched porous silicon using the new method.

FIG. 4B is a scanning electron micrograph (tilted top view) of electrochemically etched porous silicon using the new, double-etch method.

FIGS. 5A through 5E are a representative sampling of different scanning electron micrographs (top views) of electrochemically etched porous silicon, demonstrating some of the different pore size distributions achievable with this invention and showing the effect on pore size of increasing current.

FIGS. 6A and 6B show important components of an anodisation cell.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Fabrication of Porous Silicon with Average Pore Diameters of 100 nm

Described below by reference to the drawings is a preferred process for fabricating porous silicon with an average equivalent pore diameter of about 100 nanometers with more than half of the pores having equivalent pore diameters within about ±20 nm of the average 100 nm equivalent diameter.

In this specification, we will use the phrase, “equivalent pore diameter” D_e, of a pore to refer to the approximate diameter of a comparable circular cylinder having the same volume as that of the pore. Since the cross sectional area of each pore is typically approximately uniform along the depth of the pore, we can estimate this equivalent pore diameter by measuring the area, A, of the pore at the surface of the wafer and calculating a value for D_e as follows: D_e=2√{square root over (A/π)}.

A preferred anodization cell 48 is shown in an exploded view in FIG. 6A and in a perspective view in FIG. 6B. It includes cell reservoir 48, wafer holder 50, anode 52 and cathode 54. Wafer holder 50 includes two fluoroelastomer gaskets 60 (such as Viton® gaskets, available from Problem Solving Products, Inc. with offices in Denver, Colo.) that provide seals separating the cell reservoir into an anode region and a cathode region to create what is known as a “double-tank” cell. Substantially the entire voltage drop in the cell's electrical circuit is through silicon die 56. (Die 56 is, as indicated in FIG. 6A, a 10 mm×13 mm section of a silicon wafer. Although the die section is only a small part of a wafer it is sometime referred to, itself, as a wafer.) Wafer holder includes two Teflon masks with etching windows 58, each defining an etch area of 0.495 cm².

The porous silicon regions are high surface area regions consisting of nanometer size pores in a crystalline silicon substrate. The pores are produced by anodic electrochemical etches of bulk crystalline silicon. The starting material for porous silicon, for this preferred embodiment, is a heavily doped crystalline silicon wafer, commercially available for semiconductor manufacturing purposes. Wafer specifications for this porous silicon fabrication process include p-type boron doped silicon (0.001-0.0035 Ω-cm resistivity) with a <100> crystal orientation. Four inch diameter, p-type silicon (100) wafers with resistivity ranges between 0.0010 and 0.0035 Ω-cm were purchased from Silicon Quest International, Inc., with offices in Santa Clara, Calif.). The wafers were pre-scribed into 44 individual die sections measuring 10 mm×13 mm by American Precision Dicing (San Jose, Calif.) which section, as indicated above, are referred to as dies, die section or wafers. The actual etch area, defined by the Teflon masks, measures 9.0 mm×5.5 mm and equals 49.5 mm².

All chemicals used were reagent grade or higher and purchased from Hawaii Chemical & Scientific unless otherwise noted. Ultra pure water was obtained from a Bamstead Nanopure Diamond Analytical Water System (APC Water Services, Inc.).

Precleaning

Immediately prior to anodisation, wafers were pre-cleaned as described in this section. Silicon wafer 56 was placed in 40 ml of concentrated sulfuric acid and heated to about 90 degrees C. Twenty milliliters of hydrogen peroxide (30%) was added to the acid and the wafer was allowed to oxidize for 10 minutes in the heated solution, after which the wafer was rinsed with copious amounts of ultra pure water for 5 minutes. The rinsed silicon wafer was transferred to a clean, glass beaker containing 150 ml of ultra pure water and 30 ml of ammonium hydroxide (30%). The solution was heated and, once it reached 70 degrees C., 30 ml of hydrogen peroxide (30%) was added. The silicon wafer remained in the solution for 15 minutes and again was rinsed with copious amounts of water for 5 minutes. A resulting oxide layer was stripped by soaking the wafer in a 2.5% solution of hydrofluoric acid (diluted with water) for 2 minutes and again rinsed with copious amounts of water for 5 minutes. The silicon wafer was then transferred to a clean, glass beaker containing 120 ml of ultra pure water and 30 ml of hydrochloric acid (37%). The solution was heated to 70 degrees, at which time 30 ml of hydrogen peroxide was added. The silicon wafer remained in the solution for 15 minutes before a final five minute rinse with copious amounts of ultra pure water. The wafer was blown dry under an inert stream of nitrogen gas using a nitrogen source available from GasPro, with offices in Kahului, Hi.

Anodisation

The clean wafer was then assembled into the Teflon etch chamber of anodisation cell 48 and immersed in an ethanolic hydrofluoric acid solution. The solution is a mixture of equal quantities of (1) 50% hydrofluoric acid (equal volumes of hydrofluoric acid and water) and (2) ethanol. Applicants refer to this solution as 25 percent hydrofluoric acid in ethanol. Specifically, 40 milliliters of 25 percent hydrofluoric acid in ethanol is slowly added to the cell reservoir. Conductors from a power supply (not shown) are connected to the platinum wire electrode paddles in the anodisation cell and a constant current density (J=181.8 mA/cm²) is applied for 30 seconds. The total area to be etched, defined by windows 58, is 0.99 cm².

Therefore, the appropriate anodisation current is 180 mA. The silicon atoms at the silicon/electrolyte interface are attacked by the fluoride ions in solution forming silicon hexafluoride. Silicon atoms are released from the wafer in the form of silicon hexafluoride. The etched silicon wafer is removed from the anodisation cell, rinsed in acetone, then pentane and allowed to air dry. As shown in FIG. 1 and FIG. 2, the porous silicon that results from this first etch step is bi-layered, with an upper, microporous-mesoporous layer (with equivalent pore diameters mostly at about 10 to 50 nanometers) covering a lower, macroporous layer with diameters in the range of about 100 nanometers. (The magnification of the images shown in FIGS. 1 and 2 are indicated by a 1 micron reference line at the bottom of FIG. 1 and a 100 nm reference line at the bottom of FIG. 2. The upper, microporous-mesoporous layer and the top portion of the lower layer (approximately the top 70 to 90 percent of the lower layer) are dissolved in 0.1M KOH, rinsed and dried under a stream of nitrogen. The remainder of the lower layer appears as relatively shallow “pits”. These remaining pits, shown in FIG. 3, serve as defect sites for the initiation of a second electrochemical etch. (Note the 100 nm reference line at the bottom of FIG. 3.) The silicon is again immersed in an ethanolic hydrofluoric acid solution (HF:ethanol, 1(v):1(v)) in cell 48 and a constant electric current applied using the platinum electrodes. The silicon is again anodized at 180 mA (current density=181.8 mA/cm²) for 30 seconds, rinsed in acetone and finally in pentane to prevent collapsing of the pore walls due to high interfacial surface tension during drying of the porous silicon. The samples are blown dry under an inert stream of nitrogen gas and stored in a dessicator for further surface modification.

The result of the above process is a silicon wafer part with a very uniform, single, macroporous layer as shown in FIGS. 4, 4A and 4B. The pores are about two microns deep with good symmetry throughout the depth of the pores and very little (less than about 10 percent) variation in depth. The pores are roughly circular but can have final shapes similar to squares, pentagons and hexagons (with narrow walls). About 90 percent of the wafer surface is covered with pores that have “diameters” in the range of about 50 nm to 250 nm but most of the pores have equivalent pore diameters in the range of 100±50 nm.

FIG. 4A is an inverted side cross section image before a gold coating is applied and FIG. 4B is a tilted top view image after gold coating. FIG. 4A confirms the uniformity of pore width as a function of pore depth.

Varying the Pore Diameter and the Depth

The distribution of pore diameters and the depth of the pores may be controlled by adjusting current density and anodisation duration, as shown in FIGS. 5A through 5E. Typical average pore features for preferred embodiments produce average equivalent pore diameter distributions of about 50 to 250 nanometers and pore depths of about 2000 to 3000 nanometers. The current densities, J, applied to produce the samples shown in FIGS. 5A through 5E varied from J=162 mA/cm² to J=404 mA/cm². The pore diameters increase with increasing current density with J=162 mA/cm² creating pores with diameters averaging about 40 nm and J=404 mA/cm² producing pores with diameters averaging about 250 nm. The depth of the pores is very uniform. This high uniformity of the etching process provides the two optically flat interfaces; the top surface of the porous silicon, and the interface between the bottom of the porous silicon region and the non-porous, or bulk, silicon. The pore depth is controlled by the duration of etch.

Surface Modification of Porous Silicon

In preferred embodiments, the porous silicon surface may be modified for particular applications. In one application the porous silicon is utilized in a molecular sensor to anchor molecules for the purpose of monitoring molecular interactions. For this embodiment, after the porous silicon layer has been produced on the silicon wafer as explained above, a protective layer is applied to prevent or minimize oxidation and contamination with particulates from ambient air. Preferably the wafers are immediately surface modified or stored under a blanket of inert nitrogen gas in a controlled humidity environment to be surface modified later. Surface modifications can be achieved using a variety of techniques including wet chemistry and molecular vapor deposition (MVD). Applicants' first preferred embodiment for surface modification relies on MVD technology. MVD overcomes many limitations associated with wet chemistry including cost, process complexity and surface coverage. The process consists of pre-cleaning using argon or oxygen plasma followed by tunable deposition of a monolayer film under sub-atmospheric pressure.

A wide variety of chemicals can be deposited on the surface depending upon the ultimate application. For a preferred embodiment in which the porous silicon dies are to be used as a molecular sensor for measuring binding interactions, Applicants describe below the deposition of 10-(carbomethoxy)decydimethylchlorosilane (Gelest, Inc.) using a molecular vapor deposition unit Model MVD-100 available from Applied Microstructures Inc. with offices in San Jose, Calif. Post-etching, samples were placed in the MVD-100 and cleaned of any organic contamination by an oxygen plasma treatment, in this case, for 90 seconds with a chamber pressure of 0.5 Torr and RF power in the range of 100-300 watts. The plasma treatment serves a dual purpose, not only eliminating the etched surface of contaminants, but also uniformly hydroxylating the silicon surface with OH-groups for subsequent silanization. The organic linker [10-(carbomethoxy)decyldimethylchlorosilane] (Gelest, Inc.) was vaporized before metered delivery of approximately 2.0-3.0 microliters to the reaction chamber where it reacted with the hydroxylated silicon surface in the presence of trace amounts of water, resulting in the release of a negligible amount of HCL gas and the functionalized silicon surface. In this case, the vapor was allowed to react for 25-30 minutes. The dies can be used, as is, to couple proteins via standard amine coupling techniques or further modified with different bioconjugates to increase hydrophilicity and/or create specific functionalized surfaces. Using this preferred embodiment, Applicants and thier fellow workers have coupled Amino-dPEG₁₂™-t-butyl ester (Quanta Biodesign) to the surface by first activating the carbomethoxy group of the silicon surface with 200 mM EDC [1-Ethyl-3-(3-Dimethylaminopropyl)carbodiimide Hydrochloride] (Pierce Biotechnology) and 50 mM NHS [N-Hydroxysuccinimide] (Pierce Biotechnology) in water for 10 minutes. The activated surface is then allowed to react with 1 mg/ml of Amino-dPEG₁₂™-t-butyl ester for 30 minutes and any remaining NHS esters are capped with 1M ethanolamine, pH 8.0 for 10 minutes. The surface is rinsed in ultra pure water, pure ethanol and dried under a stream of inert nitrogen gas. The final product is a pegylated, porous silicon surface with a protected carboxylic acid functional group. The functional group may be deprotected by exposure to 25% trifluoroacetic acid (TFA) in ice cold methylene chloride (CH₂Cl₂) for 5 hrs and used for immobilization with standard amine coupling techniques. Alternatively, the deprotection step may be avoided by coupling the Amino-dPEG₁₂ ™ acid (Quanta Biodesign) instead of the Amino-dPEG₁₂™-t-butyl ester. In this case, the end user can proceed with activation and immobilization of the target using EDC/NHS and standard amine coupling. The end product is a functionalized, hydrophilic porous silicon die with cylindrical, straw-like pores of 100 nm diameters and 2 μ depths and two optically flat, parallel surfaces resulting from the top (air/porous silicon) and bottom (porous silicon/bulk silicon) surfaces of the porous silicon matrix. The structural morphology of the dies provides a convenient two-beam interferometer while the high surface area and adaptable surface chemistry provide the platform for numerous protein and DNA sensing applications.

While the present invention is described in terms of preferred embodiments, the reader should understand that these are merely examples and that many other embodiments are changes to the above embodiments will be obvious to persons skilled in this art. For example, the size, shape and number of pores in the porous silicon regions could vary greatly depending on the particular application of the present invention. Applicants and thier fellow workers have been able to achieve reproducible pore sizes with diameters as small as 20 nm and as large as several microns. The porosity of the regions may vary greatly with the application and many other porosity values could be utilized. Also, the self assembled monolayer and secondary linkers can take limitless forms, depending upon the end user's ultimate application. For instance, a short pegylated molecule with a hydroxyl group on one end and a protected acid on the other could be deposited directly onto the porous silicon surface after plasma treatment using the MVD-100. Linker with free thiol groups (versus the acid described in the preferred embodiment) can be utilized if the ultimate goal is to immobilize targets via the sulfhydryl group. Therefore, the scope of the invention should be determined by the claims and their legal equivalents.

Claims

1. A process for the fabrication of porous silicon from silicon wafers with pore depths of several microns and average equivalent pore diameters of about 40 nm to about 250 nm comprising the steps of:

A) in a double-tank etch chamber, comprising a positive electrode and negative electrode and an etch solution, immobilizing a silicon wafer between said positive and negative electrodes,

B) initiating a first electrochemical anodisation step to etch on a surface of said silicon structure a macroporous layer that is covered by a shallower combination microporous-mesoporous layer,

C) dissolving the combination microporous-mesoporous layer and most of the mesoporous layer leaving pits in the surface of said silicon structure, and

D) initiating a second electrochemical anodisation step to etch on the surface of said silicon structure a mesoporous layer with said pits serving as defect sites to define locations of pores having average diameters of about 40 nm to about 250 nm.

2. The process as in claim 1 wherein said average diameter of between 40 nm and 250 nm is determined by choice of current density applied in said first and second anodisation steps.

3. The process of claim 1 wherein said dissolving step is accomplished under alkaline conditions.

4. The process as in claim 1 and further comprising the step of rinsing said silicon structure in acetone and then pentane prior to initiating said second anodisation step.

5. The process as in claim 1 and further comprising a step of modifying the porous surface by molecular vapor deposition of silane compounds.

6. The process as in claim 1 wherein said etch solution is an ethanolic HF solution.

7. The process as in claim 5 wherein said ethanolic HF solution comprises about 25 percent hydrogen fluoride.

8. The process as in claim 1 wherein a current density in the range of about 162 mA/cm2 to 404 mA/cm2 is applied through said silicon structure during said second electrochemical anodisation step.

9. The process of claim 1 wherein said silicon structure has resistivity values in the range of about 0.001 to 0.0035 ohms-cm.

10. The process of claim 8 wherein an electric current density in the range of about 162 mA/cm2 to 404 mA/cm2 is applied through said silicon structure during said first electrochemical anodisation step.

11. The process as in claim 1 wherein said double-tank etch chamber defines a cathode region and an anode region isolated electrically from each other by said wafer and a seal.

12. The process as in claim 1 wherein said seal is a fluoroelastomer gasket.