Semiconductor device and method of fabricating the same
A semiconductor device, comprising: a substrate; a floating body region formed in the substrate, a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and source and drain regions, respectively, formed on second and third surface regions of the floating body region, the source region being connected to a source line and providing a first electric capacity at an interface relative to the floating body region, the drain region being connected to a bit line and providing a second electric capacity at an interface relative to the floating body region, the second electric capacity being smaller than the first electric capacity.
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This application is based upon and claims the benefit of priorities from the prior Japanese Patent Application No. 2005-207816 filed on Jul. 15, 2005 and the prior Japanese Patent Application No. 2005-257999 filed on Sep. 6, 2005, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTIONThe present invention relates to a semiconductor device including FBC (Floating Body Cell) structure, and a method of fabricating the same.
Communication for large capacity data such as moving pictures or the like has increased in accordance with spread of a broadband. In accordance with this situation, LSIs which can process a large amount of data at a high speed have been required. For this reason, a requirement for a technique for simultaneously forming a high-performance microprocessor and a large capacity memory on one semiconductor chip has been increased.
However, a memory cell of a conventional DRAM (Dynamic Random Access Memory) has a structure including one transistor and one capacitor. Hence, there is expected such a problem that the scaling of cell size is to be difficult with the progress of the generation.
As a memory cell for solving the problem, DRAM memory cell referred to as FBC has been developed. A semiconductor device including the FBC structure can perform the memory operation with one transistor, unlike the conventional DRAM. Hence, the semiconductor device has an advantage in which it is suitable for miniaturization in principl. Thus, the semiconductor device including the FBC structure is paid with much attention as a technique for realizing a DRAM embedded system LSI in and after the 45 nm-generation.
A semiconductor device including an FBC structure on a silicon on insulator (SOI) substrate, and a semiconductor device including an FBC structure on a bulk Si have already been reported.
A semiconductor device including an FBC structure on the SOI substrate is described, for example, in Japanese Patent Kokai No. 2003-68877, and a literature of T. Oosawa et al., ISSCC Dig. Tech. Papers, p. 152 (2002), and the semiconductor device including the FBC structure on the SOI substrate is an important device for the purpose of realizing an SOI logic-embedded system LSI.
A semiconductor device including an FBC structure on the bulk Si substrate is described, for example, in a literature of R. Ranica et al., Symp. on VLSI Tech. (2004), and the semiconductor device includes a n-type buried well formed on a p-type Si substrate, a p-type floating well formed on the n-type buried well, source and drain diffusion layers formed in a surface of the p-type floating well, a shallow trench isolation (STI) portion for separating adjacent transistors from each other, and a gate electrode formed via a gate oxide film on the p-type floating well.
This semiconductor device performs a memory operation by accumulating holes in the p-type floating well formed on the n-type buried well.
In the conventional semiconductor device, however, in order to increase a signal amount as a difference between thresholds in cases where “0” and “1” are read out, it is required to increase an impurity concentration of the p-type floating well. When the impurity concentration of the p-type floating well is increased, retention characteristics of a memory is degraded due to an increase in junction leakage current, and a write time is deteriorated due to a deep threshold. For this reason, it is required to realize a semiconductor device in which the signal amount is increased without increasing the impurity concentration of the p-type floating well.
SUMMARYAccording to an embodiment of the invention, a semiconductor device, comprises:
a substrate;
a floating body region formed in the substrate,
a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and
source and drain regions, respectively, formed on second and third surface regions of the floating body region, the source region being connected to a source line and providing a first electric capacity at an interface relative to the floating body region, the drain region being connected to a bit line and providing a second electric capacity at an interface relative to the floating body region, the second electric capacity being smaller than the first electric capacity.
According to another embodiment of the invention, a semiconductor device, comprises:
a semiconductor substrate;
a first conductivity type buried well formed in the semiconductor substrate;
a second conductivity type floating body region formed on the first conductivity type buried well;
a gate electrode formed above a first surface region of the second conductivity type floating body region via a gate insulating film;
first conductivity type source and drain regions, respectively, formed on second and third surface regions of the second conductivity type floating body region; and
a structure of increasing an electric capacity formed at an interface between the first conductivity type buried well and the second conductivity type floating body region.
According to still another embodiment of the invention, a method of fabricating a semiconductor device, comprises:
forming a first conductivity type buried well in a semiconductor substrate;
forming a second conductivity type floating body region on the first conductivity type buried well; and
forming a structure of increasing an electric capacity at an interface between the first conductivity type buried well and the second conductivity type floating body region.
BRIEF DESCRIPTION OF THE DRAWINGS
Here, the MOS transistor which is held between the adjacent STI portions 90 to include the p-type floating well 30, the gate oxide film 40, the gate electrode 50, the source diffusion layer 70, and the drain diffusion layer 80 is defined as one memory cell region 110 (hereinafter referred to as simply “memory cell”) in the semiconductor device 10.
As shown in
Next,
In
In addition,
[Write of “1” to Memory Cell (
In order to write “1” to the selected cell, the selected word line voltage VWL of about 1.5 V is applied at a time t1, and subsequently the selected bit line voltage VBL of about 2.2 V is applied at a time t2. Thereupon, impact ionization is caused at a gate edge of the drain diffusion layer 80, so that excessive holes are injected and held in the p-type floating well 30, and thus “1” is written thereto.
[Hold of “1” in Memory Cell (
In order to perform the storage and hold of “1” in the selected cell, the selected word line voltage VWL of about −2.0 V is applied at a time t3, and the selected bit line voltage VBL is set to about 0 V at a time t4. As a result, “1” is stored and held at the time t4.
[Read of “1” from Memory Cell (
In order to read “1” from the selected cell, the selected bit line voltage VBL is set to about 0.2 V at a time t5 while the word line voltage VWL is held at about −2.0 V. Then, the word line voltage VWL is swept from −2.0 V, thereby reading “1” from the selected cell.
[Write of “0” to Memory Cell (
In order to write “0” to the selected cell, the selected word line voltage VWL of about 1.5 V is applied at a time t11, and subsequently the selected bit line voltage VBL is set to about −1.1 V at a at a time t12. Thus, the junction between the p-type floating well 30 and the drain diffusion layer 80 is biased in the forward direction, and thus the holes accumulated in the p-type floating well 30 are released from the selected cell, thereby writing “0”.
[Hold of “0” in Memory Cell (
In order to store and hold “0”, the selected word line voltage VWL of about −2.0 V is applied at a time t13, and the selected bit line voltage VBL is set to about 0 V at a time t14. As a result, “0” is stored and held at the time t14.
[Read of “0” from Memory Cell (
In order to read “0”, the selected bit line voltage VBL of about 0.2 V is applied at a time t15 while the selected word line voltage VWL is held at about −2.0 V, and the word line voltage VWL is swept from −2.0 V, thereby reading “0” from the selected cell. A series of operations from “1” write to “0” read can be performed in the manner described above.
After a time t21 in
Here, a change amount of a body region voltage VB during the read operation in the selected memory cell of the first embodiment will hereinafter be described in more detail in
Referring to
As described above, when the area of the unit cell 140a is set to be a given condition in the first embodiment, the gate electrode 50 is displaced from the cell central line 100a to the side of the drain diffusion layer 80 to provide the structure in which the gate electrode 50, and source and drain diffusion layers 70 and 80 are asymmetrical with respect to the cell central line 100a, i.e., to reduce the ratio Cdb/Csb, so that it becomes possible to increase the signal amount. In this case, the signal amount can be increased in accordance with the increase in displacement Δ of the central line 100b of the gate electrode 50.
Now, while in the first embodiment, means for shortening the distance between the word line 50a and the remote end of the drain diffusion layer 80 has been described so far by using the word lines 50a each having the straight line structure, any other suitable structure may also be adopted as long as it has the same distance relationship as that in the first embodiment. For example, a structure, having non-straight lines, called a wiggle structure may also be used in a constitution of the word lines 50a.
Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to
In the first embodiment, the asymmetrical structure is used in which the central position of the word line is displaced to the side of the drain diffusion layer, thereby reducing the ratio Cdb/Csb. However, the second embodiment is different from the first embodiment in that impurity concentrations of a drain diffusion layer and a source diffusion layer are made asymmetrical, thereby reducing the ratio Cdb/Csb.
The second embodiment also offers the effect in which the ratio Cdb/Csb is reduced similarly to the first embodiment. However, the source line 70a and the bit line contact 80b are not common to the source and drain diffusion layers 71 and 81 for adjacent two transistors, so that an area of the unit cell 140c of the second embodiment is different from that of the unit cell 140b, as shown in
Now, though the case where the position of the gate electrode 50 coincides with the cell central line 100a is shown in
A source diffusion layer 14 and a drain diffusion layer 15 are formed on a surface of the p-type floating well 13, respectively, and a gate electrode 19 is formed on a gate oxide film 17 as a gate insulating film formed on the p-type floating well 13. Also, a gate sidewall insulating film 18 is formed on both sidewalls of the gate electrode 19. A plurality of MOS transistors (only one MOS transistor is illustrated in
In this MOS transistor, a portion of the p-type floating well 13 is deeper right under the gate electrode 19, and thus a recessed portion 12a is formed at a junction interface between the buried n-type well 12 and the p-type floating well 13. The formation of the recessed portion 12a at the junction interface makes it possible to increase an area of the junction interface.
Here, a width of the recessed portion 12a formed at the junction interface between the n-type buried well 12 and the p-type floating well 13 is preferably made as twice or more as that of a depletion layer from the side of the p-type floating well 13 and a depth thereof is preferably made equal to or larger than the width of the depletion layer from the side of the p-type floating well 13.
Now, though a schematic plan view showing a memory cell array in which memory cells are disposed in matrix pattern in accordance with the third embodiment is omitted herein, the memory cell array may be structured in the same manner, for example, as one which was shown in
In
TABLE 2 shows an example of an operation condition of the semiconductor device 10 according to the third embodiment of the present invention. This operation condition is a bias condition during a memory operation. In TABLE 2, Vg is a gate voltage, Vd is a drain voltage, Vs is a source voltage, and Vbn is a voltage applied to the n-type buried well 12, wherein they are the same as in TABLE 1.
In the conventional semiconductor device 100, a signal amount SA between a “0” read phase and a “1” read phase is 0.22 V for the gate voltage Vg as shown in
It is understood from these results that since in the semiconductor device 10 having the structure shown in
According to the third embodiment of the present invention, the area of the junction interface between the p-type floating well and the n-type buried well is increased due to the formation of the recessed portion at the junction interface between p-type floating well and the n-type buried well so that a capacity which is required to accumulate the holes is increased. As a result, it is possible to increase the signal amount.
Next, a description will be given with respect to a method of fabricating a semiconductor device according to the fourth embodiment of the present invention.
In
Here, an example of an ion implantation condition for formation of the n-type buried well 12 and the p-type floating well 13 is as follows.
(1) n-Type Buried Well 12:
(2) p-Type Floating Well 13:
Here, a straight line which extends in parallel with a paper plane and which passes through the p-type floating well 13 in parallel with the junction interface between the p-type floating well 13 and the n-type buried well 12 is defined as x-axis, a straight line which extends in parallel with the paper plane and which passes through the respective centers of the gate electrode 19 and the recessed portion 12a to meet at a right angle with the x-axis at the origin is defined as y-axis, and a straight line which extends perpendicularly to the paper plane and which passes through the origin for an intersection between the x-axis and the y-axis is defined as z-axis. In this case, the tilt angle is an angle between a component, of a straight line indicating the ion implantation direction, on an x-y cross section, and the y-axis, and the twist angle is an angle between a component, of the straight line indicating the ion implantation direction, on an x-z cross section, and the x-axis.
In
In
Now, a mask such as a photo-resist may be formed on the gate electrode 19 before formation of the recessed portion 12a. As a result, it is possible to prevent the impurity ions from being implanted into a channel region.
Here, an example of an ion implantation condition for formation of the recessed portion 12a is as follows:
In
In
It can be understood from
Though the formation of the recessed portion 12a is performed before formation of the source diffusion layer 14 and the drain diffusion layer 15 in the fourth embodiment, the formation of the recessed portion 12a may be performed after formation of the source diffusion layer 14 and the drain diffusion layer 15.
In
In
According to the fabrication steps of the fifth embodiment, even when the height of the gate electrode is low, the ions can be prevented from being implanted into the channel region right under the gate oxide film in the ion implantation for increasing the junction area. As a result, it is possible to fabricate a high quality semiconductor device.
Here, an example of an ion implantation condition for formation of the n-type buried well 12 and the p-type floating well 13 is as follows.
(1) n-Type Buried Well 12:
(2) p-Type Floating Well 13:
In
In
Here, an example of an ion implantation condition for formation of the recessed portion 12a is as follows:
In
In
It can be understood from
According to the fabrication steps in the sixth embodiment, the ion implantation is performed through the opening formed by peeling off the dummy gate, so that the recessed portion can be easily formed at the junction interface between the p-type floating well and the n-type buried well. This results in the increase of the junction area, and thus the capacity required to accumulate the holes can be increased. As a result, it is possible to increase the signal amount during the memory operation.
The following modifications can be made, for example, as explained below.
(1) The conductivity types of the n-type buried well 12, the p-type floating well 13, the source and drain diffusion regions 14 and 15, and the like may be changed to opposite conductivity types, respectively.
(2) Any other shapes, such as a round recessed shape (
(3) Any other elements other than P may also be adopted as an n-type impurity, and any other elements other than B may also be adopted as a p-type impurity.
(4) The recessed portion 12a may be replaced by a projected portion. In such a case, the STI portion 90 may be deeper than a case where the recessed portion 12a is formed.
It should be noted that the present invention is not limited to the above-mentioned embodiments of the present invention, and thus the various modifications can be made without departing from or changing the technical idea of the present invention.
Claims
1. A semiconductor device, comprising:
- a substrate;
- a floating body region formed in the substrate,
- a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and
- source and drain regions, respectively, formed on second and third surface regions of the floating body region, the source region being connected to a source line and providing a first electric capacity at an interface relative to the floating body region, the drain region being connected to a bit line and providing a second electric capacity at an interface relative to the floating body region, the second electric capacity being smaller than the first electric capacity.
2. The semiconductor device, as defined in claim 1, wherein:
- the floating body region is formed on a semiconductor layer which is formed in the substrate, the semiconductor layer being opposite in conductivity type to the floating body region.
3. The semiconductor device, as defined in claim 2, wherein:
- the substrate is a p-type Si substrate;
- the semiconductor layer is a n-type buried well;
- the floating body region is a p-type floating well; and
- the source and drain regions are, respectively, n-type source and drain diffusion layers.
4. The semiconductor device, as defined in claim 3, wherein:
- the p-type floating well is a memory region in which holes are accumulated and from which the holes are released.
5. The semiconductor device, as defined in claim 4, wherein:
- the bit line is applied with a first voltage to write a first data state into the memory region in which the holes are accumulated, a second voltage to write a second date state thereinto from which the holes are released, and a third voltage which is lower than the first voltage and higher than the second voltage to hold the first or second data state which is written into the memory region.
6. The semiconductor device, as defined in claim 3, wherein:
- the p-type floating well, the n-type source and drain diffusion layers, the gate insulating film, and the gate electrode constitute a MOS transistor, the MOS transistor being separated from adjacent MOS transistors by separating regions, each of which reaches from a surface of the substrate to the n-type buried well.
7. The semiconductor device, as defined in claim 3, wherein:
- a distance between a central line of the gate electrode and a remote end of the n-type drain diffusion layer is shorter than a distance between the central line and a remote end of the n-type source diffusion layer.
8. The semiconductor device, as defined in claim 3, wherein:
- an impurity concentration of the n-type drain diffusion layer is smaller than an impurity concentration of the n-type source diffusion layer.
9. The semiconductor device, as defined in claim 1, wherein:
- the word line is of a wiggle structure.
10. A semiconductor device, comprising:
- a semiconductor substrate;
- a first conductivity type buried well formed in the semiconductor substrate;
- a second conductivity type floating body region formed on the first conductivity type buried well;
- a gate electrode formed above a first surface region of the second conductivity type floating body region via a gate insulating film;
- first conductivity type source and drain regions, respectively, formed on second and third surface regions of the second conductivity type floating body region; and
- a structure of increasing an electric capacity formed at an interface between the first conductivity type buried well and the second conductivity type floating body region.
11. The semiconductor device, as defined in claim 10, wherein:
- the structure includes a recessed portion formed at a junction interface of the first conductivity type buried well relative to the second conductivity type floating body region.
12. The semiconductor device, as defined in claim 11, wherein:
- the recessed portion is formed in accordance with the junction interface which is deeper at a portion below the gate electrode than at portions below the first conductivity type source and drain regions.
13. The semiconductor device, as defined in claim 11, wherein:
- the recessed portion is of a width as at least twice as a width of a depletion layer from a side of the second conductivity floating body region, and a depth not smaller than the width of the depletion layer therefrom.
14. The semiconductor device, as defined in claim 11, wherein:
- the recessed portion is of a substantially right angle at corners.
15. The semiconductor device, as defined in claim 11, wherein:
- the recessed portion is of a round shape at corners.
16. The semiconductor device, as defined in claim 11, wherein:
- the recessed portion is for a part of a concave and convex shape.
17. A method of fabricating a semiconductor device, comprising:
- forming a first conductivity type buried well in a semiconductor substrate;
- forming a second conductivity type floating body region on the first conductivity type buried well; and
- forming a structure of increasing an electric capacity at an interface between the first conductivity type buried well and the second conductivity type floating body region.
18. The method of fabricating a semiconductor device, as defined in claim 17, wherein:
- forming the structure comprises:
- forming a recessed portion at a junction interface of the first conductivity type buried well relative to the second conductivity type floating body region.
19. The method of fabricating a semiconductor device, as defined in claim 18, wherein:
- forming the recessed portion, comprises:
- forming a gate electrode above the second conductivity type floating body region via a gate insulating film; and
- implanting first conductivity type ions into a portion above the junction interface of the second conductivity type floating body region by using the gate electrode as a mask.
20. A method of fabricating a semiconductor device, as defined in claim 18, wherein:
- forming the recessed portion, comprises:
- forming a dummy gate electrode above the second conductivity type floating body region;
- forming an insulating film to surround the dummy gate electrode,
- forming an opening through the insulating film by removing the dummy gate electrode; and
- implanting second conductivity type ions into a portion below the junction interface of the first conductivity type buried well through the opening.
Type: Application
Filed: Jul 13, 2006
Publication Date: Jan 18, 2007
Applicant:
Inventors: Naoki Kusunoki (Tokyo), Mutsuo Morikado (Kanagawa)
Application Number: 11/485,278
International Classification: H01L 29/76 (20060101);