Load adaptive class de driving amplifier for piezoelectric actuators

Abstract

An improved system and method for driving piezoelectric actuators for devices such as camera modules. The present invention replaces a conventional class D amplifier with a class DE amplifier. The class DE amplifier eliminates the switching losses that would otherwise occur when a class D amplifier is used. The present invention can also adjust the dead time of the amplifier based upon varying ambient temperature levels.

Description

FIELD OF THE INVENTION

The present invention relates generally to the use and function of miniaturized camera products. More particularly, the present invention relates to the use of amplifiers to drive piezoceramic actuators in miniaturized camera products.

BACKGROUND OF THE INVENTION

Traditionally, lenses in autofocus and zoom lens systems have been moved using stepping or electrostative motors. These types motors have been developed and used over the course of a number of decades and are now considered a relatively mature technology. However, for mobile imaging telephones, these motors are quite large and have substantially reached their limit in terms of potential miniaturization. In particular, these motors become less efficient and more and more heat is generated by such motors relative as they become smaller in size.

In contrast, motors based on piezoelectric elements can be significantly smaller in size, and their power consumption can be lower than in stepping and electrostative motors. Motors using piezoceramic materials are also not as fragile as stepping motors, and fewer different components are needed to make the motors operate in a simpler way. Additionally, the process for manufacturing multilayer piezoelectric ceramic materials is somewhat similar to processes for manufacturing multilayer ceramic capacitors, meaning that the same machinery can be used to manufacture piezoelectric actuators, and that a high volume of such components can be produced in a fast and cost effective manner. Furthermore, the audible noise generated from a piezoelectric motor is quite small due to ultrasonic driving frequencies and is much less noticeable than the noise resulting from the use of stepping motors. An exploded isometric view of a camera module 100 including such a piezoelectric element 110, logical circuitry 120, support tube 130, and housing 140 is depicted in FIG. 1.

Previously, class D amplifiers have been used to drive piezoceramic actuators. A class D amplifier is an amplifier in which the output transistors are operated as switches rather than as a current source. Because an ideal switch has either zero voltage across it or zero current through it at all times, it dissipates no power. When a particular transistor is turned off, the current through it is zero. When the transistor is turned on, the voltage across the switch is small (ideally zero). This increases the overall efficiency of the amplifier, requiring less power from the power supply and smaller heat sinks for the amplifier.

A conventional tuned class D type of amplifier is shown in FIG. 9(a) and shows the principle of class D operation. A class D amplifier includes a P-type FET (PFET), an N-type FET, (NFET) two body diodes and a tuned load. The two FET gates are driven with signals that are about identical, but that prevents a simultaneous state of the two FET gates and a large shoot through current flow from the supply to ground. The switching frequency f_switching of the drive signals is about the same as the resonance frequency formed by L1 and C_piezoload and a duty cycle D of drive signals about 0.5. Consequently, when the PFET is on, the NFET is off and vice versa. The pair of FET gates are equivalent to a double pole switch that define a rectangular output voltage from V_DC to 0. The load is connected to V_out, the output node of the amplifier. The load is formed by a piezoceramic actuator and an inductor that are tuned to a switching frequency resulting in a sinusoidal output at point V_ACT.

Another version of class D amplifier is shown in FIG. 9(b), where a rectangular waveform is applied to a low-pass filter, embodied by inductor Lfilter, rather than a tuned filter. The low-pass filter allows only its slowly-varying DC or average voltage to appear on the load. Different pulse widths produce different average outputs. A controlled variation of the pulse width causes the output to vary in order to produce a desired signal. This means that the duty cycles of the two switches are not equal and about 0.5, but the sum of the sum of the duty cycle of the first switch and the duty cycle of the second switch D₁+D₂≈1. This is known as pulse width modulation (PWM). In FIG. 9(b), separate V_P and V_N drive stages are shown. These can be used to make the drive signals for V_P and V_N such that a simultaneous ON state for the two semiconductor switches can be prevented. The circuit shown in FIG. 9(a) can also have such driving of the gates. In FIG. 9(c), the PWM_IN signal used to drive the V_P and V_N drive stages and the resulting V_act is shown. In this example, a rhombic waveform is used to drive the actuator, and the filtered signal V_act approximates the rhombic waveform. Also, the PWM_IN signal can be such that the duty cycle of a class D amplifier differs from constant by 0.5.

Although reasonably useful, class D amplifiers suffer from significant drawbacks. The major factors limiting the performance of class D inverters are switching losses and switching noise as discussed below. Although, in contrast to class A, B, and C amplifiers, switched mode power amplifiers such as class D amplifiers have an idealized efficiency of 100%, the combination of switching and conduction losses sets an upper bound on the amplifiers' power efficiency.

An important switching loss that occurs at the turn on transition is due to the discharge of the energy stored in the in the parasitic output capacitance of the large output power devices. In a class D circuit of the type shown in FIGS. 9(a) and 9(b), there are two devices that switch on and off alternately. If the first device is off, then the voltage across it is equal to the rail voltage V_DC, and the energy stored in the output capacitor C_parasitic is E=0.5*C*(V_dc)². The discharge power loss is P=0.5*C*(V_dc)²f. Simultaneously, the capacitor of the second device is charged through the resistance of the first device to the rail voltage. The charging process dissipates an amount of energy equal to energy amount being stored. Therefore, the turn on loss in the class D circuit at every switching transition will be twice the amount of the loss. Because there are two switching transitions per cycle, the total turn on loss will be four times the discharge power loss. Additionally, the charging and discharging of the gate capacitance of the switch devices also causes power loss, especially at high switching frequencies. Furthermore, class D amplifiers also suffer from conduction losses. Conduction losses include all of the power dissipation that is caused by the resistances associated with the semiconductors switches.

Because switching losses increase with the square of the supply voltage and linearly with the operating frequency, the operating frequencies of class D inverters are limited.

SUMMARY OF THE INVENTION

The present invention provides for the use of class DE amplifiers in conjunction with piezoceramic elements for actuating digital camera systems such as autofocus and zoom lens systems. In class DE amplifiers, switching losses are reduced in comparison to class D amplifiers. Each switching transistor in a class DE amplifier is on for less than a half period. There are two intervals of time in a period when both of the transistors are simultaneously off, which is referred to as dead time. During these intervals of “under lapping,” the shunt capacitances are recharged by the load current from 0 to V_max or from V_max to 0. Each transistor is therefore turned on under its output voltage V_out≈0. Therefore, the switching power losses are substantially absent. In addition, electromagnetic interference is reduced because of “soft switching” during the dead time of the switches.

The circuit used in conjunction with the present invention adapts in real-time to different loads in order to ensure the class DE switching conditions by changing the dead time. Additionally, different dead times can be used in the present invention for different temperatures, further enhancing the efficiency of the system.

These and other objects, advantages and features of the invention, together with the organization and manner of operation thereof, will become apparent from the following detailed description when taken in conjunction with the accompanying drawings, wherein like elements have like numerals throughout the several drawings described below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exploded isometric view of a miniaturized camera and zoom for a mobile telephone according to one embodiment of the present invention;

FIG. 2 is a perspective view of a mobile telephone that can incorporate a camera module constructed according to the principles of the present invention;

FIG. 3 is a schematic representation of the telephone circuitry of the mobile telephone of FIG. 2;

FIG. 4 is a representation showing the multiplayer structure of a piezoceramic element;

FIGS. 5(a)-5(d) are representations showing the bending of a piezoceramic element based upon the respective phases for the piezoceramic element;

FIG. 6 is a representation of a piezoceramic element as a capacitive load;

FIGS. 7(a)-7(c) are representations of an equivalent circuit for a piezoceramic element;

FIGS. 8(a)-8(d) are plots showing the output data for resistors and capacitors in series and in parallel, respectively, as a function of frequency for a piezoceramic motor;

FIG. 9(a) is a representation of a conventional class D amplifier; FIG. 9(b) shows a second version of a class D amplifier, where a rectangular waveform is applied to a low-pass filter rather than a tuned filter; and FIG. 9(c) are plots showing the PWM signal used to drive the V_P and V_N drive stages and the resulting V_act.

FIG. 10(a) is a representation of a class DE amplifier that can be used in a system of a present invention; and FIGS. 10(b)-10(d) show different switching situations for the class DE amplifier of FIG. 10(a);

FIG. 11 shows the various waveforms formed by a class DE amplifier such as the amplifier shown in FIG. 10(a);

FIG. 12 a depiction of an analog DTLL according to the principles of the present invention;

FIG. 13 is a representation of a real-time adaptation circuit constructed according to one embodiment of the present invention;

FIG. 14 shows the resultant drive signals using the real-time adaptation circuit of FIG. 13;

FIG. 15 is a representation showing how the phase differences in a class DE amplifier, where more current is triggered, can be different in absolute value depending upon which phase leads;

FIG. 16(a) is a schematic representation of a system according to the principles of one embodiment of the present invention, where different dead times can be utilized for different temperature areas; and FIG. 16(b) shows the drive signals for a class DE amplifier inside two different temperature areas;

FIG. 17 is a plot showing the effect of up and down pulses being applied by a linear phase detector to a charge pump;

FIG. 18 is a representation of a basic complementary voltage-switching tuned class DE amplifier according to one embodiment of the present invention; and

FIG. 19 shows a second version of a class DE amplifier, where a rectangular waveform is applied to a low-pass filter instead of a tuned filter.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2 and 3 show one representative mobile telephone 12 within which a camera module constructed according to the principles of the present invention may be implemented. It should be understood, however, that the present invention is not intended to be limited to one particular type of mobile telephone 12 or other electronic device. The present invention can also be incorporated into a stand alone digital camera with no additional accessories.

The mobile telephone 12 of FIGS. 2 and 3 includes a housing 30, a display 32 in the form of a liquid crystal display, a keypad 34, a microphone 36, an ear-piece 38, a battery 40, an infrared port 42, an antenna 44, a smart card 46 in the form of a UICC according to one embodiment of the invention, a card reader 48, radio interface circuitry 52, codec circuitry 54, a controller or processor 56 and a memory 58. Individual circuits and elements are all of a type well known in the art, for example in the Nokia range of mobile telephones. A camera module 60 is also operatively connected to the controller or processor 56.

An actuator for a moving zoom lens can comprise a multilayer piezoelectric ceramic element such as the element shown in FIG. 4. The multilayer structure of this type of piezoceramic component reduces the driving voltage near the engine voltages for the mobile telephone 12 or other associated electronic device. However, the capacitive load of such a piezoelement also increases near the engine voltages.

Each piezoceramic element of the type shown in FIG. 4 has four inputs: a supply voltage (VSUPPLY), the ground (GROUND) and two phases (A and B). The two phases (A and B) are used for driving the piezoceramic element backwards or forwards. The phase difference between these two phases is 90 degrees. The direction of the movement depends upon which one of the phases is leading. There is a left and a right bimorph in a piezoceramic element, which means that there are four sections in each element. The driving voltages cause the piezoceramic material to polarize in a certain way. This polarization causes the piezoceramic material to shrink. Depending upon the phases of A and B, two of the four sections are always activated, and there is different bending in the element depending upon the particular phases.

The bending of a piezoceramic element 500 is shown in FIGS. 5(a)-5(d). At FIG. 5(a), A and B are both at about ¾ with respect to the maximum voltage or magnitude. At FIG. 5(b), A is about ¼ and B is about ¾ with respect to the maximum voltage or magnitude. At FIG. 5(c), A and B are both at about ¼ with respect to the maximum voltage or magnitude. At FIG. 5(d), A equals about ¾ and B is about ¼ with respect to the maximum voltage or magnitude. In each piezoceramic element 500, there is a ground and a tip of very hard material, which are represented respectively at 510 and 520 in FIGS. 5(a)-5(d). This tip will touch its counterpart (not shown) during every cycle, causing the counterpart 520 to move slightly depending upon the voltage phases. Passing through all four phases results in an ellipsoidal trajectory for the hard material 520. The movement of the counterpart results in the adjustment of the zoom and/or autofocus feature in the camera module.

From an electrical point of view, a piezoelectric motor can be represented to a first approximation by a resonant network (L_s, C_s, R_s) in parallel with the electrical capacitance C_p of the electrodes. This representation is depicted in FIG. 7(a). At the fixed operating frequency, the equivalent circuit can be simplified to a resistor (R_pe) in parallel with a capacitor (C_pe), as shown in FIG. 7(b). This approximation is valid around the operating frequency. The capacitance and inductance are caused by the shape alternation of the material. The ability to store energy as elastic energy in the driving element and as a kinetic energy of the different moving portions of the driving element defines quantities of the capacitance and inductance. The equivalent parallel components (R_pe and C_pe) can be found by connecting the device to a network analyzer and making the appropriate calculations from measurement data. The measurement data can also be used to calculate a series equivalent circuit, with series components (R_se and C_se), which is represented in FIG. 7(c). The results of these measurements are shown as a function of the frequency in FIG. 8(a)-8(d). The electrical equivalent circuit at DC can be measured by a multimeter and is represented in FIG. 6 where VPLUS and VMINUS represent electrodes across which, a voltage can be applied.

The present invention provides a solution to the problem of power dissipation presented in class D amplifiers while also being adaptable to different load conditions. In class DE amplifiers, switching losses are reduced. Each switching transistor in a class DE amplifier of the present invention is on for less than half of a period. There are two intervals of time in a period where both of the transistors are simultaneously off. During this dead time, the shunt capacitances are recharged by the load current from 0 to V_max or from V_max to 0. Each transistor is therefore turned on under its output voltage V_out≈0, and, hence, the switching power losses are absent.

The basic complementary voltage-switching tuned class DE amplifier is presented in FIG. 18. The class DE amplifier includes two active devices, each of which operates as a switch, and a series resonant output circuit. The resonant output circuit includes a coil and a piezoelement. The capacitor C can comprise the intrinsic parasitic capacitance of the device, or it can comprise an independent capacitor. The two drive stages are used to create dead time during which both switches are off between switching moments of the switches.

FIGS. 10(a)-10(d) and FIG. 11 can be used to depict the operation of a Class-DE amplifier. The piezoceramic element is represented by the equivalent electrical circuit in FIG. 10(a), and switches are constructed with two NPN transistors (Q1 and Q2). FIGS. 10(b) and 10(c) are representations showing the function of the circuit when the switches are alternately on and off, respectively. The two switches are driven so that the drive signals have a duty ratio of D (i.e., Q1 drive+Q2 drive), wherein 0<D<1. Each drive level (Q1 and Q2) will have a duty ratio less than 1. This is in contrast to class D amplifiers that have a duty cycle of D≈0.5. Therefore, there are two intervals of time in a period where both transistors are simultaneously off, which is represented in FIG. 10(d). This dead time is identified in the wave forms of FIG. 11. During these intervals of under lapping, the shunt capacitances are recharged by the load current from 0 to V_dc or from V_dc to 0. As discussed above, each transistor is therefore turned on under its output voltage at V_out=0 and the switching power losses are substantially absent.

The operation such a system over a simple cycle is as follows. During phase ‘a,’ illustrated in FIG. 11, the transistor Q1 of FIG. 10(a) has a drive level applied to its base terminal, and the duty cycle of the drive signal is less than 0.5. During phase ‘a’, the transistor Q2 is active, and a short circuit effectively exists between the collector and emitter terminals of the transistor Q1. This is illustrated by V1,a of FIG. 10(b). A voltage V2,a exists across the shunt capacitor C associated with the transistor Q2 during this phase, while a load current ia exists. When the drive level is no longer applied to the transistor Q1, this signifies the beginning of the second phase ‘b’. During phase ‘b,’ a voltage V2,b exists, and the capacitor C associated with the transistor Q2 is discharged. This can be observed in the plot of V2 in FIG. 11. Energy from this capacitor C is transferred to the load components, L_o, C_o and R of FIG. 10(b). Simultaneously, current i_b from the load components is transferred to the capacitor C associated with the transistor Q1, and this capacitor C is charged during phase ‘b,’ while a voltage V1,b exists across this capacitor C. This can be observed in the plot of V1 in FIG. 11.

When the voltage across the capacitor C associated with the transistor Q2 is zero (i.e., it has discharged its energy), a drive level is applied to the transistor Q2. This signifies the beginning of the third phase ‘c’. During phase ‘c,’ the transistor Q2 is active, and a short circuit effectively exists between the collector and the emitter terminals of the transistor Q2. This is illustrated by V2,c in FIG. 10(c). A voltage V1,c exists across the capacitor C associated with the transistor Q1, along with load current, i_c during this phase. When the drive is no longer applied to the transistor Q2, this signifies the beginning of the fourth phase ‘d’. During phase ‘d,’ a voltage V1,d exists across the capacitor C associated with the transistor Q1, when the capacitor C is discharged. This is observable in the plot of V1 in FIG. 11. Energy from the capacitor C is transferred to the load components, L_o, C_o and R of FIG. 10(d). Simultaneously, current i_b, i_d from the load components is transferred to the capacitor C associated with the transistor Q2, and this capacitor C is charged during phase ‘d,’ where a voltage V2,d exists across this capacitor C. This can be seen in the plot of V2 in FIG. 11. The phases then cycle so that phase ‘a’ follows phase ‘d,’ and the process begins again. It should be noted that FIGS. 10(a)-10(d) also indicate the respective saturation and capacitor currents during phases a, b, c, and d, represented by I_C2,a, I_S1,a, I_S2,c, I_C1,c, I_C2,b, I_C2,d, I_C1,b, I_C1,d, as well as the voltages (Va, Vb, Vc, and Vd) present across the load component C_o. It should also be noted that for reference, the current through transistors Q1 and Q2, represented by IS1 and IS2, and the current through the respective shunt capacitors across transistors Q1 and Q2, represented by IC1 and IC2, are shown in FIG. 11. In addition, FIG. 11 indicates the angular time, represented by θ, where θ¹ and θ² respectively encapsulate dead times during a cycle as discussed above.

Another version of the effect of a class DE amplifier is shown in FIG. 19, where a rectangular wave form is applied to a low-pass filter instead of a tuned filter. The low-pass filter allows only its slowly varying DC or average voltage to appear on the load. Different pulse widths product different average outputs. The controlled variation of the pulse width causes the output to vary in order to produce a desired signal. This is known as pulse width modulation (PWM). In this case, there are two time intervals in a PWM period where both transistors are simultaneously off, which is represented in FIG. 19, which is contrary to a conventional class D low-pass filtered amplifier. This means that the sum of the duty cycle of the first switch D₁ and the duty cycle of the second switch D₂ is less than 1. During these intervals of underlapping, the shunt capacitances are recharged by the load current from 0 to V_DC or from V_DC to 0.

An issue that is raised with class DE amplifiers involves the fact that the duration of the optimum dead time is a function of equivalent electrical circuit components. These components build up from the piezoactuator and electronic driving components. These components can vary with time or from sample to sample. Example of factors causing such variance include environmental changes such as temperature, wear and change in mechanical workload as the actuator is lifting or bring down the lens load, and tolerances in the load. In particular, the piezoceramic actuator has a high temperature coefficient for its equivalent capacitance C_pe. Additionally, the value for C_parasitic can vary from one amplifier to another. These issues can be addressed by introducing a circuit that adapts the dead time to the surrounding circumstances.

In the past, suitable adaptation circuits have been presented for DC/DC converters or (regulators), but not for amplifiers. Such adaptation circuits check the voltage across the switching devices and adjust the switching moment to be equal to the moment when the voltage over the switch is approximately zero. For class D amplifiers in audio and induction motor applications, the dead time must be made as short and constant as possible in order to not introduce harmonic distortions to the output signal. This is a potential reason why such adaptation mechanisms are not commonly used in conjunction with amplifiers.

According to one embodiment of the present invention, an adaptation system can be used where different dead times are utilized for different temperature areas. In such a system, the temperature is checked before an action is taken, and a fixed dead time period is chosen based upon the temperature information. FIG. 16(a) is a schematic representation of such a system, where a temperature sensor 200 directly interacts with the digital logic drive pattern generation 210 for the drive stage 220 of the class DE amplifier. FIG. 16(b) shows drive signals for class DE amplifier inside two different temperature areas. The dead times (Dt1 and Dt2) are different inside the two shown temperature areas

A real time load adaptation circuit of the present invention is shown in FIG. 13. The adaptation circuit comprises a high side delay time locked loop (DTLL), a low side DTLL, two voltage references Vtp and Vtn, which are equal to the threshold voltages (Vt) of the P-type FET and the N-type FET, respectively, gate driving buffers B1 (inverting) and B2 (non-inverting) and a PWM driving pattern input. The adaptation circuit of the present invention delays the control signals VP and VN driving the P-type FET and the N-type FET generated from the PWM input control signal real time so that there is an optimal dead time between the control signals VP and VN, and that the switching is made when the voltage over the switches is about 0 (V_DS≈0) despite the varying loading conditions. The circuit monitors the moments when the voltage over the switch FETs, the drain to source voltage (Vd to Vs, or Vds) is zero and when gate driving voltage is turning on the switch fet and forces these moments to be equal by changing the delay between PWM input and VP and VN. The input PWM driving pattern and optimally delayed gate driving signals produced by circuitry shown in FIG. 13 are depicted in FIG. 14.

An analog DTLL is depicted in FIG. 12. The DTLL comprises two comparators, C1 and C2, a phase detector and phase difference calculation logic and charge pump, a filter capacitor C_cp, and delay generator logic. The delay generator also includes a N-FET, a current source I_d1, a comparator C3 and a capacitor C_d1. The charge pump includes adjustable current sources whose value is controlled by phase difference logic. The current source that is activated is selected by up or down pulses.

The comparators sense the power mosfet's Vds (drain to source voltage) zero-voltage crossing and gate to source voltage (V_gs) threshold voltage crossing. Comparator outputs are connected to a linear phase detector, which is an asynchronous logic circuitry that provides up/down pulses for charge pumping by detecting timing differences between the rising edges of X and G (outputs of the comparators). This is represented in FIG. 17. Depending upon the phase difference, the phase detector forces the charge pump output voltage V_cp, either rising or falling by letting the IP or IN currents charge or discharge the capacitor C_cp, with the time being proportional to the phase difference. If there is any timing error between threshold voltage and the zero-voltage crossings, it will be fed back and a pulse width equal to the error is generated to adjust the output of the charge pump such that the dead time change will be reflected in the next switching cycle.

The gain of the loop is $G=\frac{I_{\mathrm{CP}}}{I_{\mathrm{DL}}}·\frac{C_{\mathrm{DL}}}{C_{\mathrm{CP}}}\approx 1.$
G must be sufficiently large to obtain fast tracking without leading to instability (i.e., G>2) in this discrete time system with a fixed one-cycle delay.

In contrast to conventional systems, the circuit of the present invention does not use one-shots to decrease the gain when the phase difference between x and g is small. A phase difference counter is used to adjust the charge pump current by a smaller amount when the phase difference is smaller than a certain threshold phase difference. The increased charge pump current increases the gain. The greater charge pump current makes possible the fast settling when phase difference is great. The small gain makes it possible to resolve small timing errors, preventing instability while approaching a steady state.

The phase difference calculation logic triggers counter from the rising edge of the either of the inputs and, after a certain threshold time t2-t1 has commenced before the second input rising edge has come, it will increase the current of the charge pump. The effective charge pump current (I_cp) is the time average of current. After the second input's signals edge is detected, the charge pump current goes to zero. By increasing the I_cp when the phase different is great, the gain of the loop is increased and greater errors in the right switching timing are more quickly resolved. When the difference is small, the effective current is smaller and the loop behavior is more stable, near a steady state. The phase differences where more current is triggered can be different in absolute value depending upon which phase leads. This is shown by P1 and P2 in FIG. 15. Also the current can be different.

The adaptation circuits of the present invention can be used to control tuned Class-DE amplifiers driving piezoceramic actuators, as well as low pass filtered Class-DE amplifiers driving piezoceramic actuators. It should also be noted that the present invention can be used in comjunction with a variety of amplifiers. For example, the present invention can be used in conjunction with a Class-D, zero-voltage switching inverter with a single shunt capacitor.

The soft switching system described herein reduces the switching noise in the amplifier, resulting in improved electromagnetic interference (EMI) performance. This is due to the gentle gradient during the dead time in V₁ and V₂, as shown in FIG. 11, which is contrary to the sharp edges resulting from class D amplifiers.

The C₀ in FIGS. 10(a)-10(d) can comprise either a large capacitor connected in series to a piezo actuator, or the piezoelement's electrical capacitance can be used alone to form an LC circuit. By using the additional capacitance, which is about ten times larger than the piezo capacitance, the temperature dependency of the LC resonance because of piezo capacitance can be reduced. The C_parasitic value can comprise either device capacitances or additional (external) capacitances. External fast schottky diodes can also be used in parallel with the body diodes of FIGS. 9 and 13. The inductor L₀ can be formed by a PWB line pattern, or it can be a packaged circuit component.

The present invention is described in the general context of method steps, which may be implemented in one embodiment by a program product including computer-executable instructions, such as program code, executed by computers in networked environments. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps.

The foregoing description of embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the present invention. The embodiments were chosen and described in order to explain the principles of the present invention and its practical application to enable one skilled in the art to utilize the present invention in various embodiments and with various modifications as are suited to the particular use contemplated. Hamill teaches a class DE amplifier circuit in which the system maintains a gate control voltage to switch on a transistor of the class DE amplifier while the drain-source voltage is zero. Applicant respectfully disagrees with this position. In particular, Applicant submits that Hamill fails to disclose anything related to gate and source voltages. In the Introduction of Hamill, class D and class E amplifiers are merely discussed as prior art amplifiers. There is nothing suggesting that the gate and source voltage of transistors in a class DE amplifier are maintained as required in claims 19 and 24. Therefore, Hamill fails to cure all of the deficiencies of Kaneko et al.

Regarding claims 3, 4, 11, 12, 17, and 18, the Examiner correctly recognized that neither Kaneko et al. nor Hamill teach adjusting dead time of a class DE amplifier either to correspond to one of a plurality of predefined dead times based upon a measured ambient temperature or by using an algorithm based on measure ambient temperature. However, the Examiner asserted that Ohkuri teaches the use of predefined fixed dead times based upon a measure of ambient temperature, and the use of an algorithm that considers the measured ambient temperature. Applicant respectfully disagrees with the Examiner's position.

In particular, Applicant submits that Ohkuri does not teach or suggest adjusting dead time to one of a plurality of predefined fixed dead times or the use of any algorithm for determining an adjusted dead time. Ohkuri merely teaches one method of adjusting dead time, i.e., continually elongating dead time by increasing the number of serially connected devices until a maximum threshold is reached, at which time, operation of a switching element is stopped as described in paragraphs [0062]-[0070]. By contrast, claims 3, 11, and 17 require that the dead time is adjusted to correspond to one of a plurality of predefined, fixed dead times based on the measured ambient temperature. In addition, claims 4, 12, and 18 require adjusting dead time based on an algorithm that considers the measured ambient temperature. Because Ohkuri only teaches continually elongating dead time until a maximum threshold is reached, there cannot be any algorithm used. Therefore, various embodiments of the present invention allow for true adaptation of dead time according to ambient temperature, whereas Ohkuri merely teaches driving a circuit to its limit and then backing off. As such, Ohkuri fails to cure the deficiencies of Kaneko et al. and Hamill.

Claims

1. A method of driving a piezoelectric actuator, comprising:

operatively connecting a class DE amplifier to a piezoelectric element, the class DE amplifier including first and second transistors;

applying a driving voltage the first and second transistors such that the duty cycle is 0<D<1; and

discharging a shunt capacitor associated with the first transistor when the first and second transistors are off, causing the first transistor to be turned on when the voltage across shunt capacitor is zero,

wherein application of the driving voltages alters the relative position of the piezoelectric element.

2. The method of claim 1, further comprising:;

operatively connecting a temperature sensor to the class DE amplifier;

measuring the ambient temperature through the temperature sensor; and

adjusting dead time during which both transistors in the class DE amplifier are in an off state based upon the measured ambient temperature

3. The method of claim 2, wherein the dead time is adjusted to correspond to one of a plurality of predefined fixed dead times based upon the measured ambient temperature.

4. The method of claim 2, wherein the dead time is adjusted based upon an algorithm taking into account the measured ambient temperature

5. The method of claim 1, wherein the piezoelectric element comprises a piezoceramic material.

6. The method of claim 1, wherein the piezoelectric element is operatively connected to an actuator, and wherein the electrical state of the piezoelectric element affects the relative position of the actuator.

7. The method of claim 6, wherein movement of the actuator caused by changes in the electrical state of the piezoelectric element causes a corresponding movement in a camera lens system.

8. A method of driving a lens in a camera module, comprising:

positioning a piezoelectric element to engage an actuator for a lens in a camera module;

operatively connecting a class DE amplifier to the piezoelectric element, the class DE amplifier including first and second transistors;

driving the first and second transistors such that the duty cycle is 0<D<1; and

discharging a shunt capacitor associated with the first transistor when the first and second transistors are off, causing the associated transistor to be turned on when the voltage across shunt capacitor is zero,

wherein the input of voltage to the amplifier causes movement of the piezoelectric element, resulting in a corresponding movement in the actuator to move the lens.

9. The method of claim 8, wherein the piezoelectric element comprises a piezoceramic material.

10. The method of claim 8, further comprising:

operatively connecting a temperature sensor to the class DE amplifier;

measuring the ambient temperature through the temperature sensor; and

adjusting the dead time during which both transistors in the class DE amplifier are in an off state based upon the measured ambient temperature.

11. The method of claim 10, wherein the dead time is adjusted to correspond to one of a plurality of predefined fixed dead times based upon the measured ambient temperature.

12. The method of claim 10, wherein the dead time is adjusted based upon an algorithm taking into account the measured ambient temperature.

13. The method of claim 1, further comprising charging a capacitor associated with the second transistor when the first and second transistors are off.

14. A piezoelectric actuator system for a camera module, comprising:

a piezoelectric element in at least selective communication with a lens actuator; and

a class DE amplifier including first and second transistors, wherein discharging a shunt capacitor associated with the first transistor when the first and second transistors are off causes the first transistor to be turned on when the voltage across shunt capacitor is zero;

a piezoelectric element in electrical communication with the class DE amplifier; and

an actuator in at least selective contact with the piezoelectric element, wherein varying applied voltage to the class DE amplifier adjusts the relative position of the piezoelectric element, which alters the position of the actuator.

15. The piezoelectric actuator system of claim 14, wherein the piezoelectric element comprises a piezoceramic material.

16. The piezoelectric actuator system of claim 14, further comprising a temperature sensor operatively connected to the class DE amplifier, the temperature sensor measuring the ambient temperature, wherein the dead time during which both transistors in the class DE amplifier are in an off state is adjusted based upon the measured ambient temperature.

17. The piezoelectric actuator system of claim 16, wherein the dead time is adjusted to correspond to one of a plurality of predefined fixed dead times based upon the measured ambient temperature.

18. The piezoelectric actuator system of claim 16, wherein the dead time is adjusted based upon an algorithm taking into account the measured ambient temperature.

19. The piezoelectric actuator system of claim 16, wherein the system maintains a gate control voltage to switch on a transistor of the class DE amplifier while the drain-source voltage is zero.

20. A control circuit for piezoelectric actuation comprising:

a class DE amplifier including a first transistor and a second transistor, the first transistor including a first shunt capacitance and the second transistor including a second shunt capacitance;

a series resonant output circuit coupled to an output and operably connected to the class DE amplifier; and

a driving voltage applied to the first and second transistors having a duty cycle of 0<d<1 and discharging a shunt capacitor associated with the first transistor when the first and second transistors are off, causing the associated transistor to be turned on when the voltage across shunt capacitor is zero,

wherein application of the driving voltage causes the output to actuate a piezoelectric element.

21. The control circuit of claim 20, further comprising a temperature sensor operatively connected to the class DE amplifier, wherein dead time for which the first and second transistors are simultaneously off is adjusted based upon ambient temperature monitored by the temperature sensor.

22. The control circuit of claim 20, wherein the piezoelectric element comprises a piezoceramic material.

23. The control circuit of claim 20, wherein the piezoelectric element comprises part of the series resonant output circuit.

24. The control circuit of claim 20, wherein the control circuit maintains a gate control voltage to switch on a transistor of the class DE amplifier while the drain-source voltage is zero.

25. An imaging device, comprising:

the control circuit of claim 20; and

a lens operatively connected to the control circuit,

wherein the actuation of the piezoelectric element causes a corresponding movement in the lens.

26. A mobile telephone, comprising:

a processor;

a memory unit operatively connected to the processor; and

the imaging device of claim 25 operatively connected to the processor.