REFERENCE TO PRIORITY APPLICATIONS This application is a continuation-in-part (CIP) of U.S. application Ser. No. 11/464,324, filed Aug. 14, 2006, the disclosure of which is hereby incorporated herein by reference. This application also claims priority to Korean Application Serial No. 2005-0081894, filed Sep. 2, 2005, the disclosure of which also is hereby incorporated herein by reference.
FIELD OF THE INVENTION The present invention relates to integrated circuit memory devices and methods of forming same and, more particularly, to non-volatile memory devices and methods of forming non-volatile memory devices.
BACKGROUND OF THE INVENTION One class of nonvolatile memory devices includes electrically erasable programmable read only memory (EEPROM), which may be used in many applications including embedded applications and mass storage applications. In typical embedded applications, an EEPROM device may be used to provide code storage in personal computers or mobile phones, for example, where fast random access read times may be required. Typical mass storage applications include memory card applications requiring high capacity and low cost.
One category of EEPROM devices includes NAND-type flash memories, which can provide a low cost and high capacity alternative to other forms of nonvolatile memory. A typical NAND-type flash memory includes a plurality of NAND-type strings therein that are disposed side-by-side in a semiconductor substrate. Each EEPROM cell within a NAND-type string includes a floating gate electrode and a control gate electrode, which is electrically connected to a respective word line. These EEPROM cells may be cells that support a single or a multi-level programmed state. EEPROM cells that support only a single programmed state are typically referred to as single level cells (SLC). In particular, an SLC may support an erased state, which may be treated as a logic 1 storage value, and a programmed state, which may be treated as a logic 0 storage value. The SLC may have a negative threshold voltage (Vth) when erased (e.g., −3V<Vth<−1V) and a positive threshold voltage when programmed (e.g., 1V<Vth<3V).
The state of an EEPROM cell may be detected by performing a read operation on a selected cell. As will be understood by those skilled in the art, a NAND string will operate to discharge a precharged bit line BL when a selected cell is in an erased state and a selected word line voltage (e.g., 0 Volts) is greater than the threshold voltage of the selected cell. However, when a selected cell is in a programmed state, the corresponding NAND string will provide an open circuit to the precharged bit line because the selected word line voltage (e.g., 0 Volts) is less than the threshold voltage of the selected cell and the selected cell remains “off”. Other aspects of NAND-type flash memories are disclosed in U.S. application Ser. No. 11/358,648, filed Feb. 21, 2006, and in an article by Jung et al., entitled “A 3.3 Volt Single Power Supply 16-Mb Nonvolatile Virtual DRAM Using a NAND Flash Memory Technology,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1748-1757, November (1997), the disclosures of which are hereby incorporated herein by reference.
Operations to program or erase an EEPROM cell may include the application of a relatively high program or erase voltage to the control electrode or channel region of the EEPROM cell, respectively. As will be understood by those skilled in the art, the magnitude of a program voltage should be sufficient to attract a sufficient number of electrons to a floating gate electrode within the cell and the magnitude of the erase voltage should be sufficient to withdraw a high percentage of accumulated electrons from the floating gate electrode. These operations to attract electrons to the floating gate electrode or withdraw electrons from the floating gate electrode result in a change in a threshold voltage of the EEPROM cell. In particular, operations to program an EEPROM cell may result in an increase in the threshold voltage of the EEPROM cell and operations to erase an EEPROM cell may result in a decrease in the threshold voltage of the EEPROM cell, as described above for both single and multi-level cells.
Unfortunately, as EEPROM devices become more highly integrated on a semiconductor substrate, the parasitic capacitance between floating gate electrodes of closely adjacent EEPROM cells may increase. As illustrated by FIGS. 1A-1C, this parasitic capacitance is directly proportional to the area of overlap between adjacent floating gate electrodes and inversely proportional to the lateral distance between adjacent floating gate electrodes. This lateral distance is typically reduced as the level of device integration increases. In particular, FIG. 1A illustrates an array of NAND-type EEPROM devices, which includes a plurality of floating gate electrodes 19 spaced side-by-side in two dimensions (e.g., row and column directions). These floating gate electrodes 19 are separated from active regions 13 of a semiconductor substrate 11 by tunnel insulating layers 17. These active regions 13 are defined by spaced-apart trench isolation regions 15. The control electrodes of each EEPROM cell within a row are commonly connected to respective word lines 23 (shown as word lines A, B and C). Each floating gate electrode 19 is separated from a corresponding word line by an inter-gate dielectric layer 21. As illustrated by FIGS. 1B-1C, the floating gate electrodes 19 are spaced apart from each other in a bit line direction by source/drain regions 25 and are spaced apart from each other in a word line direction by the trench isolation regions 15. The area of overlap between each floating gate electrode in the bit line direction is equivalent to the product h1W1 and the area of overlap between each floating gate electrode in the word line direction is equivalent to the product h1×W2.
These increases in parasitic capacitance caused by higher device integration levels can result in a corresponding increase in floating gate interference. If this interference is sufficiently high, then the programming of one EEPROM cell may result in a threshold voltage shift of one or more closely adjacent EEPROM cells in the neighborhood of the EEPROM cell undergoing programming. Such shifts in threshold voltage can reduce memory device reliability by causing bit errors to occur during data reading operations. These and other consequences of increased parasitic capacitance between floating gate electrodes are described in an article by Jae-Duk Lee et al. entitled “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, Vol. 23, No. 5, pp. 264-266, May (2002).
SUMMARY OF THE INVENTION Embodiments of the invention include non-volatile memory devices having memory cells therein with reduced cell-to-cell coupling capacitance. According to some of these embodiments, non-volatile memory devices, such as NAND-type flash EEPROM devices, include memory cells with floating gate electrodes. These floating gate electrodes are formed to have an open-ended wraparound shape that operates to reduce parasitic cell-to-cell coupling capacitance in a bit line direction while maintaining a high coupling ratio between control and floating gate electrodes within each memory cell. In particular, each memory cell may include an EEPROM transistor therein. Each of these EEPROM transistors includes a tunneling insulating layer on a semiconductor channel region and a floating gate electrode on the tunneling insulating layer. The floating gate electrode has an open-ended wraparound shape that is filled with an electrically insulating region. According to some of these embodiments, the floating gate electrode may be shaped as a rectangular cylinder with a hollow center that is filled with the electrically insulating region.
According to still further embodiments of the invention, a non-volatile memory array includes a semiconductor substrate and at least one NAND-string of EEPROM cells in the semiconductor substrate. The at least one NAND-string of EEPROM cells includes a first non-volatile memory cell having a first open-ended and insulator-filled wraparound-shaped floating gate electrode therein and a second non-volatile memory cell having a second open-ended and insulator-filled wraparound-shaped floating gate electrode therein. The floating gate electrodes are configured so that a longitudinal axis of the first open-ended wraparound-shaped floating gate electrode is collinear with a longitudinal axis of the second open-ended wraparound-shaped floating gate electrode. The at least one NAND-string of EEPROM cells may also include a string selection transistor having a third open-ended insulator-filled wraparound-shaped gate electrode therein and a ground selection transistor having a fourth open-ended insulator-filled wraparound-shaped gate electrode therein. In these embodiments, a word line associated with the first non-volatile memory cell is separated from the first open-ended and insulator-filled wraparound-shaped floating gate electrode by a first inter-gate dielectric layer and a word line associated with the string selection transistor is electrically shorted to the third open-ended and insulator-filled wraparound-shaped floating gate electrode.
Still further embodiments of the invention include a method of forming a non-volatile memory array by forming a semiconductor substrate having first and second trench isolation regions therein that are spaced apart from each other by a semiconductor active region. A tunnel insulating layer is formed on the active region and then a first conductive layer is formed on sidewalls of the first and second trench isolation regions and on the tunnel insulating layer. An insulating region is formed on a portion of the first conductive layer extending opposite the tunnel insulating layer. A second conductive layer is then formed on the insulating region. The second conductive layer, the insulating region and the first conductive layer are then patterned in sequence to define an insulator-filled wraparound-shaped floating gate electrode.
According to further aspects of these embodiments, the patterning step may be preceded by the steps of forming an inter-gate dielectric layer on the second conductive layer and forming a third electrode layer on the inter-gate dielectric layer. The patterning step may also be preceded by a step of forming a contact hole that extends through the inter-gate dielectric layer and exposes the second conductive layer. In this case, the step of forming a third electrode layer may include depositing the third electrode layer into the contact hole. The patterning step may further include patterning the third conductive layer, the inter-gate dielectric layer, the second conductive layer, the insulating region and the first conductive layer in sequence to define a string selection line (SSL) including a first portion of the patterned third conductive layer and an underlying first portion of the patterned second conductive layer that is electrically connected to the first portion of the patterned third conductive layer at the location of the contact hole.
According to still further embodiments of the invention, the patterning step may be followed by the step of removing the patterned insulating region from the wraparound-shaped floating gate electrode. The removing step is followed by a step of depositing a dielectric layer onto the semiconductor substrate to thereby refill an interior of the wraparound-shaped floating gate with an electrically insulating material. This electrically insulating material may have a relatively low dielectric constant (e.g., lower dielectric constant relative to the patterned insulating region that is removed).
A non-volatile memory cell according to additional embodiments of the invention includes a semiconductor substrate having an active region therein, which includes source and drain regions of first conductivity type and a channel region extending between the source and drain regions. A tunnel oxide layer is provided on the channel region and a floating gate electrode is provided on the tunnel oxide layer. The floating gate electrode has an asymmetric transverse cross-section (e.g., L-shaped cross-section) defined by a plurality of segments. These segments include at least one horizontal segment extending laterally across an entire width of the channel region and at least one vertical segment extending upward from a side of the horizontal segment. A control gate electrode is also provided on the floating gate electrode. This control gate electrode is separated from the floating gate electrode by an inter-gate dielectric layer.
A non-volatile memory array according to additional embodiments of the invention includes a semiconductor substrate and a first row of non-volatile memory cells having floating gate electrodes therein with first asymmetric transverse cross-sections. A second row of non-volatile memory cells is also provided. The second row of non-volatile memory cells extends immediately adjacent the first row of non-volatile memory cells. The second row of non-volatile memory cells has floating gate electrodes therein with second asymmetric transverse cross-sections. These second asymmetric transverse cross-sections appear equivalent to the first asymmetric transverse cross-sections when rotated 180° relative to a normal to said semiconductor substrate. These asymmetric floating gate electrodes are preferably formed so that an area of overlap between opposing surfaces of the first and second floating gate electrodes that face each other is less than about 75% of the total transverse cross-sectional area of the first floating gate electrode.
A flash EEPROM array according to another embodiment of the invention includes a first row of EEPROM cells having a first floating gate electrode therein. This first floating gate electrode includes at least one horizontal segment and at least one vertical segment that collectively define a first L-shaped portion of the first floating gate electrode that faces a first direction. A second row of EEPROM cells is also provided, which extends immediately adjacent the first row of EEPROM cells. The second row of EEPROM cells has a second floating gate electrode therein. This second floating gate electrode includes at least one horizontal segment and at least one vertical segment that collectively define a second L-shaped portion of the second floating gate electrode that faces a second direction opposite the first direction.
Methods of forming a flash EEPROM device include forming first and second shallow trench isolation regions at side-by-side locations in a semiconductor substrate to thereby define an active region therebetween. A tunnel insulating region is formed on the active region and an electrically conductive layer is formed on the tunnel insulating layer and on opposing sidewalls of the first and second shallow trench isolation regions. An electrically insulating buffer region is formed on a portion of the electrically conductive layer extending between the opposing sidewalls of the first and second shallow trench isolation regions. A floating gate electrode mask pattern is formed on the electrically insulating buffer region and on the electrically conductive layer. A step is then performed to selectively etch the electrically conductive layer to define an L-shaped floating gate electrode extending between the opposing sidewalls of the first and second shallow trench isolation regions. This selective etching step is performed using the electrically insulating buffer region and the floating gate electrode mask pattern as an etching mask.
According to additional embodiments of the invention, the step of selectively etching the electrically conductive layer is followed by the steps of removing the floating gate electrode mask pattern and at least a portion of the electrically insulating buffer region and depositing an inter-gate dielectric layer on the L-shaped floating gate electrode. The depositing step may also be preceded by a step of etching back the opposing sidewalls of the first and second shallow trench isolation regions.
These methods may also include depositing a conductive layer on the inter-gate dielectric layer and then patterning the conductive layer to define a word line extending opposite the L-shaped floating gate electrode. The step of forming the tunnel insulating region may include thermally oxidizing a portion of the active region extending between the first and second trench isolation regions. The step of forming first and second shallow trench isolation regions includes selectively etching first and second stripe-shaped trenches at side-by-side locations in the semiconductor substrate, filling the first and second stripe-shaped trenches with first and second electrically insulating regions and etching back sidewalls of the first and second electrically insulating regions.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a perspective view of a conventional NAND-type EEPROM device.
FIG. 1B is a cross-sectional view of a portion of the NAND-type EEPROM device of FIG. 1A, taken along the word line direction I-I′ in FIG. 1A.
FIG. 1C is a cross-sectional view of a portion of the NAND-type EEPROM device of FIG. 1A, taken along the bit line direction II-II′ in FIG. 1A.
FIG. 2A is a plan layout view of a NAND-type EEPROM device according to embodiments of the present invention.
FIG. 2B is a cross-sectional view of the NAND-type EEPROM device of FIG. 2A, taken along the line B-B′ in FIG. 2A.
FIG. 2C is a cross-sectional view of the NAND-type EEPROM device of FIG. 2A, taken along the line C-C′ in FIG. 2A.
FIG. 2D is a cross-sectional view of the NAND-type EEPROM device of FIG. 2A, taken along the line D-D′ in FIG. 2A.
FIGS. 3A-3I and 4A-4I are cross-sectional views of intermediate structures that illustrate methods of forming EEPROM devices according to embodiments of the present invention.
FIGS. 5A-5E and 6A-6E are cross-sectional views of intermediate structures that illustrate methods of forming EEPROM devices according to embodiments of the present invention.
FIG. 7A is a perspective view of a portion of a flash EEPROM array having L-shaped floating gate electrodes that are arranged in an alternating left/right sequence, according to embodiments of the present invention.
FIG. 7B is a perspective view of a portion of a flash EEPROM array having L-shaped floating gate electrodes that are arranged in an alternating left/right sequence, according to embodiments of the present invention.
FIG. 7C is a cross-sectional view of the flash EEPROM array of FIG. 7B, taken along line C-C′.
FIG. 7D is a cross-sectional view of the flash EEPROM array of FIG. 7B, taken along line D-D′.
FIG. 7E is a cross-sectional view of the flash EEPROM array of FIG. 7B, taken along line E-E′.
FIG. 8 is a perspective view of a portion of a flash EEPROM array having L-shaped floating gate electrodes, according to embodiments of the present invention.
FIGS. 9A-9M are cross-sectional views of flash EEPROM cells having L-shaped floating gate electrodes, according to embodiments of the present invention.
FIGS. 10A-10J and 11A-11J are perspective and cross-sectional views of intermediate structures that illustrate methods of forming an EEPROM array according to embodiments of the present invention.
FIG. 12A-12B are perspective views of intermediate structures that illustrated methods of forming an EEPROM array having L-shaped floating gate electrodes that are arranged in an alternating left/right sequence.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference characters.
A NAND-type EEPROM device according to first embodiments of the invention is illustrated by FIGS. 2A-2D. In particular, FIG. 2A, which is a plan layout view of a NAND-type EEPROM device, illustrates a plurality of bit lines 148 that extend in parallel in a first direction across a semiconductor substrate 100 having active regions 105 therein. As shown by FIG. 2B, these active regions 105 extend between adjacent trench isolation regions 106, which are located within shallow trenches 104. These bit lines 148 are connected vertically by bit line contact plugs 146 to corresponding ones of the active regions 105. These bit line contact plugs 146 are formed within contact openings 144. FIG. 2A also illustrates a plurality of word lines 132a, a string select line 132b, a ground select line 132c and a common source line 140, which extend in parallel in a second direction across the semiconductor substrate 100. These first and second directions are illustrated as the bit line direction and the word line direction, respectively.
FIG. 2B illustrates a cross-sectional view of the NAND-type EEPROM device of FIG. 2A, taken along the bit line direction. As illustrated by FIG. 2B, each bit line 148 is electrically connected to a drain region 136a of a corresponding string selection transistor (SST) within a corresponding NAND-type string of EEPROM cells. This electrical connection is provided by a bit line contact plug 146 (e.g., metal plug), which extends through a stacked arrangement of a first interlayer dielectric layer 138 and a second interlayer dielectric layer 142. The string selection transistor (SST) also includes a source/drain region 134, gate oxide layer 110b, a lower string select gate electrode 120b, an insulating region 115b and an upper string select gate electrode 128b, which is electrically connected to the lower string select gate electrode 120b. The insulating region 115b is formed on an upper surface 119b of a lower portion of the lower string select gate electrode 120b. The upper string select gate electrode 128b is part of the string select line 132b illustrated by FIG. 2A. The upper string select gate electrode 128b is covered by an electrically insulating hard mask pattern 130b. Region 122b represents an inter-gate dielectric pattern having a contact opening 126a therein and region 124b is a lower conductive pattern. Regions 122b and 124b collectively form a buffer pattern 125a.
A ground selection transistor (GST) includes a source region 136b, which is electrically connected to the common source line 140, a source/drain region 134, gate oxide layer 110c, a lower ground select gate electrode 120c, an insulating region 115c and an upper ground select gate electrode 128c, which is electrically connected to the lower ground select gate electrode 120c. The insulating region 115c is formed on an upper surface 119c of a lower portion of the lower ground select gate electrode 120c. The upper ground select gate electrode 128c is part of the ground select line 132c illustrated by FIG. 2A. The upper ground select gate electrode 128c is covered by an electrically insulating hard mask pattern 130c. Region 122c represents an inter-gate dielectric pattern having a contact opening 126b therein and region 124c is a lower conductive pattern. Regions 122c and 124c collectively form a buffer pattern 125b.
FIG. 2B also illustrates a plurality of EEPROM cells within the NAND-type string associated with the corresponding bit line 148. These EEPROM cells extend in series between the ground selection transistor GST and the string selection transistor SST. Each EEPROM cell includes a pair of source/drain regions 134, a tunnel oxide layer 11a and a floating gate electrode 120a on the tunnel oxide layer 110a. The tunnel oxide layer 110a extends opposite a corresponding channel region within the substrate 100. Each channel region extends between a corresponding pair of source/drain regions within each EEPROM cell.
As described more fully hereinbelow, the floating gate electrode 120a, which has an open-ended wraparound shape, is filled with an electrically insulating region 115a. This electrically insulating region 115a extends on an upper surface 119a of a lower portion of the floating gate electrode 120a. An inter-gate dielectric pattern 122a is formed on the floating gate electrode 120a, as illustrated. The control gate electrode 132a, which represents a portion of a corresponding word line, comprises a composite of a lower conductive pattern 124a and an upper conductive pattern 128a. The upper conductive pattern 128a is covered by an electrically insulating hard mask pattern 130a.
A cross-sectional view of the NAND-type EEPROM device of FIG. 2A is illustrated by FIG. 2C. In particular, FIG. 2C illustrates a plurality of EEPROM cells that extend side-by-side in a word line direction (eg., along line C-C′ in FIG. 2A). This word line direction is illustrated as being orthogonal to the direction of the bit lines 148, which extend on top of the second interlayer dielectric layer 142. Each of these EEPROM cells includes an open-ended wraparound-shaped floating gate electrode 120a having a bottom electrode portion 171a, a top electrode portion 173a and side electrode portions 172a. These electrode portions collectively define a floating gate electrode having the shape of a rectangular cylinder, which has a longitudinal axis extending in the bit line direction. This rectangular cylinder is filled with the insulating region 115a.
As further illustrated by FIG. 2C, the source, drain and channel regions of each EEPROM cell are separate from the source, drain and channel regions of adjacent cells by corresponding isolation regions 106, which are located within shallow trenches 104. The tunnel oxide layer 110a also extends between the upper sidewalls of the shallow trenches 104. The inter-gate dielectric pattern 122a, the lower conductive pattern 124a, the upper conductive pattern 128a and the hard mask pattern 130a are illustrated as being continuous in the word line direction.
A second cross-sectional view of the NAND-type EEPROM device of FIG. 2A is illustrated by FIG. 2D. In particular, FIG. 2D illustrates a plurality of string selection transistors (SST) that extend side-by-side in a word line direction (e.g., along line D-D′ in FIG. 2A). Each of these string selection transistors includes an open-ended wraparound-shaped lower string select gate electrode 120b, an insulating region 115b and an upper string select gate electrode 128b (which represents a string selection word line). The lower string select gate electrode 120b includes a bottom electrode portion 171b, a top electrode portion 173b and side electrode portions 172b. These electrode portions collectively define a lower string select gate electrode having the shape of a rectangular cylinder. This rectangular cylinder is filled with the insulating region 115b.
Methods of forming the NAND-type EEPROM device of FIGS. 2A-2D will now be described more fully with respect to FIGS. 3A-3I and 4A-4I. In particular, FIGS. 3A-3I are cross-sectional views of intermediate structures of an EEPROM device taken along a bit line direction and FIGS. 4A-4I are cross-sectional views of the same EEPROM device taken along a word line direction. FIG. 3I corresponds generally to the right half of FIG. 2B and FIG. 4I corresponds generally to the cross-section shown in FIG. 2C.
Referring now to FIGS. 3A and 4A, methods of forming a NAND-type EEPROM device according to embodiments of the invention include forming a hard mask pattern 102 on a primary surface of a semiconductor substrate 100. This hard mask pattern 102 may be formed by depositing a composite layer of silicon nitride and silicon oxide having a thickness in a range from about 300 Å to about 2000 Å on the semiconductor substrate 100 and then photolithographically patterning the deposited layer. Active regions 105 are then defined within the substrate 100 by selectively etching shallow trenches 104 into the substrate 100, using the hard mask pattern 102 as an etching mask. These trenches 104 are then filled with a trench isolation material (e.g., oxide). This filling of the trenches 104 may be performed by depositing an electrically insulating layer into the trenches 104 and then planarizing or otherwise etching back the deposited insulating layer to be planar with an upper surface of the hard mask pattern 102. This planarization step results in the definition of a plurality of trench isolation regions 106 within the substrate 100.
As illustrated by FIGS. 3B and 4B, the hard mask pattern 102 is then removed to expose recesses 108 within the trench isolation regions 106. Then, as shown by FIGS. 3C and 4C, a plurality of layers are formed on the substrate 100. These layers include a plurality of tunnel oxide layers 110, which may be formed by thermally oxidizing exposed portions of the active regions 105. These tunnel oxide layers 110 may have a thickness in a range from about 60 Å to about 100 Å. A first polysilicon layer 112 is then conformally deposited on the trench isolation regions 106 and the tunnel oxide layers 110, as illustrated. This first polysilicon layer 112 may be a doped or undoped layer having a thickness in a range from about 50 Å to about 200 Å. Next, a relatively thick electrically insulating layer 114 is conformally deposited on the first polysilicon layer 112. This electrically insulating layer 114 may have a thickness in a range from about 200 Å to about 1000 Å, which is sufficient to completely fill the recesses 108.
Referring now to FIGS. 3D and 4D, the electrically insulating layer 114 and the first polysilicon layer 112 are then planarized by an etch-back or chemical mechanical polishing (CMP) process. This planarization step is performed for a sufficient duration to expose upper surfaces of the trench isolation regions 106 and define a plurality of first polysilicon patterns 112a. The planarized upper surface of the electrically insulating layer 114 is also further etched-back slightly to define a plurality of insulating regions 115 within the recesses 108. As illustrated, upper surfaces of these insulating regions 115 are recessed relative to the upper surfaces of the trench isolation regions 106.
Thereafter, as illustrated by FIGS. 3E and 4E, a second polysilicon layer 117 is conformally deposited on the structures of FIGS. 3D and 4D. In particular, the second polysilicon layer 117 is deposited on the trench isolation regions 106, the insulating regions 115 and the first polysilicon patterns 112a. The second polysilicon layer 117 is then planarized to define a plurality of second polysilicon patterns 117a, which have an upper surface that is planar with an upper surface of the trench isolation regions 106. As illustrated by FIGS. 3F and 4F, each of the second polysilicon patterns 117a and a corresponding one of the first polysilicon patterns 112a collectively form a corresponding preliminary floating gate electrode pattern 120. As shown by FIG. 3F, each preliminary floating gate electrode pattern 120 extends in a bit line direction for the full length of a NAND string (i.e., across multiple EEPROM cells).
Referring now to FIGS. 3G and 4G, a selective etch-back step is performed to recess the trench isolation regions 106 and fully expose sidewalls of first polysilicon patterns 112a. Then, an inter-gate dielectric layer 122 and a lower conductive layer 124 (e.g., third polysilicon layer) are sequentially deposited onto the preliminary floating gate electrode patterns 120 and recessed trench isolation regions 106, as illustrated. The inter-gate dielectric layer 122 may be formed as an oxide-nitride-oxide (ONO) layer having a thickness in a range from about 100 Å to about 200 Å and the lower conductive layer 124 may be formed as a doped polysilicon layer having a thickness in a range from about 30 Å to about 200 Å.
A selective etching step is then performed to define a contact opening 126a (and contact opening 126b, not shown in FIG. 3G) that extends through the lower conductive layer 124 and the inter-gate dielectric layer 122 and exposes an upper surface of a corresponding preliminary floating gate electrode pattern 120. An upper conductive layer 128 (e.g., fourth polysilicon layer) and an electrically insulating hard mask layer 130 are then conformally deposited, as illustrated. The upper conductive layer 128 may be formed to have a thickness in a range from about 200 Å to about 1000 Å and the hard mask layer 130 may be formed as a silicon oxide layer having a thickness in a range from about 500 Å to about 2500 Å.
As illustrated by FIGS. 3H and 4H, a selective etching step(s) is performed to sequentially etch through the hard mask layer 130, the upper conductive layer 128, the lower conductive layer 124, the inter-gate dielectric layer 122, the preliminary floating gate electrode patterns 120 and the insulating regions 115, which fill the preliminary floating gate electrode patterns 120. These selective etching step(s) results in the definition of the hard mask patterns 130a, 130b (and 130c shown in FIG. 2B), a plurality of word lines 132a and floating gate electrodes 120a of the EEPROM cells and a string select line 132b, which connects the gate electrodes of the string select transistors (SST) within a corresponding row. The ground select line 132c (not shown in FIG. 3H, but shown in FIG. 2B) is also defined. These selective etching step(s) also defines the electrically insulating regions 115a within the floating gate electrodes 120a and the insulating region 115b associated with the string select transistor (SST). As described above with respect to FIG. 2D, each floating gate electrode 120a has a bottom electrode portion 171a, a top electrode portion 173a and side electrode portions 172a, as illustrated by FIG. 4H.
Referring now to FIGS. 2B, 3I and 4I, a selective ion-implanting/drive-in step is performed to define the source/drain regions of the EEPROM cells, string select transistors and ground select transistors. These source/drain regions are illustrated best by the reference numerals 134, 136a and 136b in FIG. 2B. After these regions have been formed, a first inter-layer dielectric layer 138 is formed on the substrate 100. This first inter-layer dielectric layer 138 may be silicon oxide layer having a thickness in a range from about 3000 Å to about 8000 Å. As illustrated by FIG. 2B, the first inter-layer dielectric layer 138 may be patterned to define a contact opening therein and a common source line 140 may be formed in the contact opening. This common source line 140 is electrically connected to the source region 136b of each of the ground select transistors (GST) within a plurality of the NAND strings. A second inter-layer dielectric layer 142 is also formed on the first inter-layer dielectric layer 138 and on the common source line 140. This second inter-layer dielectric layer 142 may be silicon oxide layer having a thickness in a range from about 5000 Å to about 2000 Å. A selective etching step is then performed to define a bit line contact opening 144 that extends through the fist and second inter-layer dielectric layers and exposes the drain region 136a of the string selection transistor (SST). This bit line contact opening 144 is then filled with a bit line contact plug 146.
Additional methods of forming EEPROM devices according to embodiments of the invention are illustrated by FIGS. 5A-5E and 6A-6E. In particular, FIGS. 5A and 6A illustrate steps to form tunnel oxide patterns 110 and a polysilicon pattern 212 on the structures illustrated by FIGS. 3B and 4B. This polysilicon pattern 212 may be formed by depositing a blanket polysilicon layer and then planarizing the layer for a sufficient duration to expose upper surfaces of the trench isolation regions 106. Referring now to FIGS. 5B and 6B, this polysilicon pattern 212 is etched back to define a plurality of relatively thin polysilicon patterns 212a on corresponding ones of the tunnel oxide patterns 110. Another polysilicon layer 214 is then conformally deposited on the tunnel oxide regions 106 and on the polysilicon patterns 212a.
As illustrated by FIGS. 5C and 6C, the polysilicon layer 214 is selectively etched back to form polysilicon sidewall spacers 214a on sidewalls of the openings 108 in the trench isolation regions 106. An electrically insulating layer is then deposited into the openings and onto the trench isolation regions and then planarized and etched-back to define a plurality of insulating regions 115 having upper surfaces that are recessed within corresponding ones of the openings 108. A polysilicon layer 216 is then conformally deposited onto the trench isolation regions 106 and onto the plurality of insulating regions 115. This polysilicon layer 216 is of sufficient thickness to completely fill the openings 108.
Referring now to FIGS. 5D and 6D, the polysilicon layer 216 is then planarized for a sufficient duration to expose the trench isolation regions 106 and thereby define a plurality of polysilicon patterns 216a. This planarization step may include a chemical mechanical polishing and/or chemical etch-back process. This planarization of the polysilicon layer 216 results in the definition of a plurality of preliminary floating gate electrode structures 120′. Each of these preliminary floating gate electrode structures 120′ includes a corresponding polysilicon pattern 216a, a pair of polysilicon sidewall spacers 214a and a polysilicon pattern 212a.
The structures of FIGS. 5D and 6D, which are similar to the structures of FIGS. 3F and 4F, undergo the further processing illustrated and described above with respect to FIGS. 3G-3H and 4G-4H. However, as illustrated by FIGS. 5E and 6E, the insulating regions 115 are removed by etching (e.g., wet etching) to thereby define a plurality of tunnel paths 121a and 121b associated with the EEPROM cells and string selection and ground selection transistors.
Thereafter, as illustrated by FIGS. 2B, 31 and 41, a selective ion-implanting/drive-in step is performed to define the source/drain regions of a plurality of the EEPROM cells, string select transistors and ground select transistors (not shown in FIG. 41). These source/drain regions are illustrated best by the reference numerals 134, 136a and 136b in FIG. 2B. After these regions have been formed, a first inter-layer dielectric layer 138 is formed on the substrate 100. This first inter-layer dielectric layer 138, which may be silicon oxide layer having a thickness in a range from about 3000 Å to about 8000 Å, is also provided to refill the tunnel paths 121a and 121b.
Then, as illustrated by FIG. 2B, the first inter-layer dielectric layer 138 may be patterned to define a contact opening therein and a common source line 140 may be formed in the contact opening. This common source line 140 is electrically connected to the source region 136b of each of the ground select transistors (GST) within a plurality of the NAND strings. A second inter-layer dielectric layer 142 is also formed on the first inter-layer dielectric layer 138 and on the common source line 140. A selective etching step is then performed to define a bit line contact opening 144 that extends through the fist and second inter-layer dielectric layers and exposes the drain region 136a of the string selection transistor (SST). This bit line contact opening 144 is then filled with a bit line contact plug 146.
A NAND-type EEPROM device according to additional embodiments of the invention is illustrated by FIGS. 7A-7E. In particular, FIG. 7A is a perspective view of a portion of a NAND-type array of EEPROM cells having L-shaped floating gate electrodes 40. These L-shaped floating gate electrodes 40 operate to reduce cell-to-cell coupling capacitance in both bit line and word line directions, yet still maintain sufficiently high control electrode-to-floating gate electrode coupling during programming operations. As illustrated by FIG. 7A, a portion of a first NAND string of EEPROM cells includes two L-shaped floating gate electrodes 40G1 and 40G3 and a portion of a second NAND string of EEPROM cells includes two L-shaped floating gate electrodes 40G2 and 40G4. These floating gate electrodes are provided on a semiconductor substrate 11 having a plurality of active regions 20 therein that are defined by spaced-apart shallow trench isolation (STI) regions 30. These active region are illustrated as having a width equal to w1. The source/drain regions (S/D) 50 and channel regions of the EEPROM cells are formed in the active regions 20. As will be understood by those skilled in the arts the channel regions represent those portions of the active regions 20 that extend underneath the floating gate electrodes 40 (and between opposing source and drain regions).
Each of the L-shaped floating gate electrodes 40 is illustrated as including a horizontal segment and a vertical segment. The horizontal segment is illustrated as having a thickness t, with width and length dimensions as w1′ and w2. The vertical segment is illustrated as having a thickness t2 with width and length dimensions as w2 and h1. The spacing between adjacent floating gate electrodes in the word line direction is illustrated as d1 and the spacing between adjacent floating gate electrodes in the bit line direction is illustrated as d2.
FIG. 7B is a perspective view of another portion of a NAND-type array of EEPROM cells having L-shaped floating gate electrodes 40 that extend on corresponding tunnel insulating regions 17. As illustrated, these L-shaped floating gate electrodes 40 are arranged in an alternating left/right sequence on a row-by-row basis. This alternating sequence supports lower gate-to-gate parasitic coupling capacitance in the bit line direction by increasing the effective distance between the vertical segments of the floating gate electrodes within a corresponding NAND string. Thus, in FIG. 7B, one row of EEPROM cells (in a word line direction) includes L-shaped floating gate electrodes having horizontal segments on right sides of corresponding vertical segments when viewed in the bit line direction and another immediately adjacent row of EEPROM cells includes L-shaped floating gate electrodes having horizontal segments on left sides of corresponding vertical segments. FIG. 7B also illustrates patterned inter-gate dielectric layers 60 and word lines 70. Each of these word lines 70 operates as the corresponding control gate electrodes of EEPROM cells within a corresponding row of the NAND-type array.
FIG. 7C is a cross-sectional view of the NAND-type array of FIG. 7B, taken along line C-C′. As illustrated by FIG. 7C, the vertical segments of the floating gate electrodes 40, which have a height h1, are located on the shallow trench isolation regions 30, and the horizontal segments of the floating gate electrodes 40 extend across the channel regions of the EEPROM cells. FIG. 7D is a cross-sectional view of the NAND-type array of FIG. 7B, taken along line D-D′. As illustrated by FIG. 7D, the floating gate electrodes 40 have vertical segments that are located on opposite sides of a NAND string (within the NAND-type array) relative to the floating gate electrodes illustrated in FIG. 7C. FIG. 7E is a cross-sectional view of the NAND-type array of FIG. 7B, taken along line E-E′. As illustrated by FIG. 7E, the horizontal segments of the floating gate electrodes 40 have a thickness of t1 and the inter-gate dielectric layers 60 are disposed on these horizontal segments. The reference numerals 50 represent the shared source/drain regions of EEPROM cells located within a corresponding NAND-type string of EEPROM cells.
FIG. 8 is a perspective view of a portion of a NAND-type array of EEPROM cells having L-shaped floating gate electrodes 40 that extend on corresponding tunnel insulating regions 17. In contrast to the L-shaped floating gate electrodes 40 of FIG. 7B, the L-shaped floating gate electrodes in FIG. 8 are not arranged in an alternating sequence on a row-by-row basis. According, the parasitic gate-to-gate coupling capacitance associated with the EEPROM cells in the NAND-type array of FIG. 8 is greater than the parasitic gate-to-gate coupling capacitance associated with the EEPROM cells in FIG. 7B, by virtue of the fact that the floating gate electrodes in the EEPROM array of FIG. 8 have a greater degree of overlap along the bit-line direction of each NAND string.
EEPROM cells according to further embodiments of the invention will now be described with respect to FIGS. 9A-9M. In FIG. 9A, the L-shaped floating gate electrode 40 within an EEPROM cell includes a horizontal segment 40h and a vertical segment 40v. Recesses are also formed in the shallow trench isolation regions 30 and these recesses are lined with the inter-gate dielectric layer 60. These recesses are sufficiently deep so that the inter-gate dielectric layer 60 extends below an interface between the active region 20 and the corresponding tunnel insulating layer 17, as illustrated. The depth of these recesses also causes the inter-gate dielectric layer 60 to cover the sidewalls of the floating gate electrode 40.
In contrast, in the cell embodiment of FIG. 9B, the tunnel insulating layer 17 is recessed below upper surfaces of adjacent trench isolation regions 30. In this case, portions of the sidewalls of the floating gate electrode 40 are covered by the trench isolation regions 30, which extend above the horizontal segment 40h. Accordingly, the inter-gate dielectric layer 60 does not fully cover the sidewalls of the floating gate electrode 40.
In the cell embodiment of FIG. 9C, the tunnel insulating layer 17 is elevated above upper surfaces of adjacent trench isolation regions 30. In this case, the sidewalls of the horizontal segment 40h and sidewalls of the tunnel insulating layer 17 are covered by the inter-gate dielectric layer 60, as illustrated. The cell embodiment of FIG. 9C is similar to the cell embodiment of FIG. 9A, however, the horizontal segment 40h is narrower in FIG. 9C relative to FIG. 9A. The cell embodiment of FIG. 9D is similar to the cell embodiment of the FIG. 9C, however, the horizontal segment 40h is illustrated as having the same lateral dimension as the active region 20. The cell embodiment of FIG. 9E is similar to the cell embodiment of FIG. 9D, however, the horizontal segment 40h is illustrated as having narrower lateral dimensions relative to the active region 20. Accordingly, the inter-gate dielectric layer 60 contacts a portion of an upper surface of the channel insulating layer 17.
The cell embodiment of FIG. 9F is similar to the cell embodiment of the FIG. 9A, however, a buffer pattern 65 is provided between the horizontal segment 40h of the floating gate electrode 40 and the inter-gate dielectric layer 60, as illustrated. This buffer pattern 65 can be formed of an oxide material, a nitride material or a material having a relative high dielectric constant (e.g., high-k material). The cell embodiment of FIG. 9G is similar to the cell embodiment of the FIG. 9B, however, the buffer pattern 65 is provided between the horizontal segment 40h of the floating gate electrode 40 and the inter-gate dielectric layer 60, as illustrated.
The cell embodiment of FIG. 9H is similar to the cell embodiment of the FIG. 7C, however, the thickness t1 of the horizontal segment 40h is less than the thickness t2 of the vertical segment 40v. The cell embodiment of FIG. 91 is similar to the cell embodiment of the FIG. 7C, however, the thickness t1 of the horizontal segment 40h is greater than the thickness t2 of the vertical segment 40v. The cell embodiment of FIG. 9J is similar to the cell embodiment of the FIG. 7C, however, the floating gate electrode 40 has two vertical segments 40v1 and 40v2. The vertical segment 40v1 has a height h1 and the vertical segment 40v2 has a height h2.
The cell embodiment of FIG. 9K is similar to the cell embodiment of FIG. 9B, however, the vertical segment of the floating gate electrode is divided into a lower vertical segment 40vl, a central segment 40c and an upper vertical segment 40vu. The cell embodiment of FIG. 9L is similar to the embodiment of FIG. 7C, however, the horizontal segment of the floating gate electrode is divided into a lower horizontal segment 40hl and an upper horizontal segment 40hu. The lower horizontal segment has a width equivalent to a width of the active region 20 and the upper horizontal segment has a width greater than the width of the active region 20. The cell embodiment of FIG. 9M is similar to the embodiment of FIG. 9L, however, the lower horizontal segment 40hl and the upper horizontal segment 40hu have widths equivalent to a width of the active region 20.
Techniques for forming EEPROM memory devices having L-shaped floating gate electrodes will now be described more fully with respect to FIGS. 10A-10J and 11A-11J. As illustrated by FIGS. 10A and 11A, a pad oxide layer 14 and a trench hard mask layer (e.g., silicon nitride layer) are formed in sequence on a primary surface of a semiconductor substrate 11 and then photolithographically patterned to define a trench hard mask pattern 18 having a plurality of stripe-shaped openings therein that expose the semiconductor substrate 11. A selective etching step is then performed to define a plurality of shallow trenches 9 in the semiconductor substrate 11, as illustrated by FIGS. 10B and 11B. During this etching step, the trench hard mask pattern 18 is used as an etching mask and a plurality of semiconductor active regions 20 are defined within the substrate 11.
Referring now to FIGS. 10C and 11C, the shallow trenches 9 are then filled with shallow trench insulating (STI) regions 30. These STI regions 30 may be formed by conformally depositing a relatively thick electrically insulating layer onto the structure of FIGS. 10B and 11B and then etching-back the deposited electrically insulating layer using a chemical-mechanical planarization (CM P) technique. The etching-back step may be performed for a sufficient duration to expose upper portions of the trench hard mask pattern 18, as illustrated.
FIGS. 10D and 11D illustrate steps to remove the trench hard mask pattern 18 and the pad oxide layer 14 to thereby define openings 22 between adjacent STI regions 30. As illustrated, the sidewalls of the STI regions 30 may become laterally recessed as a result of the removal (e.g., etching) of the pad oxide layer 14. A step to thermally oxidize upper portions of the active regions 20 is then performed to thereby define a plurality of tunnel oxide layers 17 on the active regions 20. The tunnel oxide layers 17 may also be formed using another type of deposition technique (e.g., oxide CVD). Referring now to FIGS. 10E and 11E, a polysilicon layer 40′ is conformally deposited on the STI regions 30 and the tunnel oxide layers 17. This polysilicon layer 40 includes opposing vertical segments 40v1′ and 40v2′ on sidewalls of the STI regions 30. These opposing vertical segments 40v1′ and 40v2′ define second openings 22′ between the STI regions 30.
Referring now to FIGS. 10F and 11F, buffer regions 65′ are formed within the second openings 22′. These buffer regions 65′ may be formed as oxide, nitride or aluminum oxide (e.g., Al2O3) regions, for example. These buffer regions 65′ are formed by conformally depositing an electrically insulating layer (not shown) on the polysilicon layer 40′ to thereby fill the second opening 22′ and then planarizing the electrically insulating layer for a sufficient duration to expose the polysilicon layer 40′. This planarization step may be performed as a chemical-mechanical planarization (CMP) step.
FIGS. 10G and 11G illustrate steps to deposit a gate mask layer on the structure of FIGS. 10F and 11F and then photolithographically pattern the gate mask layer to define a plurality of stripe-shaped floating gate mask patterns 55 that extend in a bit line direction. As illustrated, each of these floating gate mask patterns 55 covers a corresponding vertical portion 40v2′ of the polysilicon layer 40′. Referring now to FIGS. 10H and 11H, an etching step is performed to selectively etch back the polysilicon layer 40′ using the floating gate mask patterns 55 as an etching mask. This etching step results in the formation of a plurality of L-shaped floating gate electrodes 40″ having horizontal and vertical portions 40h′ and 40v′2. Thereafter, at least portions of the buffer regions 65′ are selectively removed using an etching step that may also result in some recession of the STI regions 30. In the event the buffer regions 65′ are completely removed, then additional etching steps (not shown) may be performed to thin the vertical or horizontal portions of the L-shaped floating gate electrodes 40″, as illustrated by FIGS. 9H-9I.
FIGS. 10I and 11I illustrate the conformal deposition of an inter-gate dielectric layer 60′ on the L-shaped floating gate electrodes 40″ and the STI regions 30. This dielectric layer 60′ may be formed as an oxide-nitride-oxide layer or as a high-k dielectric layer (e.g., aluminum oxide layer), for example. Finally, FIGS. 10J and 11J illustrate the formation of a plurality of word lines 70 that extend in a word line direction and opposite the L-shaped floating gate electrodes 40″. These word lines 70 may be formed by conformally depositing a blanket conductive layer(s) and then selectively patterning the conductive layer into a plurality of word lines 70. Source/drain regions 50 may then be formed in the active regions 20 by implanting source/drain region dopants into the active regions 20 using the word lines 70 as an implant mask.
Additional methods of forming EEPROM memory devices include forming L-shaped floating gate electrodes having an alternating left/right sequence along a bit line direction. These methods are similar to the methods illustrated by FIGS. 10A-10J and 11A-11J, however, the steps of forming the plurality of stripe-shaped floating gate mask patterns 55 is replaced by steps to form the mesh-shaped floating gate mask pattern 55′ of FIG. 12A, which has a plurality of openings therein that are staggered in a zig-zag arrangement along the bit line direction. This staggered arrangement of the openings results in the formation of L-shaped floating gate electrodes 40″ that are staggered (to face left and face right) along the bit line direction, as illustrated by FIG. 12B. The steps of FIGS. 101-10J and 11I-11J are then performed on the structure of FIG. 12B to thereby define a plurality of word lines 70.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
