Cross diffusion barrier layer in gate structure
Various embodiments include a substrate having including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate, an insulation layer overlying the substrate, a gate layer overlying the insulation layer, a barrier layer overlying the gate layer, and an electrode layer overlying the barrier layer. The first and third doped regions may be located on a first side of the gate layer. The second and fourth doped regions may be located on a second side of the gate layer. The first and third doped regions may be source and drain regions of a first transistor. The second and fourth doped regions may be source and drain regions of a second transistor. The gate layer may include a gate segment to couple to a third transistor. Other embodiments are disclosed.
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This application is a Continuation of U.S. application Ser. No. 10/228,839, filed Aug. 26, 2002, which is incorporated herein by reference.
FIELDThe present disclose relates to semiconductor devices, including gate structure with mixed conductivity types.
BACKGROUNDSome semiconductor devices have a gate structure over a substrate to control conduction between active regions within the substrate. A typical gate structure usually has a layer of polycrystalline silicon (or polysilicon) doped with some type of dopant (impurities) to form a doped polysilicon gate.
The type of the dopant defines the conductivity type of the doped polysilicon gate. An n-type polysilicon gate has a dopant that provides extra electrons. For example, arsenic is usually used as a dopant in an n-type polysilicon gate. A p-type polysilicon gate has a dopant that provides extra holes. For example, boron is commonly used as a dopant in a p-type polysilicon gate.
Some devices have two doped polysilicon gates of different conductivity types placed side by side and sharing the same gate contact that spreads across both gates. When a shared gate contact is used, a dopant from one gate may cross to the shared gate contact and diffuse to the other gate. This is cross diffusion.
The cross diffusion changes the conductivity of the two doped polysilicon gates. A small cross diffusion may cause the device to perform inefficiently. Too much cross diffusion may lead to failure of the device.
Some methods for preventing cross diffusion exist in various forms. Some of these methods, however, either increase the resistance of the doped polysilicon gates or have inadequate prevention of the cross diffusion.
BRIEF DESCRIPTION OF THE DRAWINGS
The following description and the drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice it. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like numerals describe substantially similar components throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the invention encompasses the full ambit of the claims and all available equivalents.
Device area 102 includes a well 103 encompassing doped regions 104 and 106. Device area 112 includes a well 113 encompassing doped regions 114 and 116. These doped regions can be used as sources and drains of transistors. For example, doped regions 104 and 106 can be used as a source and a drain of a p-channel transistor, and doped regions 114 and 116 can be used as a drain and a source of an n-channel transistor. Line 2-2 in
Cross diffusion barrier layer 222 includes nitrogen. In some embodiments, cross diffusion barrier layer 222 includes a combination of silicon and nitrogen, for example, silicon nitride.
Gate portion 210 includes polysilicon doped with a dopant of first conductivity type. Gate portion 212 includes polysilicon doped with a dopant of second conductivity type. The first and second conductivity types include N-type and P-type.
In embodiments represented by
Gate portion 212 includes polysilicon doped with a dopant, for example boron or boron fluoride to make it a P-type material. In other embodiments, gate portion 202 can be P-type material and gate portion 212 can be N-type material.
The N-type material has excess electrons as majority carriers for conducting current. The P-type material has excess holes as majority carriers for conducting current. Further, in the specification, the term “doped region” refers to a region having a semiconductor material doped with a dopant to become either an N-type material or a P-type material.
In some embodiments, electrode layer 204 includes tungsten. In other embodiments, electrode layer 204 includes a combination of tungsten and silicon. In some other embodiments, electrode layer 204 includes other materials.
In embodiments represented by
Gate layer 202 has a layer thickness T1. Cross diffusion barrier layer 222 has a layer thickness T2. In some embodiments, T1 is in a range of about 400 angstroms to about 600 angstroms, and T2 is about one percent of T1. In other embodiments, T2 is in a range of about 5 angstroms to about 10 angstroms. In some other embodiments, T2 equals to about the thickness of a nitrogen atom, in which cross diffusion barrier layer 222 has monolayer of single nitrogen atoms.
Well 103 includes P-type material and well 113 includes N-type material. Doped regions 104 and 106 include N-type material. Doped regions 114 and 116 include P-type material. Thus, transistor 320 is a p-channel transistor and transistor 322 is an n-channel transistor.
Transistors 320 and 322 can form an inverter by adding an interconnection connecting doped regions 106 and 116 (
Transistors 530 and 532 have a shared gate 580 connected to node 510. Transistors 540 and 542 have a shared gate 590 connected to node 512. Each of the shared gates 580 and 590 has similar construction as that of shared gate 120 of
Memory cell 500 is a static memory cell. Inverters 520 and 522 form a latch to hold data. Memory cell 500 holds the data in complementary forms at storage nodes 510 and 512. For example, when node 510 holds a voltage corresponding to a logic one of the data, node 512 holds a voltage corresponding to a logic zero of the data. In the opposite, when node 510 holds a logic zero, node 512 holds a logic one. Thus, nodes 510 and 512 hold two stable logic states of a data. Either one of the nodes 510 and 512 can be designated to hold the true logic state of the data.
Access transistors 550 and 552 access nodes 510 and 512 during a read operation and a write operation. The read operation reads data from memory cell 500. During a read operation, a voltage is applied to word line 556 to turn on transistors 550 and 552 to connect the voltages on nodes 510 and 512 to bit lines 554 and 558. The difference between the voltages on bit lines 554 and 558 is measured to obtain the true logic state representing the data stored in memory cell 500. During a write operation, complementary voltages representing input logic one and logic zero of a data are applied to bit lines 554 and 558. A voltage is applied to word line 556 to turn on transistors 550 and 552 to connect the voltages on bit lines 554 and 558 to nodes 510 and 512. Inverters 520 and 522 hold the voltages representing the input logic one and logic zero of the data at nodes 510 and 512 as long as power is supplied to memory cell 500.
Device 100, inverter 400, and memory cell 500 can be formed by a method described below.
In
In
In
In
In some embodiments, cross diffusion barrier layer 1402 is formed by a remote plasma nitridization (RPN) process. In this RPN process, nitrogen plasma is created on the surface of gate layer 1201. Silicon on the top surface of gate layer 1201 reacts with the nitrogen and forms cross diffusion barrier layer 1402 layer having a combination of silicon and nitrogen. In this process, cross diffusion barrier layer 402 is formed immediately below the top surface of gate layer 1201.
In some embodiments, cross diffusion barrier layer 1402 includes silicon nitride (Si3N4). In other embodiments, cross diffusion barrier layer 1402 has about 80 percent of silicon and about 20 percent of nitrogen. In some other embodiments, the concentration of nitrogen in cross diffusion barrier layer 1402 is in a range of about 10 percent to about 40 percent of nitrogen.
In some embodiments, the introduction of nitrogen into gate layer 1201 is performed with a nitrogen plasma at a pressure of about 10 milliTorr, an RF (radio frequency) power in a range of about 500 watts to about 1500 watts, a nitrogen gas flow of about 250 scc, a temperature range of about 350 to about 400 degrees Celsius, and a duration in a range of about 20 seconds to about 100 seconds.
In other embodiments, the introduction of nitrogen into gate layer 1201 is performed with a nitrogen plasma at a pressure of about 7 milliTorr, an RF power of about 900 watts, a nitrogen gas flow of about 250 scc, a temperature range of about 100 to 200 degrees Celsius, and a duration of about 40 seconds.
Since cross diffusion barrier layer 1402 having nitrogen is formed by adding nitrogen into gate layer 1201, the doped polysilicon in gate layer 1201 suffers insignificant depletion (or loss) of dopant, thereby preserving the original material structure of gate layer 1201. In addition, by adding nitrogen to gate layer 1201 to form cross diffusion barrier layer 1402, the thickness of layer 1402 can be accurately obtained by controlling the amount of nitrogen before it is introduced into gate layer 1201. Moreover, since nitrogen is introduced into gate layer 1201 from an external source, the concentration of nitrogen in cross diffusion barrier layer 1402 can be controlled. Further, cross diffusion barrier layer 1402 created by the combination of silicon and nitrogen causes insignificant or no insulation effect, thereby reducing or eliminating parasitic capacitance when cross diffusion barrier layer 1402 is sandwiched between gate layer 1201 and another conductive layer.
In
Cross diffusion barrier layer 1402 has a low resistance. Therefore, when additional contact or conductive layer, such as electrode layer 1602, is to formed, layer 1402 contributes substantial insignificant resistance to the total resistance of the gate structure 1620.
Memory array 2801 corresponds to memory array 2200 (
Memory device 2904 can be memory device 2800 of
System 2900 represented by
Various embodiments of the invention describe structures and methods for providing an adequate prevention of cross diffusion in polysilicon gates without substantially increasing the resistance of the polysilicon gates.
Some embodiments include a device having a substrate with doped regions and a gate layer opposing the doped regions and separated from the substrate by a gate insulation layer. The gate layer includes a first gate portion of first conductivity type and a second gate portion of second conductivity type adjacent to the first gate portion. The device also includes a cross diffusion barrier layer sandwiched between the gate layer and an electrode layer. The cross diffusion barrier layer includes nitrogen. Some embodiments include a method that includes forming a gate insulation layer on a substrate. A polysilicon layer is formed on the gate insulation layer. The polysilicon layer is doped with a dopant of first conductivity type in a first portion and a dopant of second conductivity type in a second portion adjacent to the first portion. The method also includes performing a nitridization process to form a cross diffusion barrier layer on the polysilicon layer. Further, an electrode layer is formed on the diffusion barrier layer.
Although specific embodiments are described herein, those skilled in the art recognize that other embodiments may be substituted for the specific embodiments shown to achieve the same purpose. This application covers any adaptations or variations of the embodiments of the present invention. Therefore, the embodiments of the present invention are limited only by the claims and all available equivalents.
Claims
1. A device comprising:
- a substrate including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate;
- an insulation layer overlying the substrate;
- a gate layer overlying the insulation layer, wherein the first and third doped regions are located on a first side of the gate layer, wherein the second and fourth doped regions are located on a second side of the gate layer, wherein the first and third doped regions are source and drain regions of a first transistor, wherein the second and fourth doped regions are source and drain regions of a second transistor, and wherein the gate layer includes a gate segment to couple to a third transistor;
- a barrier layer overlying the gate layer; and
- an electrode layer overlying the barrier layer.
2. The device of claim 1, wherein the barrier layer includes nitrogen.
3. The device of claim 2, wherein the barrier layer includes silicon combined with the nitrogen.
4. The device of claim 1, wherein the barrier layer has a thickness in a range of about 5 angstroms to about 10 angstroms.
5. The device of claim 1, wherein the barrier layer includes about 10 percent to about 40 percent nitrogen.
6. The device of claim 1, wherein the at least one of the first, second, third, and fourth doped regions are doped with a dopant, and wherein the dopant is one of arsenic, phosphorous, and boron.
7. The device of claim 1, wherein the gate layer includes a first gate portion, and a second gate portion coupled to the first gate portion, wherein the first gate portion having a first conductivity type, and wherein the second gate portion having a second conductivity.
8. The device of claim 1, wherein the electrode layer includes one of tungsten silicide, titanium silicide, and tungsten nitride.
9. A device comprising:
- a first transistor coupled to a substrate, the first transistor including a first source and a first drain; and
- a second transistor coupled to the first transistor, the second transistor including a second source and a second drain, the first and second transistors sharing a gate structure, the gate structure including:
- a polysilicon layer, wherein the first source and the second drain are located on a first side of the polysilicon layer, wherein the first drain and the second source are located on a second side of the polysilicon layer, and wherein the polysilicon layer including a segment to couple to one of a source and a drain of a third transistor;
- an electrode layer overlying the polysilicon layer; and
- a barrier layer sandwiched between the electrode layer and the polysilicon layer.
10. The device of claim 9, wherein the first transistor includes a p-channel transistor.
11. The device of claim 10, wherein the second transistor includes an n-channel transistor.
12. The device of claim 9, wherein the barrier layer includes a combination of silicon and nitrogen.
13. The device of claim 12, wherein the electrode layer includes tungsten silicide.
14. The device of claim 9, wherein the barrier layer has a thickness of about one percent of a thickness of the gate layer.
15. A device comprising:
- a first inverter; and
- a second inverter coupled to the first inverter via a first storage node and at a second storage node, each of the first and second inverters including a first transistor, and a second transistor coupled to the first transistor, and a gate structure shared by the first and second transistors, the gate structure including:
- a gate layer, wherein a source of the first transistor and a drain of the second transistor are located on a first side of the gate layer, and wherein a drain of the first transistor and a source of the second transistor are located on a second side of the gate layer;
- an electrode layer; and
- a barrier layer sandwiched between the electrode layer and the polysilicon layer, wherein the gate layer of the gate structure of the first inverter includes a segment to couple to a third transistor, and wherein the gate layer of the gate structure of the second inverter includes a segment to couple to a fourth transistor.
16. The device of claim 15, wherein the first inverter includes an input coupled to the first storage node and an output coupled to the second storage node, and wherein the second inverter includes an input coupled to the second storage node and an output coupled to the first storage node.
17. The device of claim 16, wherein the third transistor includes a source coupled to the first storage node, a drain coupled to a first bit line, and a gate coupled to a word line, and wherein the fourth transistor includes a source coupled to the second storage node, a drain coupled to a second bit line, and a gate coupled to the word line.
18. The device of claim 15, wherein the barrier layer includes a combination of silicon and nitrogen.
19. The device of claim 15, wherein the barrier layer has a thickness of about a thickness of a nitrogen atom.
20. The device of claim 18, wherein the electrode layer includes tungsten nitride.
21. A system comprising:
- a processor; and
- a static random access memory device coupled to the processor, the static random access memory device including:
- a substrate including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate;
- an insulation layer overlying the substrate;
- a gate layer overlying the insulation layer, wherein the first and third doped regions are located on a first side of the gate layer, wherein the second and fourth doped regions are located on a second side of the gate layer, wherein the first and third doped regions are source and drain regions of a first transistor, wherein the second and fourth doped regions are source and drain regions of a second transistor, and wherein the gate layer includes a gate segment to couple to a third transistor;
- a barrier layer overlying the gate layer; and
- an electrode layer overlying the barrier layer.
22. The system of claim 21, wherein the barrier layer includes nitrogen.
23. The system of claim 22, wherein the barrier layer includes silicon combined with the nitrogen.
24. The system of claim 23, wherein the electrode layer titanium silicide.
25. The system of claim 24, wherein the barrier layer includes about 80 percent of silicon and about 20 percent of nitrogen.
Type: Application
Filed: Dec 28, 2006
Publication Date: May 10, 2007
Applicant:
Inventors: Sanh Tang (Boise, ID), Chih-Chen Cho (Boise, ID), Robert Burke (Boise, ID), Anuradha Iyengar (Stafford, TX), Eugene Gifford (Kuna, ID)
Application Number: 11/646,896
International Classification: H01L 29/788 (20060101); H01L 29/76 (20060101);