Power-on reset circuit for an integrated circuit
A power-on reset circuit for an integrated circuit has a trigger unit that includes (i) a first voltage drop element with a first terminal for coupling to a supply voltage, and a second terminal; (ii) a second voltage drop element with a first terminal, coupled to the second terminal of the first voltage drop element, and a second terminal; and (iii) an inverter with an input, coupled to the first terminal of the second voltage drop element, and an output. A discharge unit is provided to conduct a current from the trigger unit during a decrease of the supply voltage to decrease the voltage at the input of the first inverter, and substantially block current from the trigger unit during an increase of the supply voltage.
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This invention relates generally to providing a power-on reset signal for an integrated circuit.
BACKGROUNDWhen a power condition of an integrated circuit (IC) changes from a low to a high voltage level, one or more semiconductor devices in the IC can enter undesirable logic states. For example, devices in the IC can be left in uncertain logic states after the power of the IC is switched on or after some disturbance is applied to the power of the IC.
A power-on reset circuit is implemented to reset the logic states of the IC to desired values by providing a reset signal.
During a high-speed, short-duration glitch 200 of electrical power to the IC from an external impulse, such as a power failure or electromagnetic interference, the power-on reset circuit 100 cannot generate a desirable reset signal 190 fast enough to respond to the power glitch 200. For example, during the power glitch 200, along a negative slope 210 of the supply voltage 150 that is supplied to the IC, the trigger voltage 180 across the capacitor 120 lags behind the supply voltage 150, causing a missing reaction at the reset signal 190.
During a subsequent recovery of power, shown as a positive slope 220 of the supply voltage 150 in
Thus, it is desirable to provide a power-on reset circuit capable of effectively resetting an integrated circuit in response to a power condition. It is further desirable to provide a power-on reset circuit capable of reliably delivering the reset signal at a predetermined time.
SUMMARYConsistent with embodiments of the invention, there is provided a power-on reset circuit for an integrated circuit that comprises a trigger unit. A first voltage drop element of the trigger unit includes a first terminal and a second terminal, the first terminal for coupling to a supply voltage. A second voltage drop element of the trigger unit includes a first terminal and a second terminal, the first terminal of the second voltage drop element being coupled to the second terminal of the first voltage drop element. The trigger unit also includes a first inverter having an input terminal and an output terminal, the input terminal being coupled to the first terminal of the second voltage drop element. A second inverter of the trigger unit includes an input terminal and an output terminal, the input terminal of the second inverter being coupled to the output terminal of the first inverter. A switch of the trigger unit includes a first terminal, a second terminal, and a third terminal. The first terminal of the switch is coupled to the output terminal of the first inverter, the second terminal of the switch is coupled to the second terminal of the second voltage drop element, and the third terminal of the switch is for coupling to an electrical ground. The power-on reset circuit further comprises a discharge unit to conduct a current from the trigger unit during a decrease of the supply voltage to decrease a voltage at the input terminal of the first inverter, and substantially block current from the trigger unit during an increase of the supply voltage.
Also consistent with embodiments of the invention, there is provided a power-on reset circuit for an integrated circuit that comprises a trigger unit. A first voltage drop element of the trigger unit includes a first terminal and a second terminal, the first terminal for coupling to a supply voltage. A second voltage drop element of the trigger unit includes a first terminal and a second terminal, the first terminal of the second voltage drop element being coupled to the second terminal of the first voltage drop element. The trigger unit also includes an inverter including an input terminal and an output terminal, the input terminal of the inverter being coupled to the first terminal of the second voltage drop element. The power-on reset circuit further comprises a discharge unit. The discharge unit includes a voltage coupling element that includes a first terminal and a second terminal, the first terminal for coupling to the supply voltage. A third voltage drop element of the discharge unit includes a first terminal and a second terminal, the first terminal of the third voltage drop element being coupled to the second terminal of the voltage coupling element, and the second terminal of the third voltage drop element for coupling to the electrical ground. The discharge unit additionally includes a switch having a first terminal and a second terminal, the first terminal of the switch being coupled to the second terminal of the voltage coupling element, and the second terminal of the switch being coupled to the input terminal of the inverter.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain advantages and principles of the invention.
In the drawings,
Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
An integrated circuit (IC) comprises electrical circuitry, including a plurality of electronic components and electrical interconnections between the electronic components. The electronic components typically comprise active and passive electronic components, which include digital circuits. For example, the IC may comprise capacitors, resistors, field effect transistors (FETs), flip-flops, clock circuits, and/or memory devices. The IC may use “very large scale integration” (VLSI) or “ultra large scale integration” (ULSI), these terms designating degrees of spatial density of components in a single IC. Typically, the IC has the form of a monolithic semiconductor “chip.”
A power-on reset circuit 300 is provided to generate a reset signal at a node 320 for an IC 305, as illustrated in the schematic block diagram of an exemplary embodiment in
The power-on reset circuit 300 is adapted to receive a supply voltage Vsupply at a node 310 from a power supply 315 coupled to the IC 305 and generate a reset signal at a node 320 in relation to a preselected power condition in the supply voltage Vsupply. The power-on reset circuit 300 transmits the reset signal, carried as an output voltage Vout at the node 320 of the power-on reset circuit 300, to control a supply of electrical power to the IC 305. For example, the reset signal may be received by the IC 305 at an enable terminal (not shown) that, based on the reset signal, regulates whether or not the IC 305 is coupled to the power supply 315.
Upon detection of the preselected power condition, the power-on reset circuit 300 outputs the reset signal, which goes from a “low” value to a “high” value, or alternatively from high to low, at node 320 to reset the digital circuits of the IC 305. This reset process sets the logical states of the IC 305 to known default values, when the power supply to the IC 305 is initially turned on or after a disruption in the power supply. The power supply disruption can include, for example, a black out, brown out, power spike, or other perturbance in the level of the supply voltage Vsupply provided by the power supply.
The power-on reset circuit 300 comprises a trigger unit 330, which includes a first voltage drop element 340 and a second voltage drop element 350, to bias a trigger voltage Vx at a node 360. The first voltage drop element 340 includes a first terminal 344 and a second terminal 346, the first terminal 344 being adapted to be coupled to the power supply to receive the supply voltage Vsupply at node 310. The second voltage drop element 350 includes a first terminal 354 and a second terminal 356. The first terminal 354 of the second voltage drop element 350 is coupled to the second terminal 346 of the first voltage drop element 340. Each of the first and second voltage drop elements 340, 350 is an electronic component adapted to produce a voltage drop between its first terminal 344, 354 and second terminal 346, 356. For example, the first or second voltage drop element 340, 350 may comprise a metal-oxide-semiconductor field effect transistor (MOSFET), capacitor, resistor, diode, junction field effect transistor (JFET), or bipolar junction transistor (BJT).
The trigger unit 330 further comprises a first inverter 370 having an input terminal 374 and an output terminal 376. The input terminal 374 of the first inverter 370 is coupled to the first terminal 354 of the second voltage drop element 350. The first inverter 370 may comprise, for example, a Schmitt trigger that outputs a voltage with a hysteresis relationship to its input voltage. The Schmitt trigger switches the output voltage from low to high when its input voltage reaches a first threshold value. However, the output voltage is switched back from high to low when the input voltage of the Schmitt trigger reaches a second threshold value that is lower than the first threshold value. Alternatively, the first inverter 370 may comprise a “standard inverter” that outputs a voltage without any substantial hysteresis relationship to its input voltage, such that the output voltage can be mapped one-to-one to the input voltage. The output voltage of the standard inverter is switched when the input voltage crosses substantially the same threshold voltage from either direction.
The trigger unit 330 also comprises a second inverter 380 including an input terminal 384 and an output terminal 386. The input terminal 384 of the second inverter 380 is coupled to the output terminal 376 of the first inverter 370. The second inverter 380 is adapted to receive the output voltage from the first inverter 370 and transmit the reset signal 320 as the output voltage Vout at node 320. The second inverter 380 is an optional element, which may be included depending on a magnitude of the output voltage from the first inverter 370.
The trigger unit 330 may further comprise a first switch 390 to substantially prevent leakage current through the trigger unit 330 in a power-on quiescent stage. The first switch 390 is adapted to disconnect the second voltage drop element 350 from ground when the supply voltage Vsupply at node 310 is greater than or equal to a high threshold voltage Vth. When the supply voltage Vsupply at node 310 is less than or equal to a low threshold voltage Vtl, the first switch 390 electrically grounds the second terminal 356 of the second voltage drop element 350. If there is substantially no current leakage through the first and second voltage drop elements 340, 350 due to electrical characteristics of other electronic components in the power-on reset circuit 300, such as if the second voltage drop element 350 does not permit any substantial leakage of direct current (DC) from node 360 to ground, then it may not be necessary to include the first switch 390 in the power-on reset circuit 300.
The power-on reset circuit 300 further comprises a rapid discharge unit 400 adapted to selectively conduct current from the trigger unit 330 in relation to a rate of change of the supply voltage Vsupply at node 310. During a preselected condition of the supply voltage Vsupply, the rapid discharge unit 400 selectively conducts current from the trigger unit 330 to decrease the trigger voltage Vx at node 360. For example, the rapid discharge unit 400 may be adapted to drain current from the trigger unit 330 during a decrease of the supply voltage Vsupply to more rapidly decrease the trigger voltage Vx. During an increase of the supply voltage Vsupply, the rapid discharge unit 400 may be adapted to substantially block current from the trigger unit 330 to prevent interference with the trigger voltage Vx.
In one version, the rapid discharge unit 400 comprises a voltage coupling element 410 and a third voltage drop element 420. The voltage coupling element 410 comprises a first terminal 414 and a second terminal 416. The first terminal 414 of the voltage coupling element 410 is adapted to be coupled to the supply voltage Vsupply of the power supply 315. The third voltage drop element 420 comprises a first terminal 424 and a second terminal 426, the first terminal 424 being coupled to the second terminal 416 of the voltage coupling element 410.
The rapid discharge unit 400 further comprises a second switch 430 adapted to decrease the trigger voltage Vx at node 360 by conducting current from the input terminal 374 of the first inverter 370 when the second switch 430 is in a turned-on state. The second switch 430 comprises a first terminal 434 and a second terminal 436. The first terminal 434 of the second switch 430 is coupled to the second terminal 416 of the voltage coupling element 410, while the second terminal 436 of the second switch 430 is coupled to the input terminal 374 of the first inverter 370.
In operation, the rapid discharge unit 400 of
If the supply voltage Vsupply at node 310 decreases after the power-on quiescent stage, the second capacitor 470 couples a negative voltage from the power supply onto the source voltage Vy at node 500 that is at the source of the NMOS FET 480. The NMOS FET 480 is turned on because the gate-to-source voltage across the NMOS FET 480 exceeds the turn-on threshold voltage of the NMOS FET 480. Thus, the NMOS FET 480 discharges the first capacitor 460 through the second resistor 450 to ground to rapidly decrease the trigger voltage Vx at node 360. A faster decrease of the supply voltage Vsupply at node 310 will couple a more negative voltage to the source voltage Vy at node 500 to result in a faster decrease of the trigger voltage Vx at node 360. When the trigger voltage Vx decreases sufficiently that the trigger voltage Vx is less than a threshold turn-off voltage of the Schmitt trigger 490, the output voltage Vout is pulled down to electrical ground.
The power-on reset circuit 300 of
Vth=2VSGP+Vtn (1)
In operation, the rapid discharge unit 400 substantially blocks current from the trigger unit 330 during the ramp-up stage 590. The second NMOS FET 550 of the rapid discharge unit 400 is turned off to substantially block the current from the input of the Schmitt trigger 570 in the trigger unit 330 through the rapid discharge unit 400 to ground, which allows the trigger voltage Vx 572 in the trigger unit 330 to ramp up quickly. While the supply voltage Vsupply 576 is lower than a threshold voltage of the diode-connected PMOS FET 510, the trigger voltage Vx 572 remains at electrical ground while the output of the Schmitt trigger 570 is pulled up to a high voltage level. However, when the supply voltage Vsupply 576 exceeds the threshold voltage of the diode-connected PMOS FET 510, the trigger voltage Vx 572 rises in proportion to the supply voltage Vsupply 576. When the supply voltage Vsupply 576 finally reaches a high threshold voltage Vth 630 of the power-on reset circuit 300, the output of the Schmitt trigger 570 changes from the high voltage level to a low voltage level. This turns off the first NMOS FET 540, causing the trigger voltage Vx 572 to jump to nearly the level of the supply voltage Vsupply 576, as shown in
In the power-on quiescent stage 600, the power-on reset circuit 300 is adapted to tolerate fluctuations of the supply voltage Vsupply 576 that are within a voltage window between a high threshold voltage Vth 630 and a low threshold voltage Vtl 640. These fluctuations of the supply voltage Vsupply 576 may be due, for example, to noise or electromagnetic interference. Typically, the voltage window is selected to fall within a known voltage tolerance of the electrical circuitry of the IC 305. For example, the specifications of the first PMOS FET 510, the resistor 520, and the Schmitt trigger 570, as shown in
During the power-on quiescent stage 600, the IC 305 may experience a power disruption 610 in which the supply voltage Vsupply 576 momentarily drops from a higher level to a lower level. During the initial voltage decrease within the power disruption 610, the second NMOS FET 550 turns on to rapidly decrease the trigger voltage Vx 572. For example, the power-on reset circuit 300 may be adapted to decrease the trigger voltage Vx 572 faster than the rate of decrease of the supply voltage Vsupply 576.
Returning to
Furthermore, the power-on reset circuit 300 of
As the supply voltage Vsupply at node 310 begins to recover from the power disruption 610, the rapid discharge unit 400 substantially blocks current from the trigger unit 330. The trigger unit 330 can then increase the trigger voltage Vx at node 360 substantially absent interference from the rapid discharge unit 400 so that the recovery of the output voltage Vout at node 320 is more reliable.
Another exemplary embodiment of the power-on reset circuit 300 is illustrated in the schematic diagram of
Yet another exemplary embodiment is illustrated in the schematic diagram of
Vth=2VD+Vtn (2)
In yet another exemplary embodiment of the power-on reset circuit 300, illustrated in the schematic diagram of
Yet another exemplary embodiment of the power-on reset circuit 300 is illustrated in the schematic diagram of
Although the present invention has been described in detail with regard to exemplary embodiments thereof, other variations are possible. For example, the first voltage drop element 340, the second voltage drop element 350, the third voltage drop element 420, the voltage coupling element 410, the first switch 390, and/or the second switch 430 of
Claims
1. A power-on reset circuit for an integrated circuit, the power-on reset circuit comprising:
- a trigger unit including a first voltage drop element including a first terminal and a second terminal, the first terminal for coupling to a supply voltage, a second voltage drop element including a first terminal and a second terminal, the first terminal of the second voltage drop element being coupled to the second terminal of the first voltage drop element, a first inverter including an input terminal and an output terminal, the input terminal of the first inverter being coupled to the first terminal of the second voltage drop element, a second inverter including an input terminal and an output terminal, the input terminal of the second inverter being coupled to the output of the first inverter, and a switch including a first terminal, a second terminal, and a third terminal, the first terminal of the switch coupled to the output terminal of the first inverter, the second terminal of the switch coupled to the second terminal of the second voltage drop element, and the third terminal of the switch for coupling to an electrical ground; and
- a discharge unit to conduct a current from the trigger unit during a decrease of the supply voltage to decrease a voltage at the input of the first inverter, and substantially block current from the trigger unit during an increase of the supply voltage.
2. A power-on reset circuit according to claim 1, wherein the switch is a first switch, the discharge unit comprising:
- a voltage coupling element including a first terminal and a second terminal, the first terminal for coupling to the supply voltage;
- a third voltage drop element including a first terminal and a second terminal, the first terminal of the third voltage drop element coupled to the second terminal of the voltage coupling element, and the second terminal of the third voltage drop element for coupling to the electrical ground; and
- a second switch including a first terminal and a second terminal, the first terminal of the switch coupled to the second terminal of the voltage coupling element, and the second terminal of the switch coupled to the input terminal of the first inverter.
3. A power-on reset circuit according to claim 2, wherein the third voltage drop element comprises a diode-connected NMOS FET.
4. A power-on reset circuit according to claim 2, wherein the voltage coupling element comprises a capacitor.
5. A power-on reset circuit according to claim 2, wherein the voltage coupling element comprises a PMOS capacitor.
6. A power-on reset circuit according to claim 2, wherein the first and third voltage drop elements comprise first and second diodes, respectively.
7. A power-on reset circuit according to claim 1, wherein at least one of the first and second switches comprises a native NMOS FET.
8. A power-on reset circuit according to claim 1, wherein the first inverter comprises a Schmitt trigger.
9. A power-on reset circuit according to claim 1, wherein the first inverter comprises a standard inverter.
10. A power-on reset circuit according to claim 1, wherein the first voltage drop element comprises a PMOS FET having a grounded gate.
11. A power-on reset circuit according to claim 1, wherein the first voltage drop element comprises a diode-connected PMOS FET.
12. A power-on reset circuit according to claim 1, wherein the second voltage drop element comprises a capacitor.
13. A power-on reset circuit according to claim 1, wherein the second voltage drop element comprises a resistor.
14. A power-on reset circuit for an integrated circuit, the power-on reset circuit comprising:
- a trigger unit including a first voltage drop element including a first terminal and a second terminal, the first terminal for coupling to a supply voltage, a second voltage drop element including a first terminal and a second terminal, the first terminal of the second voltage drop element being coupled to the second terminal of the first voltage drop element, and an inverter including an input terminal and an output terminal, the input terminal of the inverter being coupled to the first terminal of the second voltage drop element; and
- a discharge unit including a voltage coupling element including a first terminal and a second terminal, the first terminal for coupling to the supply voltage, a third voltage drop element including a first terminal and a second terminal, the first terminal of the third voltage drop element being coupled to the second terminal of the voltage coupling element, and the second terminal of the third voltage drop element for coupling to an electrical ground, and a switch including a first terminal and a second terminal, the first terminal of the switch being coupled to the second terminal of the voltage coupling element, and the second terminal of the switch being coupled to the input terminal of the inverter.
15. A power-on reset circuit according to claim 14, wherein the third voltage drop element comprises a diode-connected NMOS FET.
16. A power-on reset circuit according to claim 14, wherein the voltage coupling element comprises a capacitor.
17. A power-on reset circuit according to claim 14, wherein the voltage coupling element comprises a PMOS capacitor.
18. A power-on reset circuit according to claim 14, wherein the first and third voltage drop elements comprise first and second diodes, respectively.
19. A power-on reset circuit according to claim 14, wherein the switch comprises a native NMOS FET.
20. A power-on reset circuit according to claim 14, wherein the first inverter comprises a Schmitt trigger.
Type: Application
Filed: Nov 7, 2005
Publication Date: May 10, 2007
Applicant:
Inventor: Kuo-Chun Hsu (Miaoli)
Application Number: 11/267,142
International Classification: H03L 7/00 (20060101);