A content addressable memory including capacitor memory cell

Abstract

A content addressable memory is realized, wherein capacitor stores data and diode controls to store data “1” or “0”, which diode has four terminals, first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line. The plate of capacitor couples to second terminal, but it does not couple to first, third and fourth terminal. With no coupling, the plate can swing ground to high level, which can realize to remove internal negative voltage for memory operation and by turning off word line during standby no holding current is required to sustain data. In this manner, active current is dramatically reduced and standby current is only leakage current. The match line has compare circuits which include series MOS transistors for each memory cell, wherein the storage node is connected to the gate of first MOS transistor, and the comparand data is connected to the gate of second MOS transistor. Hidden refresh is asserted during precharge of match operation. The size of CAM is smaller than that of SRAM, DRAM-based CAM, and the height of cell is almost same as that of control circuit.

Description

FIELD OF INVENTION

The invention relates to content addressable memory (CAM), and more particularly to CAM including capacitor memory cell which stores data in a capacitor.

BACKGROUND

A content addressable memory (CAM) device is a storage device that is particularly suitable for matching functions because it can be instructed to compare a specific pattern of comparand data with data stored in an associative CAM array. A CAM can include a number of data storage locations, each of which can be accessed by a corresponding address. Functionality of a CAM depends at least in part on whether the CAM includes binary or ternary CAM cells.

Typical binary CAM cells are able to store to states of information, a logic one state and a logic zero state. Binary CAM cells typically include a memory cell and a compare circuit. The compare circuit compares the comparand data with data stored in the memory cell and provides the match result to a match line. Columns of binary CAM cells may be globally masked by mask data stored in one or more global mask registers.

Ternary CAM cells are mask-per-bit CAM cells that effectively store three states of information, namely a logic one state, a logic zero state, and a don't care state for compare operations. Ternary CAM cells typically include a second memory cell that stores local mask data for the each ternary CAM cell. The local mask data masks the comparison result of the comparand data with the data stored in the first memory cell such that, when the mask bit has a first predetermined value (a logic low, for example) its compare operation will be masked so that the comparison result does not affect the match line. The ternary CAM cell offers more flexibility to the user to determine on an entry-per-entry basis which bits in a word will be masked during a compare operation.

In FIG. 1, a prior art of SRAM-based CAM cell is depicted. It is one of the conventional CAM devices which use a static random access memory (SRAM) device. CAM cell 110 and 110′ include two SRAM cells 120 and 120′. CAM cell offers ternary data storage. Preferably, these two SRAM cells 120 and 120′ together can store up to four different states. Three of these four states (“0”, “1”, and “X”) are used in CAM cell, making CAM cell into a ternary state CAM cell. Each of SRAM cells 120 and 120′ includes two inverter latches, 111 and 112, 111′ and 112′ to store data. The stored data in two cells are inverted when those are written through the access transistor 113, 114, 113′ and 114′ from the memory control circuit, such that the bit line 115 and the inverting bit line 116 are a pair to store one data into latch 111 and 112, the bit line 115′ and the inverting bit line 116′ are a pair to store another data into latch 111′ and 112′, the bit line 115 and 115′ are inverted from the control circuit. As a result, the output of inverter 111 and the output of inverter 111′ are inverted to achieve compare operation when comparand data are asserted.

Compare circuit 123 and 123′ compare the data stored in the memory cell 120 and 120′ with comparand data provided on compare signal lines 117 and 117′. Compare circuit 123 includes transistors 118 and 119 to discharge the match line 122 when both transistors are turned on. Compare circuit 123′ includes transistors 118′ and 119′ to discharge the match line 122 when both transistors are turned on. Transistors 118 and 119 are coupled in series to form a first path of the compare circuit 123, and transistors 118′ and 119′ are coupled in series to form a second path of the compare circuit 123′. The sources (drains) of transistors 118 and 118′ are coupled to the match line, while the drains (sources) of transistors 119 and 119′ are coupled to ground potential. These n-channel series devices perform the comparison function.

Regarding control inputs to each of the transistors 118, 119, 118′ and 119′, the gates of transistors 118 and 118′ are coupled to receive data from the first cell 120 and second cell 120′, respectively. The gate of transistor 119 receives comparand data from compare signal line 117 and the gate of transistor 119′ receives comparand data from compare signal line 117′. The sources (drains) of transistors 118 and 118′ are coupled to the match line. Compare circuit 123 and 123′ pull the pre-charged match line to a logic zero state when the comparand data does not match (i.e., mismatches) the data stored in the memory cell 110 and 110′. To mask compare operation, comparand 117 and 117′ have logic value “low” for both lines, which makes match line to keep pre-charged voltage. This makes match (i.e., matches). SRAM-based CAM has very good performance for storing data and comparing match line, but 6 transistor-based SRAM has relatively large die area and high subthreshold leakage current for whole chip even though single memory cell has very little leakage.

In FIG. 2, a prior art of DRAM based CAM is illustrated, U.S. Pat. No. 6,331,961, wherein CAM cell 230 and 230′ include two DRAM cells 240 and 240′. CAM cell offers ternary data storage. Preferably, these two DRAM cells 240 and 240′ together can store up to four different states. Three of these four states (“0”, “1”, and “X”) are used in CAM cell, making CAM cell into a ternary state CAM cell. Each of SRAM cells 240 and 240′ includes storage capacitor to store data. The stored data in two cells are inverted when those are written through the access transistor 232, 233, 232′ and 233′ from the memory control circuit, such that the bit line 234 drives to store one data into the storage capacitor 231, the bit line 234′ drives to store another data into the storage capacitor 231′, the bit line 234 and 234′ are inverted from the control circuit. As a result, the stored data of capacitor 231 and 231′ are inverted to achieve compare operation.

Compare circuit 241 and 241′ compare the data stored in the memory cell 230 and 230′ with comparand data provided on compare signal lines 236 and 236′. Compare circuit 241 includes transistors 237 and 238 to discharge the match line 242 when both transistors are turned on. Compare circuit 241′ includes transistors 237′ and 238′ to discharge the match line 242 when both transistors are turned on. Transistors 237 and 238 are coupled in series to form a first path of the compare circuit 241, and transistors 237′ and 238′ are coupled in series to form a second path of the compare circuit 241′. The sources (drains) of transistors 237 and 237′ are coupled to the match line, while the drains (sources) of transistors 238 and 238′ are coupled to ground potential. These n-channel series devices perform the comparison function.

However, DRAM requires multiple internal voltage, such that word line has VPP which is higher than that of bit line high level, the pre-charge level of bit line has half VDD (VDD is array voltage), the capacitor plate has half VDD, and the bulk of the access transistor 232, 233, 232′ and 233′ have negative voltage. And it is difficult to turn off NMOS device by the storage node because the storage node does not have full high level or full low level because the capacitor will discharge.

Another memory device can be applied for configuring CAM cell. A RAM device based on said Negative Differential Resistance (NDR) device or so-called thyristor device, U.S. Pat. No. 6,229,161 “Semiconductor capacitively-coupled negative differential resistance device and its applications in high-density high-speed memories and in power switches”, has been introduced. These NDR-based RAM devices typically include at least two active elements, including an NDR device. The NDR device can be any one of a variety of NDR devices ranging from a simple bipolar transistor to more complicated quantum-effect devices. The NDR-based RAM device supports a cell area smaller than conventional SRAM cells because of the smaller number of active devices and interconnections.

However, the NDR-based RAM cell stores data into the state of the thyristor which is on or off, therefore the holding current is relatively high for whole chip during standby even though each cell has very little holding current to sustain the turn-on state of thyristor when the stored data is high. Moreover, it has high active power consumption as well, to generate negative voltage for switching gate-like device, which is said second word line. The internal negative voltage cuts off subthreshold current of the gate-like device to couple NDR device. Without negative voltage for the second word line, the stored data will be lost by the subthreshold leakage through gate-like device.

Still, there is a need in the art for a content addressable memory, which realizes high density, low power and simple structure to fabricate on the wafer.

SUMMARY OF INVENTION

The present invention is directed to a content addressable memory (CAM) including capacitor memory cell. The invention does not use static random access memory (SRAM) which has 6 transistor memory cell, or dynamic random access memory (DRAM) which stores data in a capacitor through MOS (Metal Oxide Semiconductor) access transistor having subthreshold leakage and multiple internal voltage generators, or NDR-based memory which requires holding current and internal negative voltage generator.

Rather, the invention is drawn to a capacitor memory cell based CAM which stores data in a capacitor and a p-n-p-n diode controls to store or read data “1” or “0”, wherein diode is only turned on during storing or reading data. There is no need of complex MOS device to implement the capacitor memory cell. Diode need not be a high performance device nor have a high current gain. Moreover, capacitor memory does not require internal negative voltage generator for operation and area is smaller than that of DRAM and SRAM based memory. And diode current is generally much higher than that of MOS transistor, which diode can drive bit line quickly and achieve memory speed fast. Capacitor memory based CAM offers the advantages of capacitor memory without the speed penalty associated with refresh cycle. The present invention devotes a circuit including a capacitor memory cell to configure a CAM on the bulk of wafer and on the SOI wafer, and the height of cell is almost same as that of control circuit to integrate CAM cells and other control circuits on a chip, and a timing to refresh sustaining data for a predetermined time. In so doing, the invention answers the need to take advantage of capacitor memory in a CAM while preserving the high speed performance demanded of any CAM.

These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings which are incorporated in and form a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention:

FIG. 1 depicts an SRAM-based content addressable memory (CAM) cell as a prior art.

FIG. 2 depicts a DRAM-based content addressable memory (CAM) cell as a prior art.

FIG. 3 illustrates the present invention of capacitor memory based CAM.

FIG. 4 illustrates write and read timing of the capacitor memory shown in FIG. 3.

FIGS. 5a and 5b illustrate I-V curve of the capacitor memory shown in FIG. 3.

FIG. 6 provides a truth table summarizing the logical relationships among various signals in FIG. 3.

FIG. 7 illustrates refresh operation for the present invention when the stored data is “high”.

FIG. 8 illustrates refresh operation for the present invention when the stored data is “low”.

FIGS. 9a and 9b illustrate the cross sectional views of one embodiment for the present invention on the SOI wafer. 9a is shown from the word line direction, and 9b is shown from the bit line direction.

FIGS. 10a and 10b illustrate the cross sectional views of one partially vertical embodiment for the present invention on the bulk. 10a is shown from the word line direction, and 10b is shown from the bit line direction.

FIG. 11 illustrates the cross sectional view of one vertical embodiment of the memory cell which is seen from the word line direction of the CAM for the present invention on the SOI wafer.

FIG. 12 illustrates an alternative embodiment with reverse configuration for the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT(S)

Reference is made in detail to the preferred embodiments of the present invention, which is a content addressable memory (CAM) including capacitor memory cell. While the invention is described in conjunction with the preferred embodiments, the invention is not intended to be limited by these preferred embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, as is obvious to one ordinarily skilled in the art, the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so that aspects of the invention will not be obscured.

In FIG. 3, a schematic of the CAM cell for the present invention is shown. The memory cell 310 and 310′ store data in storage capacitor 336 and 336′. These capacitor 336 and 336′ should have enough capacitance to retain data for a required time, which can include trench capacitor or high dielectric capacitor. The plate of capacitor 336 and 336′ couple to storage node 334 and 334′, but they have no coupling region to node 333, 335, 333′ and 335′. Storage node 334 and 334′ serve as the bases of n-p-n transistor 331 and 331′ respectively. The emitter 335 and 335′ of n-p-n transistors are connected to word line 344, collector of n-p-n 331 and 331′ serve as the cathodes of diode 332 and 332′ respectively. The anode of diode 332 and 332′ serve as the bit line 339 and 339′ respectively. PMOS pull-up 341 and 341′ sustain the turn-on state of diode for realizing nondestructive read. Node 342 and 342′ are bi-directional signal to read or write data. Compare circuit 320 and 320′ share a match line 346 which includes series MOS transistors, 337, 338, 337′ and 338′.

In FIG. 4, write and read timing are illustrated for the memory cell of the present invention. Word line 444 stays at high level during standby, and moves to ground level when writing or reading. Bit line 439 stays at high level during standby. Then bit line 439 determines to store data “1” or data “0”. Write operation has a sequence to store data safely. To prepare writing data “1” is to move word line 444 to ground level as shown 451 in FIG. 4, and then to raise plate signal 445, while bit line 439 keeps high level but it will go down slightly by turn-on diode. Then the storage node 434 becomes forward bias (VF1) from word line which is at ground during write operation, and the floating node 433 which is the cathode of diode 432 becomes forward bias (VF2) from the bit line which is at high level to write data “1”. The current flows from bit line to word line, after then plate returns to ground level, however rising plate can not couple storage node because current flow is stronger than coupling. As a result, the storage node 434 keeps forward bias and p-n-p-n diode is still turned-on. After plate returned to ground level, the word line 444 returns to high level, which cut off the current path from the bit line to word line because both lines are at high level and plate is isolated by insulator. After write cycle, reverse bias leakage of diode helps to keep data “1” because the storage node discharges toward high level, which makes stronger forward bias for the storage node 434, while the floating node 433 becomes strong reverse bias but it has very small parasitic capacitance only, hence the floating node 433 is controlled by the storage node 434 which has high capacitance. In this sense, data “1” does not need refresh cycle. However, data “1” can be lost when reading data “1”, word line moves down and pulls down bit line while word line is low without pull-up device with multiple read cycles before refresh cycle. To keep data “1”, PMOS pull-up is connected to bit line 439 and keeps turn-on state, and realizes non destructive read which removes restoring procedure and reduces cycle time.

To write data “0”, a sequence clears the state of diode before writing to have the same stored level regardless of previous stored level, which stored level can be discharged after a long time. This sequence needs to turn-on diode first as shown 452 in FIG. 4. After turn-on diode, bit line 439 goes down to ground level and turns off diode because word line and bit line are at ground level. After then, plate 445 returns to ground level which plate couples to storage node 434 to lower level than that of ground level, because the storage node 434 is floating. Stored voltage of data “0” is determined by the swing voltage of plate and the capacitance of storage node. After then, storage node 434 will be discharged by reverse bias leakage toward the adjacent nodes which stay at high level during standby or unselected. Capacitor oxide leakage would be ignorable in most applications with thick oxide or low leakage insulator. The floating node 433 is third terminal which is the cathode of diode 432 in FIG. 3, which node 433 depends on the state of the n-p-n transistor (331 in FIG. 3) because the third terminal 433 has very small parasitic capacitance and floating, while storage node has more charges to sustain the voltage which is stored data. The inverting voltage output is appeared in the bit line 439 and non-inverting current output 453 is appeared in the bit line. Refresh cycles are periodically asserted to sustain data “0”, which operation includes to read voltage from the cell and write inverting voltage to the cell.

In the present invention, memory array can use single power supply as shown in FIG. 4. This is very useful to configure high density and high speed memory. In some applications, plate will swing from ground level to slightly higher voltage than that of word line, which plate pulls down storage node lower to retain data longer. Plate voltage can be internally generated or externally supplied. This is another useful scheme to configure memory array.

In FIGS. 5a and 5b in view of FIG. 3, I-V curves are shown for the capacitor memory cell of the present invention. During standby, word line voltage (Vwl) is at high level which does not make any current except oxide leakage. When reading data “1”, word line moves to ground level and makes current flow (Iwl) through bit line in FIG. 5a. This means that the storage node is forward biased from the word line. The floating node 333 in FIG. 3 moves quickly down by the forward biased n-p-n 331 in FIG. 3, where the floating node 333 is floating and has very low parasitic capacitance. When reading data “0”, the storage node 334 stays at lower than ground level, which makes reverse bias for n-p-n transistor, hence n-p-n transistor can not flow current, and then p-n diode 332 can not flow current either. Voltage output of bit line is high level, which makes inverting voltage output to bit line. And non-inverting current output (IDD) 453 in FIG. 4 is appeared in the bit line. FIG. 5b illustrates reading data ‘0’ which has no current, that is, turned-off diode. And forward blocking voltage (Vfb) is illustrated when storing data “0”, where forward blocking voltage is determined by the plate swing level and storage capacitance.

In FIG. 6 in view of FIG. 3, a truth table T20 is shown summarizing the behavior of CAM cell in relation to signal states maintained by various elements within CAM cell in accordance with the present invention. First column T21 lists binary states of “0” and “1” that can be stored in storage node of the capacitor memory cell 310 in FIG. 3; second column T22 lists binary states of “0” and “1” that can be stored in storage node of the capacitor memory cell 310′ in FIG. 3. Third column T23 lists the ternary states that can be maintained in one of the complement compare data lines, namely cdata which is the signal 343′ in FIG. 3. Fourth column T24 lists the ternary states that can be maintained in the other complement compare data line, namely ncdata which is the signal 343 in FIG. 3. Fifth column T25 lists “high” and “low” as the two available voltage levels for match line 346. Finally, sixth column T26 lists “match” and “mismatch” as the two possible results for comparing states of ncdata line 343 and cdata line 343′ with the states of CAM cell.

Continuing with FIG. 6 in view of FIG. 3, row T31 indicates masked case where sdata and nsdata are “0”, which makes match line to stay the pre-charge level, regardless of the compare data because sdata and nsdata turn off MOS transistor 337 and 337′, rows T32-T33 both indicate that “0” state of CAM cell is represented by “0” of capacitor memory cell 310, and “1” of capacitor memory cell 310′. In row T32, because state “1” of cdata line 343′ does not match state “0” of CAM cell, match line 346 is driven “low” to indicate a partial mismatch of the data key and the stored value (state “0”) of CAM cell. In row T33, because state “0” of cdata line 343′ matches state “0” of CAM cell, match line 346 is driven “high” to indicate a partial match of the comparand and the stored value (state “0”) of CAM.

Continuing still with FIG. 6 in view of FIG. 3, rows T34-T35 both indicate that “1” state of CAM cell is represented by “1” of capacitor memory cell 310 and “0” of capacitor cell 310′. In row T34, because state “1” of cdata line 343′ matches state “1” of CAM cell, match line 346 is driven “high” to indicate a partial match of the comparand and the stored value (state “1”) of CAM cell. In row T35, because state “0” of cdata line 343′ does not match state “1” of CAM cell, match line 346 is driven “low” to indicate a partial mismatch of the comparand and the stored value (state “1”) of CAM cell.

Referring now to FIG. 7 in view of FIG. 3, a timing diagram for match and refresh “1” operation is shown in accordance with one embodiment of the invention. As shown, for the match/compare operation the storage node voltage 734 has enough voltage to turn on MOS device (337 in FIG. 3) when stored data is “1”, which is forward bias voltage (VF) and near the high level. Match line 746 is pre-charged at the end of the falling edge of the match line. This pre-charge makes match line 746 ready for the following cycle. After the match operation, the result of match line 746 is latched during pre-charge. Also effectively in the pre-charge of match operation, word line 744 is turned on (active low), wherein the data stored in capacitors (343 and 343′ in FIG. 3) are read, respectively, and saved into the sense amplifiers (not shown) through bit line (339 and 339′ in FIG. 3). Sense amplifiers hold the data_true 753 and data_bar 754 until the restore cycle 752 is completed. In particular, the restore cycle 752 performs to write the inverting voltage data from sense amplifier into the bit line (339 and 339′ in FIG. 3), where data_bar 754 signal drives the bit line. It makes the capacitor memory to recover the previous data from the read cycle 751. The plate 745 couples to storage node 734, however the plate 745 can not affect the storage node 734, when the p-n-p-n diode is turned-on because the current flow is stronger than capacitive coupling. After refreshed, the stored data “1” will be discharged toward high level after, but the discharge helps to sustain data “1”. In this sense, data “1” does not require refresh cycle while data “0” requires refresh cycle.

In FIG. 8, a timing diagram for match and refresh “0” operation is shown in accordance with one embodiment of the invention. The sense amplifier reads data from the cell, and has data_true 853 and data_bar 854 in the sense amplifier (not shown) during the read cycle 851. After compare operation, diode is turned on by raising plate 845 in restore cycle 852 in order to clear the storage node 834 which can be discharged from the previous write or refresh cycle. After then, bit line 839 moves to ground to turn off diode. After turning on diode, the plate 845 returns from high level to ground level which couples to storage node 834 lower than ground level. After restoring, the storage node 834 will move toward high level because word line 844 and bit line 839 are at high level during standby and unselected. Refresh will help to sustain data “0” effectively in the manner.

Continuing with FIG. 8 in view of FIG. 3, the refresh/restore operation can be implemented in multiple stages in order to avoid speed penalty. Specifically, because restoring data can sometime take longer to complete (in the case of restoring a “0”), combining restore with refresh slows down performance of the CAM. In FIGS. 7 and 8, refresh cycle has two separate cycles such that the first cycle is read and the second cycle is restore cycle. However, in slow applications, single refresh cycle is still available to reduce complexity of circuit control because the capacitor memory is faster than conventional DRAM with using diode in order to read data from the storage node while DRAM needs to wait the charge redistribution between the storage node and the bit line which has higher capacitance in general.

FIG. 9a outlines one embodiment of a fabrication technique on the SOI wafer for the capacitor memory cell of the present invention (compare circuit is not shown), wherein word line 911 is connected to n-type region 916 through silicide layer 915 which reduces contact resistance, n-type region 916 is attached to p-type region 917, p-type region 917 is attached to n-type region 918, n-type region 918 is attached to p-type region 919, p-type region 919 is attached to bit line 912 through silicide layer 920. The plate of capacitor 913 couples to p-type region 917, which plate 913 has no coupling region to n-type region 916 and n-type region 918. Inversion layer 914 is isolated from the adjacent nodes, which inversion layer 914 can be appeared when the voltage of plate 913 is higher than storage node 917. With no coupling region, plate can swing from ground level to high level because inversion layer does not make any leakage to adjacent nodes. The oxide layer between plate 913 and inversion layer 914 has higher dielectric constant than that of control circuit to have more capacitance, and the metal shunting line 921 is added to connect to plate 913 repeatedly outside of the memory array to reduce resistance of polysilicon plate. The memory cell is isolated from the substrate region 924 by the isolation layer 923. The layer 922 blocks silicide. FIG. 9b shows the bit line direction of the memory cell, where the cell is isolated from the substrate 924 by insulator 923. The height of cell is almost same as control circuit.

This configuration removes complicated MOS device from the memory cell, as a result, the memory cell has a capacitor and a diode, which is simple to fabricate and analyze as long as reverse bias leakage and oxide leakage are controllable. Another leakage path is so-called back channel effect in the planar structure of wafer from the parasitic MOS transistor, such that the substrate 924 serves as gate, n-type region 916 and 918 serve as source/drain, p-type region 917 serves as body. Related references are disclosed, Chen et al, “Characterization of back-channel subthreshold conduction of walled SOI devices”, IEEE Transactions on electron Devices, Vol. 38, No. 12, pp 2722, December 1991, and Shin et al, “Leakage current models of thin film silicon-on-insulator devices”, Applied Physics Letters, Vol. 72, No. 10, March 1998. This back channel effect is reduced or removed by adding additional n-type ions near the bottom side of the third terminal 918, or applying high voltage (higher than the standby voltage of word line) to the substrate 924.

FIG. 10a outlines one embodiment of a fabrication technique to remove back channel effect and add trench capacitor on the wafer for forming the capacitor memory cell of the present invention wherein word line 1011 is connected to n-type region 1016 through silicide layer 1015, n-type region 1016 is attached to p-type region 1017, p-type region 1017 is attached to n-type region 1018, n-type region 1018 is attached to p-type region 1019, p-type region 1019 is attached to bit line 1012 through silicide layer 1020. To remove parasitic MOS transistor, p-type region 1019 is vertically attached on the n-type region 1018. Furthermore, in order to increase storage capacitance, trench capacitor is added as shown FIG. 10b. This trench capacitor is formed between one storage node and the other storage node after forming diode, such that the plate of trench capacitor 1014 is connected to plate 1013, and layer 1014 and storage node 1017 are isolated by insulator and make capacitor. FIG. 10b is shown from the bit line direction of the memory cell, where the whole memory cell is isolated from the well 1024 by insulator 1023. The height of cell is almost same as control circuit.

FIG. 11 outlines one vertical embodiment of a fabrication technique on the bulk or SOI wafer for the capacitor memory cell, where the memory cell is implemented inside of trench area 1150, the plate 1156 is placed in the bottom, word line 1151 is connected to n-type region 1154 through silicide layer 1153, n-type region 1154 is attached to p-type region 1155 which is on the lower side of region 1154 and is coupled by plate 1156, p-type region 1155 is attached to n-type region 1157 which is on the upper side of region 1155, n-type region 1157 is attached to p-type region 1158 which is on the upper side of region 1157, bit line 1152 is connected to p-type region 1158. To make a p-n junction for region 1157 and 1158, there is one of alternative embodiment, which is metal semiconductor diode. The leakage of this diode between n-type 1157 and metal 1158 does not matter for storing data because n-type region 1157 is floating and does not have any data, where data is stored in the region 1155. There is a related reference to fabricate metal semiconductor diode with CMOS process, Sankaran et al, “Schottky barrier diodes for millimeter wave detection in a foundry CMOS process”, IEEE Electron Device Letters, Vol. 26, No. 7, pp 492-494, July 2005. The present invention can use various type of metal to form metal semiconductor diode, and more useful applications are to use various types of semiconductor, such as silicon, germanium, GaAs, SiGe and others, as long as reverse bias leakage is controllable. The memory cell is isolated from the well or substrate region 1165 by insulator 1164. The control circuit is depicted in the same figure, such that the gate 1160 has source/drain region 1161, another source/drain region 1163, and the body 1162. This figure illustrates that the height of capacitor memory cell can be almost same as that of control circuit.

While the description here has been given for configuring the memory circuit and structure, an alternative embodiment would work equally well with reverse connection. In FIG. 12, the word line 1244 is connected to emitter 1235, bit line 1239 is connected to cathode of diode 1232. First terminal 1235 is p-type and serves as word line, second terminal 1234 is n-type and serves as storage node, third terminal 1233 is p-type and floating, and fourth terminal 1239 is n-type and serves as bit line. Plate 1245 couples to the storage node and has no coupling region with first, third and fourth terminal. NMOS pull-down 1241 is applied to sustain the turn-on state of diode when stored data is “1”. Node 1242 is bidirectional signal to write and read data. Word line and bit line stay at ground level, and plate stays at high level during standby.

CONCLUSION

A content addressable memory including capacitor memory cell is realized on the bulk or SOI wafer. Fabrication is compatible with CMOS process with additional steps. Memory cell area is minimized and smaller than that of DRAM, SRAM, or NDR-based CAM. There are many embodiments for implementing the memory cells and circuits depending on the applications.

Circuit implementation is simpler than that of these days memory having multiple power supply. The present invention has single or dual positive power supply for the memory operation.

The refresh cycles are hidden from the outside of the chip, which can reduce the complexity of upper level system configuration.

The foregoing descriptions of specific embodiments of the invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to explain the principles and the application of the invention, thereby enabling others skilled in the art to utilize the invention in its various embodiments and modifications according to the particular purpose contemplated. The scope of the invention is intended to be defined by the claims appended hereto and their equivalents.

Claims

1. A content addressable memory, comprising:

capacitor memory cell wherein includes a capacitor and a diode, which capacitor stores data and diode controls to store data “1” or “0”, which diode has four terminals, first terminal is n-type and serves as word line, second terminal is p-type and serves as storage node, third terminal is n-type and floating, fourth terminal is p-type and serves as bit line, and plate of capacitor couples to second terminal, which plate has no coupling region to first, third and fourth terminal; and

at least one compare circuit coupled among the memory cell and at least one match line to receive first and second signal sets and affect a logical state of the match line in response to a predetermined logical relationship between the first and second signal sets, the compare circuit including a first transistor set and a second transistor set, wherein the first signal set couples to control a conduction state of the first transistor set and the second signal set couples to control a conduction state of the second transistor set, wherein the first signal set includes stored data and the second signal set includes comparand data.

2. The content addressable memory of claim 1, wherein can be implemented an alternative embodiment with reverse configuration, such that diode has four terminals, wherein first terminal is p-type and serves as word line, second terminal is n-type and serves as storage node, third terminal is p-type and floating, fourth terminal is n-type and serves as bit line, and plate of capacitor couples second terminal, which plate has no coupling region to first, third and fourth terminal.

3. (canceled)

4. (canceled)

5. (canceled)

6. (canceled)

7. (canceled)

8. (canceled)

9. (canceled)

10. (canceled)

11. (canceled)

12. The content addressable memory of claim 1, wherein the capacitor has higher dielectric constant than that of control circuit in the chip.

13. The content addressable memory of claim 1, wherein the diode is formed from silicon diode.

14. The content addressable memory of claim 1, wherein the fourth terminal of the diode uses metal to form metal semiconductor diode.

15. The content addressable memory of claim 1, wherein the diode is formed from compound semiconductor diode, such as GaAs, SiGe.

16. The content addressable memory of claim 1, wherein the diode is formed from germanium diode.

17. (canceled)

18. (canceled)

19. (canceled)