METHOD OF FORMING A NON-CONTINUOUS CONDUCTIVE LAYER FOR LAMINATED SUBSTRATES
A method of fabricating a circuit board is provided that includes forming a first layer of conductive material over an insulating layer, removing portions of the conductive material to define a first circuit pattern and a first rail area that is electrically isolated from the first circuit pattern, and removing portions of the conductive material from the first rail area. Optionally, the first rail area is positioned generally adjacent to a first edge of the circuit board and spans at least a portion of the length of the first edge. Optionally, portions of the conductive material of the first layer are removed to define a second rail area that is electrically isolated from the first circuit pattern and the first rail area, and portions of the conductive material of the first layer are also removed from the second rail area.
This is a divisional application of application Ser. No. 10/804,952, filed Mar. 19, 2004 and entitled “METHOD OF FORMING A NON-CONTINUOUS CONDUCTIVE LAYER FOR LAMINATED SUBSTRATES”, which is a divisional application of application Ser. No. 09/968,564, filed Oct. 1, 2001 and entitled “METHOD OF FORMING A NON-CONTINUOUS CONDUCTIVE LAYER FOR LAMINATED SUBSTRATES”, now U.S. Pat. No. 6,729,024, which is a divisional application of application Ser. No. 09/634,064, filed Aug. 8, 2000 and entitled “NON-CONTINUOUS CONDUCTIVE LAYER FOR LAMINATED SUBSTRATES”, now U.S. Pat. No. 6,429,385. This application is also related to application Ser. No. 10/210,219, filed Aug. 1, 2002 and entitled “NON-CONTINUOUS CONDUCTIVE LAYER FOR LAMINATED SUBSTRATES”, now U.S. Pat. No. 6,727,437, which is a continuation application of application Ser. No. 09/634,064, now U.S. Pat. No. 6,429,385.
FIELD OF THE INVENTIONThe present invention relates to the field of circuit board and substrate manufacture and, more particularly, to a non-continuous conductive layer for laminated substrates.
BACKGROUND OF THE INVENTIONCircuit boards and printed circuit boards (PCB) are commonly used in electronic devices of today. Many electronic devices, such as motherboards, memory devices, video adaptors, network cards and the like are created using circuit boards.
Generally, a circuit board is a flat piece of insulating material such as fiberglass, epoxy or phenolic resin, on which electrical components are mounted and interconnected to form a circuit. The flat piece of insulating material forms the substrate. A laminated circuit board is a circuit board in which a conductive layer is laminated onto an insulating layer. Circuit boards or PCBs have multiple conductive paths or interconnects to provide electrical connections among circuit components on the board.
The connections between components on a circuit board are typically created by using photolithography. The circuit pattern is drawn, photographed, and reduced to a negative having the desired final size. This negative is called the photomask or mask. Light is passed through the mask onto a substrate having a conductive layer that has been coated with a photoresistive material. Where light strikes the photoresistive material, its composition is changed. In the next step, the photoresistive material not affected by light is washed off. Finally, the circuit board is exposed to an etching solution that eats away the parts of the conductive layer not protected by the photoresistive material, creating the desired circuit pattern on the surface of the circuit board.
Standard substrates are used for circuit boards and devices such as memory devices. Minor defects or deformations in these substrates or circuit boards can have a significant impact on further processing of the circuit board which includes attaching components, such as integrated circuits, to the circuit board. Processing requires strict tolerances and even minor deformations can damage equipment or render a circuit board useless. For example, even a 1/16″-⅛″ bow in a substrate for a dual in line memory module (DIMM) can cause problems in processing the module.
What is needed is a way to reduce warping or deforming of circuit boards during processing.
SUMMARY OF THE INVENTIONA method for fabricating a circuit board having a non-continuous conductive layer is disclosed. A conductive layer is laminated onto an insulating layer. A pattern is etched on the conductive layer to eliminate continuous lengths of conductive material.
A method for fabricating a circuit board is disclosed. A conductive layer is formed over an insulating layer. The conductive layer has a first rail area, a pattern area and a second rail area. The pattern area of the conductive layer is patterned. Conductive material from the first and second rail areas is removed.
A module board is disclosed. The module board includes a circuit board, a pattern and rails. The circuit board has a conductive layer of a conductive material laminated to an insulating layer. The pattern is etched onto the substrate. The rail is located along a first and second length of the substrate. The rail is an area not etched from the pattern. Conductive material is at least partially removed from the rails to remove continuous lengths of conductive material from the circuit board.
Other methods, systems and devices are disclosed.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
The term “patterning” refers to one or more steps that result in the removal of selected portions of layers. The patterning process is also known by the names photomasking, masking, photolithography and microlithography. The term “circuit board” refers to a flat piece of insulating material, such as epoxy or phenolic resin, on which electrical components are mounted and interconnected.
As stated earlier,
Having described the invention in detail and by reference to preferred embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims. For example, support and guidance structures used in packaging often have continuous layers of conductive material. Gaps or portions of conductive material can be removed from support and guidance structures to reduce deformations caused by the memory effect.
Claims
1. A method of fabricating a memory device on a laminated circuit board wherein the laminated circuit board has a length, a width and a thickness, the method comprising:
- laminating a metal layer to an insulating layer;
- removing metal from the metal layer to define conductive paths, bonding pads, and rails, said rails defined along at least a portion of the edges of the length of the circuit board where no metal has been removed, said rails electrically isolated from said conductive paths and bonding pads; and,
- etching the rails to remove metal therefrom.
2. The method of claim 1, wherein etching the rails includes removing all metal from the rails.
3. A method of fabricating a memory device on a laminated circuit board, wherein the laminated circuit board has a length, a width and a thickness comprising:
- laminating a first metal layer to a first side of an insulating layer;
- laminating a second metal layer to a second side of an insulating layer;
- etching conductive paths and bonding pads onto the first metal layer to define at least one first side die site and at least one first side rail wherein said first side rail comprises a continuous strip of said first metal layer that is electrically isolated from said at least one first side die site;
- etching conductive paths and bonding pads onto the second metal layer to define at least one second side die site and at least one second side rail, wherein said second side rail comprises a continuous strip of said second metal layer that is electrically isolated from said at least one second side die site; and,
- etching either said at least one first side rail, said at least one second side rail, or both said at least one first side rail and said at least one second side rail to remove at least a portion of the metal.
4. The method of claim 3, wherein etching conductive paths and bonding pads onto the first metal layer for at least one first side die site comprises removing metal from the first metal layer, resulting in forming rails along edges of the length of the first metal layer where the rails have no metal removed and wherein etching conductive paths and bonding pads onto the second metal layer for at least one second side die site comprises removing metal from the metal layer, resulting in forming rails along edges of the length of the second metal layer where the rails have no metal removed.
5. The method of claim 3, wherein etching the rails comprises removing sections of metal from the rails.
6. The method of claim 3, wherein etching the rails comprises removing all metal from the rails.
7. A method of forming a circuit board comprising:
- forming a circuit board having an insulating layer sandwiched between a first conductive layer and a second conductive layer;
- etching said first conductive layer defining a first site comprising a first patterned area of conductive traces, and a first generally rectangular rail extending adjacent to a first edge of said first conductive layer spanning substantially the length thereof, said first rail electrically isolated from said first patterned area and comprises gaps etched into said first conductive layer; and,
- etching said second conductive layer defining a second site comprising a second patterned area of conductive traces, a third generally rectangular rail extending adjacent to a first edge of said second conductive layer spanning substantially the length thereof, and a fourth generally rectangular rail extending adjacent to a second edge of said second conductive layer spanning substantially the length thereof, said third and fourth rails electrically isolated from said second patterned area and comprise gaps etched into said second conductive layer.
8. A method of forming a circuit board according to claim 7, further comprising:
- a second generally rectangular rail extending adjacent to a second edge of said first conductive layer spanning substantially the length thereof, said second rail electrically isolated from said first patterned area and comprises gaps etched into said first conductive layer.
Type: Application
Filed: Feb 15, 2007
Publication Date: Jun 14, 2007
Inventor: Patrick Tandy (Boise, ID)
Application Number: 11/675,365
International Classification: H01R 12/00 (20060101);