Method for fabricating saddle type fin transistor
A method for fabricating a saddle type fin transistor includes: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin. The hard mask pattern may be formed in a stack structure including an amorphous carbon layer and the coating layer.
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The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a saddle type fin transistor having characteristics of a fin transistor and a recess transistor.
DESCRIPTION OF RELATED ARTSGenerally, transistors having horizontal channels that are most widely used often have disadvantages associated with a current trend in the large-scale of device minimization and integration. Thus, the minimization of such transistors becomes limited. The minimized horizontal channels of the transistors may have disadvantages such as a short channel effect and a drain induced barrier lower (DIBL) effect, usually caused by a shortened channel length. If the channel length is decreased to 50 nm or less, process variations increase, resulting in scattered device characteristics. If the channel length is decreased to 30 nm or less, the short channel effect and the DIBL effect become severe, often disabling a normal device operation. Therefore, a dual gate transistor is suggested to overcome the above mentioned disadvantages. In general, the dual gate transistor has a structure including channels and gates that surround the channels or are disposed in both sides of the channels.
For the transistors having the horizontal channels, the gate electrodes are formed on the horizontal channels. Thus, an electric field that has an upward/downward unbalance is more likely to be applied to the horizontal channels, and as a result, controlling an on/off operation of the transistors is generally difficult due to the gate electrodes. As the channel size decreases, the short channel effect becomes pronounced. On the contrary, gate electrodes of dual gate transistors having vertical channels are commonly formed in both sides of the thin channels. Thus, the gate electrodes generally affect the entire channel regions. When the transistors are turned off, a current flow can be controlled between a source and a drain. As a result, power consumption can be reduced, and the on/off operation can be controlled effectively.
Fin transistors are one example of the transistors having the vertical channels.
Another example of the transistors having the vertical channels is a recess transistor 20 (or a trench transistor) illustrated in
Referring to
A high density plasma layer having a good gap-filling property is formed to fill the trenches. A chemical mechanical polishing (CMP) process is performed thereon to planarize the high density layer. As a result, a device isolation structure 111 defining an active region and a field region is formed. A wall oxide layer may be formed on the inner surface of the trenches where the device isolation structure 111 is formed. The wall oxide layer is formed using an oxidation treatment, which also rounds the inner surface of the trenches.
An amorphous carbon layer 112A, a silicon oxynitride (SiON) layer 112B and an anti-reflective coating layer 113 are formed sequentially on the above resulting structure. A photoresist pattern 114 is formed on the anti-reflective coating layer 113 using a photolithography process. The anti-reflective coating layer 113 is a bottom anti-reflective coating layer and, is formed of an organic or inorganic material. The amorphous carbon layer 112A and the SiON layer 112B serve as a hard mask.
Referring to
Referring to
Referring to
As described above, the amorphous carbon layer 112A is used as a hard mask material for forming the saddle type fin 115. Thus, when the field region and the active region (i.e., the device isolation structure 111 and the substrate 110) have different heights, those layers for forming the hard mask pattern 112 are formed over the device isolation structure 111 and the substrate 110 with different heights. Detail description of this step coverage characteristic of the hard mask pattern 112 comprising amorphous carbon, will be provided in
As the saddle type fin (S-fin) has a large height difference, the FICD thereof becomes increased. As a result, as illustrated in
It is, therefore, an object of the present invention to provide a method for fabricating a saddle type fin transistor advantageous of improving a device characteristic by reducing an increase of a FICD of a target structure, usually caused by a height difference between an active region and a field region.
In accordance with an aspect of the present invention, there is provided a method for fabricating a saddle type fin transistor, including: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin.
BRIEF DESCRIPTION OF THE DRAWINGSThe above and other objects and features of the present invention will become better understood with respect to the following description of the exemplary embodiments given in conjunction with the accompanying drawings, in which:
A method for fabricating a saddle type fin transistor in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. If it is stated that a layer is formed “on” another layer or on a substrate, it should be construed that the layer is formed directly on the other layer or on the substrate, or a third layer may be interposed therebetween. Also, like reference numerals denote like elements even in different drawings.
Instead of using the amorphous carbon layer 112A as a hard mask pattern (refer to
As illustrated in
As illustrated in
The saddle type fin transistor according to the embodied fabrication method can be obtained using substantially the same processes as the typical method illustrated in
According to the embodiments of the present invention, the fin etching process is performed using a coating material that can be easily planarized. Thus, a FICD of a target structure (i.e., the saddle type fin or gate) is less likely to increase, and as a result, a short circuit effect or leakage current may not be induced during subsequent processes. Accordingly, a device characteristic can be improved.
The present application contains subject matter related to the Korean patent application No. KR 2005-133846, filed in the Korean Patent Office on Dec. 29, 2005, the entire contents of which being incorporated herein by reference.
While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims
1. A method for fabricating a saddle type fin transistor, comprising:
- preparing a substrate where a device isolation structure is already formed;
- forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and
- performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin.
2. The method of claim 1, wherein the hard mask pattern is formed in a stack structure including an amorphous carbon layer and the coating layer.
3. The method of claim 2, wherein the amorphous carbon layer is formed over the coating layer.
4. The method of claim 2, wherein the amorphous carbon layer is formed underneath the coating layer.
5. The method of claim 3, wherein the coating layer includes an anti-reflective coating layer.
6. The method of claim 4, wherein the coating layer includes an anti-reflective coating layer.
7. The method of claim 5, wherein the coating layer is formed to a height larger than a height difference created beneath the hard mask pattern.
8. The method of claim 6, wherein the coating layer is formed to a height larger than a height difference created beneath the hard mask pattern.
9. The method of claim 7, wherein the forming of the hard mask pattern comprises:
- forming a silicon oxynitride (SiON) layer over the hard mask pattern;
- coating an anti-reflective coating layer over the SiON layer;
- forming a photoresist pattern over the anti-reflective coating layer; and
- performing a photolithography process on the photoresist pattern to sequentially etch the anti-reflective coating layer, the SiON layer and the hard mask pattern.
10. The method of claim 8, wherein the forming of the hard mask pattern comprises:
- forming a silicon oxynitride (SiON) layer over the hard mask pattern;
- coating an anti-reflective coating layer over the SiON layer;
- forming a photoresist pattern over the anti-reflective coating layer; and
- performing a photolithography process on the photoresist pattern to sequentially etch the anti-reflective coating layer, the SiON layer and the hard mask pattern.
Type: Application
Filed: Jun 29, 2006
Publication Date: Jul 5, 2007
Applicant:
Inventor: Kwang-Ok Kim (Kyoungki-do)
Application Number: 11/480,198
International Classification: H01L 21/8234 (20060101); H01L 21/336 (20060101);