Methods to make DRAM fully compatible with SRAM
This invention provides practical methods to make a DRAM fully compatible with existing SRAM products. This is accomplished by design and manufacture methods according to the invention, which includes a method to reduce standby power of reference voltage generators and a method to avoid the alpha particle problem using a novel error correction code (ECC) mechanism. The reference voltage generator of the present invention can adjust the values of output voltage and driving power separately following simple procedures. It has very strong driving power to maintain the reference voltage, which is necessary to support high-speed operation of memory devices of the present invention. In the mean time, its standby power can be reduced by orders of magnitudes using simple control mechanism, which is necessary to make our memory device compatible with the properties of existing SRAM products. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable. It is an ideal reference voltage generator to generate the bit line pre-charge voltage for a DRAM designed to emulate an SRAM device. The unique features of the ECC protection of the present invention avoid RC delay problems in prior art ECC circuits, which is necessary to support high speed operation of our products. The alpha particle problem is no longer an issue. All the supporting circuits can use repeated layouts, which is very important for memory design. The manufacture technology for embedded IC is simplified dramatically, which allow us to have high performance logic circuits. The memory devices of the present invention are therefore compatible in every detailed feature with existing SRAM products.
This Application is a Divisional Application of a co-pending application Ser. No. 08/989,841 filed on Dec. 12, 1997 and application Ser. No. 08/989,841 is a Continuation-in Part application Ser. No. 08/653,620 filed on Mar. 24, 1996 by the same Applicant of this Application.
BACKGROUND OF THE INVENTIONThe present invention relates to methods to make a dynamic random access memory (DRAM) fully compatible with a static random access memory (SRAM).
DRAM and SRAM are two major types of memory devices in the Integrated Circuit (IC) industry. DRAM of current art always has lower performance relative to SRAM, while SRAM is more expensive. Therefore, DRAM of current art is used for cost-sensitive applications, while SRAM is used for applications that require performance, power efficiency, or user-friendliness. Since the logic circuits of current art is operating at much high frequencies than DRAM, memory access operations are often the performance bottleneck for computers. A typical solution for this performance bottleneck is to use a large number of low cost DRAM's as the main memory, while using a smaller number of high performance SRAM's as cache memory. This multiple level memory structure provides necessary compromises to balance cost efficiency and performance requirements. However, complex logic circuits are needed to assure data consistency of this memory structure. In many cases, memory operations are still the performance bottleneck for computer systems. It is therefore highly desirable to be able to manufacture high performance and cost efficient memories to remove multiple level memory structures in computer systems.
The need to manufacture different types of memory devices causes tremendous wastes in the IC industry. DRAM's are typically manufactured by 4 layer poly, double layer metal (4P2M) technology; SRAM's are typically manufactured by 2 layer poly, double layer metal (2P2M) technology; logic circuits require technologies with many metal layers such as a single layer poly, 4 layer metal (1P4M) technology. Details of transistor manufacture procedures are also different between memory and logic. DRAM technologies emphasize on leakage current reduction and high voltage tolerance, so it needs to use thick gate, long channel transistors with higher threshold voltage. Logic circuits emphasize on performance, so they prefer thin gate, short channel transistors with lower threshold voltage. An SRAM technology needs to have special modules to build poly resistors. Due to these conflicting requirements, researchers in the IC industry must develop different manufacturing technologies to build DRAM's, SRAM's, and logic circuits separately. It is therefore highly desirable to simplify those conflicting needs from different types of products.
One approach to solve the above long-existing problem is to improve the data access rate of DRAM using parallel processing and pipeline concepts in DRAM design. Well-known products using such approaches are the synchronized DRAM (SDRAM), the RAMBUS system approach, and the multiple-bank DRAM (MDRAM). The major problem for those products is that they are not compatible with existing products. The computer industry does not want to change existing designs to adapt for those new memory structures. The other problem is that these approaches improve data access rate without improving memory latency.
Another approach is to make a DRAM device behaves as an SRAM device using self-refresh circuits. This type of memory device is user-friendly because it has the same interface as conventional SRAM devices. However, they are not very useful because performance of such self-refresh DRAM is as low as conventional DRAM, while it requires high standby power to support self-refresh operations.
The above inventions and developments provided partial solutions to memory design problems, but the computer industry resists to adapt to such partial solutions. Meeting requirements in performance and cost efficiency is not enough. To be successful, a novel solution must be compatible to existing memory devices in every details. U.S. Pat. No. 8,653,620 described methods to make a DRAM as fast as SRAM including a self-refresh mechanism which is completely invisible to external users. U.S. Pat. No. 8,805,290 described methods to build smaller memory device using the same manufacture technologies used to build logic IC products. The above two inventions allow us to make memories faster than SRAM of current art while using silicon area as small as that of DRAM of current art. However, there are further detailed problems we must solve to make our products truly compatible with existing industry standards. The present invention is developed to cover those remaining details.
The first issue is the standby power problem. An SRAM consumes almost no power when it is not used. A DRAM consumes power even when the user is not using the memory. There are two major sources for this waste in energy. The most well-known source comes from the memory refresh operations. The self-refresh mechanism described in U.S. Pat. No. 8,653,620 improved energy efficiency for memory refresh, and solved the problem effectively. The other major source comes from the DRAM pre-charge circuits. Bit lines of DARM are usually pre-charged to a voltage near half of its power supply voltage. In order to make the product fully compatible with SRAM, we must have an internal reference voltage generator to maintain this pre-charge voltage. Reference voltage generators of current art consume standby powers. Because our product is much faster than conventional DRAM, the reference voltage generator need to have much stronger driving capability than those used by conventional DRAM's. It is therefore even more difficult to meet the requirements on standby power. This problem must be solved because the computer industry expects low standby power from SRAM's.
Another important issue is a reliability problem known as “alpha particle problem”—high energy particles hit an integrated circuit, and change the contents of its memory elements. The memory cells used in our previous inventions are more sensitive to the alpha particle problem than conventional SRAM devices. It is therefore desirable to develop an error correction mechanism to correct errors caused by the alpha particle problem.
SUMMARY OF THE INVENTIONThe primary objective of this invention is, therefore, to provide practical methods to make a DRAM fully compatible with existing SRAM products. This and other objects are accomplished by design and manufacture methods according to the invention, which includes a method to reduce standby power of reference voltage generators and a method to avoid the alpha particle problem using a novel error correction code (ECC) mechanism.
The reference voltage generator of the present invention can adjust the values of output voltage and driving power separately following simple procedures. It has very strong driving power to maintain the reference voltage, which is necessary to support high speed operation of memory devices of the present invention. In the mean time, its standby power can be reduced by orders of magnitudes using simple control mechanism, which is necessary to make our memory device compatible with the properties of existing SRAM products. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable. It is an ideal reference voltage generator to generate the bit line pre-charge voltage for a DRAM designed to emulate an SRAM device. The unique features of the ECC protection of the present invention avoid RC delay problems in prior art ECC circuits, which is necessary to support high speed operation of our products. The alpha particle problem is no longer an issue. All the supporting circuits can use repeated layouts, which is very important for memory design. The manufacture technology for embedded IC is simplified dramatically, which allow us to have high performance logic circuits. The memory devices of the present invention is therefore compatible in every detailed feature with existing SRAM products.
While the novel features of the invention are set forth with particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 4(a-g) illustrate the manufacture procedures for a prior art high performance IC technology that has both high speed transistor for its logic circuits and low leakage transistors for its DRAM memory cells on the same chip; and
FIGS. 5(a-d) show the manufacture procedures for the high performance integrated circuits of the present invention.
DETAILED DESCRIPTION OF THE INVENTIONFor a DRAM device, memory bit lines are typically pre-charged to a voltage around half of the power supplier voltage Vcc. In order to make a DRAM fully compatible with existing SRAM devices, this bit line pre-charge voltage must be generated internally. It is therefore necessary to have a reference voltage generator that is invisible to external users. Because our emulated “SRAM” is much faster than conventional DRAM, this internal reference generator must have a driving power much stronger than that of reference voltage generators of current art. To emulate an SRAM which has very small standby power, the voltage generator also need to consume very little standby power. These conflicting requirements for lower standby power and higher driving capability requires novel design.
Using the current to voltage relationship of Metal-Oxide-Semiconductor (MOS) transistors, we have
Istbr=Gmn*(VGN−PCGV−Vtn)2 (1)
where Gmn is a constant determined by the carrier mobility and the size of transistor MN, and Vtn is the threshold voltage of transistor MN.
Rearranging Eq. (1), we have
VGN=PCGV+Vtn+(Istbr/Gmn)1/2˜PCGV+Vtn (2)
where we used the fact that the third term (Istbr/Gmn)1/2 is usually negligible.
Similarly, we have
VGP=PCGV−Vtp−(Istbr/Gmp)1/2˜PCGV−Vtp (3)
where Gmp is a constant determined by the carrier mobility and the size of transistor MP, and Vtp is the threshold voltage of transistor MP.
If we describe the current to voltage relationships of transistors MPR and MNR using simplified ohmic relation as
VGP=Istbr*Rp (4)
Vcc−VGN=Istbr*Rn (5),
from Eqs. (2-5) we have
Istbr=(Vcc−Vtp−Vtn)/(Rp+Rn) (6)
PCGV=(Vcc+Vtp−Vtn)/2+[(1−Rp/Rn)/(1+Rp/Rn)]*(Vcc−Vtp−Vtn)/2 (7)
where Rp is the effective resistance of transistor MPR, and Rn is the effective resistance of transistor MNR.
The transistor MNO in
At steady state, the standby leakage current Istb is
Istb=Mc*Istbr=Mc*(Vcc−Vtn−Vtp)/(Rn+Rp) (8)
which suggest that standby leakage current Istb can be reduced by reducing the width ratio Mc or by increasing (Rp+Rn). However, reducing the standby leakage current Istb will also reduce the driving power of driving transistors MPO and MNO, which will make the output voltage VOUT more noisy when the IC is active.
The effective sizes of transistors MPR, MNR, MP, MN for a practical example is shown in Table I. In this example, the standby current Istb equals to 0.01 mamps when the switch control signal ZZ is high, and Istb increase to 5 mamps when ZZ is low. In the mean time, the driving capability represented by output current Iout increases significantly when ZZ is high as shown in
A reference voltage generator of the present invention can be designed by the following procedures:
- step 1: determine the target value of output voltage PCGV, then calculate Rp/Rn ratio using Eq. (7);
- step 2: based on noise margin, calculate the required driving power of the output transistors MNO, MNP, then determine the sizes of transistors MNR1, MPR1, MN1, MP1;
- step 3: determine the value of tolerable standby leakage current Istb to determine the sizes of transistors MNR2, MPR2, MN2, MP2 according to EQ. (8);
- step 4: design the logic circuit to generate the switch control signal ZZ.
A reference voltage generator of the present invention has many advantages. It is very convenient to adjust its output voltage, driving power, and leakage current. The values of output voltage and driving power can be adjusted separately following simple procedures. It has very strong driving power to maintain the- reference voltage. Almost all the power consumed by this reference voltage generator is used to maintain its output voltage; there is little wasted power. Its standby power can be reduced by orders of magnitudes using simple control mechanism. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable. It is an ideal reference voltage generator to generate the bit line pre-charge voltage for a DRAM designed to emulate an SRAM device.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. There are a wide varieties of methods to design variable size transistors. Similar reference voltage generators can be manufactured using bipolar transistors instead of MOS transistors. The gate voltages of transistors MPR, MNR do not always need to be power supplier voltages. For example, we can connect their gates to PCGV to save area. The switches SPR, SNR, SP, SN can be replaced with metal options. We also can use more switches so that each variable transistor can have multiple controllable sizes. The output voltage of the reference voltage generator also can be controlled by programmable signals. These and other modification are considered falling in the spirit of the present invention.
DRAM is more sensitive to alpha particle problem then SRAM because it relies on storage capacitors to hold data. This reliability problem must be solved to make DRAM devices fully compatible to conventional SRAM devices. An error correction code (ECC) mechanism of the present invention is used to correct erroneous data caused by alpha particle problem or other sources of problems such as manufacturing defects. Due to the small dimensions of DRAM memory cells, errors tend to happen at nearby memory cells; therefore, ECC circuits of the present invention must be able to correct erroneous data from nearby memory cells. Another problem for ECC circuit is the delay caused by resistance and capacitance (RC delay) of long metal lines. Error correction logic circuits need to calculate the parity of data distributed in widely separated space; ECC calculation often needs to use long metal lines to collect data. Metal line RC delay became a dominating factor to determine the performance of the ECC circuits. To support high speed operations, this RC delay problem must be solved.
Due to the complexity of the error correction mechanism, we will need to use the array symbol used for C programming language in the following discussions to describe the mechanism. For example, D[3:2][4:1] means a set of 8 symbols D34, D33, D32, D31, D24, D23, D22, and D21. We will also use the symbol “mod” to represent the modulation operation that results in the remain of a divide operation. For example, [(k+3) mod 8] equals 2 when k=7, and [(k−3) mod 8] equals 6 when k=1. The “mod” function is implemented by a rotational relationship in the input connections of actual circuits.
FIGS. 2(c,d) are schematic diagrams of one of those 4 sets of ECC logic circuits 320 in
N11=Parity{Ck,Dk0} (9a),
N23=Parity{Dk3,Dk4,Dk7} (9b),
N33=Parity{N23B,Dk2,Dk5,Dk6} (9c),
N41=Parity{N33B,N24T,Dk1,Dk4,Dk5} (9d),
N24=Parity{Dk4,Dk5,Dk6,Dk7} (9e),
N32=Parity{Dk0,Dk1,Dk2,Dk3,Dk4,Dk5,Dk6,Dk7} (9f),
N42=Parity{N32T,N11B,Dk0,Dk1,Dk2,Dk3,Dk4,Dk5} (9g),
and
Fk=Parity{N42T,N41B} (9h),
where “Parity{}” means the parity value of all the inputs included in “{}” signs. The inputs (N11B, N22B, N33B, N41B,N24T, N32T, N42T) provided by nearby parity circuits can be determined by the fact that all of those parity circuits in
N11B=Parity{C[(k+1)mod 8],D[(k+1)mod 8]0} (10)
where C[(k+1) mod 8] is the ECC bit, and D[(k+1) mod 8]0 is the first data connected to the parity circuit below it. All other inputs (N22B, N33B, N41B,N24T, N32T, N42T) can be determined in similar ways; some of them will need to use data and ECC inputs from parity circuits farther away. Based on the connections in
Fk=Parity{Ck,D[(k−2)mod 8][7:0],D[(k−1)mod 8][5:0],D[k][7:4,0],D[(k+1)mod 8][5,4,1],D[(k+2)mod 8][6,5,2],D[(k+3)mod8][7,4,3]} (11)
where k=(0, 1, 2, 3, 4, 5, 6, 7).
During a memory write operation, external data are sent to the parity circuits (320) and the Ck inputs are forced to zero to calculate the ECC bits of the external data. Based on Eq. (11), we have
ECC(k)=Parity{D[(k−2)mod 8][7:0],D[(k−1)mod 8][5:0],D[k][7:4,0],D[(k+1)mod 8][5,4,1],D[(k+2)mod 8][6,5,2],D[(k+3)mod 8][7,4,3]} (12)
where ECC(k) is the value of ECC bit, and k=(0, 1, 2, 3, 4, 5, 6, 7). These ECC values are written into the memory array together with the input data during a write operation.
During a read operation, the data and the stored ECC values are read from the memory, and the correction factors (F7-F0) are calculated using the same parity circuits based on Eq. (11). When there is no error in the 72-bit data, all the error correction factors will be zero. When one of the 72 bit data is wrong, an odd number of the correction factors (F7-F0) will be high. Based on Eq. (12), we know that the failure pattern of the correction bits for each data bit is unique; it is therefore possible to determine which bit is wrong by observing the failure pattern of the correction bits. These error correction factors are sent to an error decoding circuit (340) shown in
The ECC mechanism of the present invention is novel by the rotation relationship in the parity calculation; parity calculation of C[k+1] is the result of simple rotation of C[k]. This rotational relationship allow us to design circuits that can be used repeatedly in physical layout, which is extremely important for memory devices. The length of metal connection is also minimized because no signals need to travel more than the distance of a small circuit block. Speed degradation caused by RC delay is therefore avoided.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. For example, Eq. (12) can be modified to different forms while keeping the rotation relationship. Different numbers of data and correction bits can be used to serve the same purpose. The novel element for the correction mechanism of the present invention is to enforce a rotational relationship in parity calculation of ECC mechanism. Based on the rotational relationship, repeating circuit design can be used to simplify design effort. Higher performance is also achieved by minimizing RC delay.
A memory device equipped with the above ECC protection mechanism will need additional logic circuits and 12.5% more memory cells than a conventional DRAM. However, this does not necessarily mean a DRAM equipped with the ECC circuits of the present invention is larger than a conventional DRAM. One reason is that we no longer need to have redundancy memory arrays because the ECC circuits will correct most of defect problems. Additional area reduction comes from improvements in memory refresh time. DRAM memory cells must be refreshed periodically; otherwise it will lose its storage data due to leakage current. The maximum time between two refresh operations is called the “refresh time” for a memory cell.
To understand the method to simplify manufacture technology using ECC method, we must understand the limitations of prior art manufacture technologies. To reduce sub-threshold leakage current, the word line transistor (303) for a prior art DRAM cell must be a long channel transistor with high threshold voltage and thick gate oxide. For performance optimization, high speed logic circuits would like to use short channel transistors with low threshold voltage and thin gate oxide. In order to meet those conflicting requirements, we must build both types of transistor on the same IC; the manufacture technology became more complex than a typical logic technology or a typical DRAM technology. FIGS. 4(a-g) illustrate the manufacture procedures for a prior art high performance IC technology that has both high speed transistors for its logic circuits and low leakage transistors for its DRAM memory cells on the same chip. In the following figures, the cross-section diagrams for an n-channel high performance logic transistor are shown in the left hand side, and the cross-section diagrams for an n-channel low leakage memory transistor are shown in the right hand side for comparison.
When the DRAM array is equipped with the above ECC protection mechanism, the memory refresh requirement is improved by many orders of magnitudes; we can use the same transistor for logic circuits and for memory cells without any charge retention problem. Using methods described in our previous patent applications, we no longer need to use high word line voltage. Therefore, we can achieve high performance by using logic transistors everywhere, and simplify the manufacture technology at the same time. The manufacture procedures of an embedded DRAM technology of the present invention is illustrated in FIGS. 5(a-c). At the first step, the procedure for Vt implant illustrated in
Using the ECC protection mechanism of the present invention in DRAM devices provides many advantages over prior art devices. The alpha particle problem is no longer an issue because the ECC circuits can correct errors from multiple nearby bits. There is no need to have redundancy array for the same reason. Our device still can operate at high performance because RC delay problems in prior art ECC circuits is solved by the rotational ECC circuits of the present invention. All the supporting circuits can use repeated layouts, which is very important for memory design. The manufacture technology for embedded IC is simplified dramatically because we can use thin gate transistors for DRAM memory cells.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all modifications and changes as fall within the true spirit and scope of the invention.
Claims
1-24. (canceled)
25. A logic transistor supported on a substrate having an embedded memory transistor also supported on same substrate provided for connection to an error-code-correction (ECC) circuit and memory cells, wherein:
- said logic transistor having a logic-transistor gate, a logic-transistor gate oxide disposed under said logic-transistor gate, and a logic-transistor channel disposed under said logic-transistor gate oxide;
- said memory transistor having a memory-transistor gate, a memory-transistor gate oxide disposed under said memory-transistor gate, and a memory-transistor channel disposed under said memory-transistor gate oxide; and
- said logic-transistor gate oxide having substantially the same thickness as said memory-transistor gate oxide, and said logic-transistor channel having substantially the same dopant concentration as said memory-transistor channel.
26. The logic transistor of claim 25 wherein:
- said memory-transistor gate oxide and said logic-transistor gate oxide having a thickness less than or equal to one-hundred Angstroms.
27. A method for manufacturing a logic transistor on a substrate with an embedded memory transistor also on said substrate ready for connection to an error-code-correction (ECC) circuit, comprising:
- performing a channel ion implant to form a logic-transistor channel and a memory-transistor channel having substantially the same doping concentration; and
- forming a gate oxide layer for said logic transistor and said memory transistor having substantially the same thickness over said logic-transistor channel and said memory-transistor channel.
28. The method for manufacturing said logic transistor of claim 27 further comprising a step of:
- forming a gate on top of said gate oxide layer for said logic transistor and said memory transistor having substantially the same thickness.
29. The method for manufacturing said logic transistor of claim 27 wherein:
- said step of forming said gate oxide layer for said logic transistor and said memory transistor is a step of forming said gate oxide layer with a thickness less than or equal to one-hundred Angstroms.
30. The method for manufacturing said logic transistor of claim 27 wherein:
- said step of performing a channel ion implant to form a logic-transistor channel and a memory-transistor channel is a step of forming said logic-transistor channel and said memory-transistor channel having a channel length less than or equal to 0.5 micrometers.
Type: Application
Filed: Jul 10, 2006
Publication Date: Jul 19, 2007
Inventor: Jeng-Jye Shau (Palo Alto, CA)
Application Number: 11/484,803
International Classification: H03M 13/00 (20060101);