System and method for an adaptive state machine to control signal filtering in a serial link
A method for adaptively filtering a control signal in a serial link includes monitoring for a blanking interval in a video stream having an associated clock signal and monitoring for an occurrence of a VSNYC signal once the blanking interval has started. A control signal is initially detected wherein the control signal occurs subsequent to the occurrence of the VSNYC signal. A set of properties of the control signal are recorded and a set of filter parameters are adjusted for detecting the control signal in a next blanking period based on the set of properties of the control signal.
This application is a continuation application of application Ser. No. 10/224,995, filed Aug. 21, 2002, which is incorporated herein by reference.
FIELD OF THE INVENTIONThe present invention relates generally to video systems, and more particularly to decryption of encrypted video signals.
BACKGROUND OF THE INVENTION
The content protection protocol used in system 10 is high bandwidth digital content protection (HDCP) commonly used on DVI (digital video interface) or panel-link type interfaces. Included in the prior art system 10 is a first content protection state machine 40, in the set top box 20, and a second content protection state machine 50, in the television receiver 30. First content protection state machine 40 encrypts video data and second content protection state machine 50 decrypts the video data before it is displayed. The reason for the encryption by content protection state machine 40 is to prevent unauthorized copying of the video signal with, for example, a video tape recorder.
A modulator 60 converts various data signals, including the video data, for efficient transport over a set of differential pairs of wires 70 that are synchronized by clock 80. A demodulator 90 then reverts the signals into a control 3 (CTL3) signal 100, a 24 bit data path 110, a set of control signal lines (CTL0, CTL1 and CTL3) 120, and a clock line 130. Also included is a microprocessor 140 that controls the entire system 10. Microprocessor 140 communicates with content protection state machine 50 via DDC (display data channel) bus 142.
The HDCP protocol specifies that the CTL3 pulse 100 needs to be at least eight clock signals wide in order for the content protection state machine 50 to be properly notified to decrypt the next video frame. A CTL3 pulse can get corrupted, however, and this results in video frames not being decrypted, when they should be, and is manifested as “snow” on a display. Conversely, video frames that do not need to be decrypted can be subjected to decryption and also results in a scrambled display. This degradation of the video signal will completely prevent the viewing of the images generated by the video signal. Some typical non-ideal CTL3 pulses include a glitch 170 or glitches 180 that will separate a CTL3 pulse into several pulses, each less than eight clock signals wide; a CTL3 pulse due to noise 190, a first false CTL3 pulse 200 where a pulse exists when one should not and a second false CTL3 pulse 210 where a pulse is present at the wrong point in time in relation to the VSYNC 16 and DE. Additionally, it is possible for the two numbers to match, even if the picture is not decrypted properly. In this situation, re-authentication is prevented when it is useful and necessary.
When a problem with the video decryption occurs, a re-authentication process needs to take place to restore the video image and can take up to several seconds. This is accomplished by comparing two 16 bit numbers before and after the video frame is encrypted/decrypted. If the two numbers do not match, the set top box 20 initiates the re-authentication process. Sometimes the numbers do not match up, however, even if the picture was decrypted properly. This causes an unnecessary re-authentication cycle to occur and results in a lost image which manifests as a glitch in the images generated by the video signal. Additionally, it is possible for the two numbers to match, even if the picture is not decrypted properly. In this situation, re-authentication is prevented when it is useful and necessary.
Accordingly, what is needed is a method to screen out invalid control signals, accurately detect valid control signals and prevent invalid re-synchronzation cycles in order to maintain a continuous video stream on a display.
SUMMARY OF THE INVENTIONThe present invention provides a system and method for an adaptive state machine to control signal filtering in a serial link. By updating filter parameters based upon the characteristics of the control signal, accurate detection of the control signal is achieved. When applied to a video transmission environment, loss of picture is virtually eliminated.
A method for adaptively filtering a control signal in a serial link, in accordance with the present invention, includes monitoring for a blanking interval in a video stream having an associated clock signal and monitoring for an occurrence of a VSYNC signal once the blanking interval has started. A control signal is initially detected wherein the control signal occurs subsequent to the occurrence of the VSYNC signal. A set of properties of the control signal are recorded and a set of filter parameters are adjusted for detecting the control signal in a next blanking period based on the set of properties of the control signal.
A system for adaptively filtering a control signal in a serial link, in accordance with the present invention, includes a transmitter that is responsive to an authentication signal and is operative to develop a plurality of data signals and a clock signal on a plurality of differential pairs. A receiver, coupled to the plurality of differential pairs, includes a demodulator that is responsive to the plurality of data signals and the clock signal and is operative to develop a control signal, a plurality of synchronization signals and the clock signal. A content protection state machine, on the receiver, is responsive to the plurality of synchronization signals, a filtered control signal and the clock signal and is operative to develop the authentication signal. A filter, on the receiver, is responsive to the control signal and a filter parameter signal and is operative to develop the filtered control. Also included is a control machine, on the receiver, that is responsive to the control signal and is operative to develop the filter parameter signal wherein the filter parameter signal is updated based on a set of characteristics of the control signal.
An advantage of the present invention is that a custom filter can be constructed that can adaptively change and thus accurately detect valid control signals while ignoring noise, glitches and invalid signals. As a result, picture display is vastly improved since interruptions to a video signal are greatly reduced. Another advantage is that the receiver can adapt the filtering mechanism to more closely match the behavior of an existing transmitter. As a result, the quality of the filtering is improved and the receiver can work well with a wide variety of transmitters manufactured by different manufacturers.
These and other advantages of the present invention will become apparent to those skilled in the art after reading the following descriptions and studying the various figures of the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
A first section 246 of the non-adaptive filter 220 uses the input flip-flops (224, 226, 232 and 234) as a four stage pipeline that keeps track of the signal history. The first section 246 only switches states (SET or CLEAR) if all four flip-flops flops (224, 226, 232 and 234) show the same result. Consequently, any glitches that are three clock signals or less will be ignored. A second section 248 ensures that the output of the first section 246 will propagate only during a low DE signal.
While the use of the non-adaptive filter 220 is an improvement, it is still possible to miss a CTL3 signal due to glitches or a false signal could occur due to noise on the control line. The use of an adaptive filter 222, as illustrated in the block diagram of
When the CTL3 width state machine 380 is enabled, a CTL3 rising edge 390 or CTL3 falling edge 400 is watched for. A count is then initiated at operations 410 and 420 to determine the width of the CTL3 pulse, which is equated to the filter depth FD. Restated, the width of the CTL3 pulse and its relationship to the leading transition on VSYNC are the filter parameters used to identify valid CTL3 pulses.
An advantage of the present invention is that a custom filter can be constructed that can adaptively change and thus accurately detect valid control signals while ignoring noise, glitches and invalid signals. As a result, picture display is vastly improved since interruptions to a video signal are greatly reduced. Another advantage is that the receiver can adapt the filtering mechanism to more closely match the behavior of an existing transmitter. As a result, the quality of the filtering is improved and the receiver can work well with a wide variety of transmitters manufactured by different manufacturers.
While this invention has been described in terms of certain preferred embodiments, it will be appreciated by those skilled in the art that certain modifications, permutations and equivalents thereof are within the inventive scope of the present invention. It is therefore intended that the following appended claims include all such modifications, permutations and equivalents as fall within the true spirit and scope of the present invention.
Claims
1. A receiver for adaptively filtering a control signal in a serial link, the receiver comprising:
- a plurality of input ports adapted to receive a plurality of data signals and a clock signal on a plurality of differential pairs at said input ports;
- a demodulator responsive to the plurality of data signals and the clock signal and operative to develop a control signal, a plurality of synchronization signals, and the clock signal;
- a content protection state machine responsive to the plurality of synchronization signals, a filtered control signal, and the clock signal;
- a filter responsive to the control signal and a filter parameter signal and operative to develop the filtered control; and
- a control machine responsive to the control signal and operative to develop the filter parameter signal, wherein the filter parameter signal is updated based on a set of characteristics of the control signal.
2. A receiver as in claim 1, wherein the content protection state machine is operative to develop an authentication signal.
3. A receiver as in claim 1, wherein the demodulator is operative to develop the plurality of data signals.
4. A receiver as in claim 1, wherein the plurality of data signals and a clock signal on a plurality of differential pairs are received from an external transmitter responsive to the authentication signal and operative to develop the plurality of data signals and the clock signal on the plurality of differential pairs.
5. A receiver as in claim 1, further comprising the transmitter.
6. A receiver as in claim 1, further comprising the transmitter in communication with the receiver.
7. A method for adaptively filtering a control signal in a serial link, the method comprising:
- receiving a plurality of data signals and a clock signal on a plurality of differential pairs;
- generating a control signal, a plurality of synchronization signals, and the clock signal;
- generating an authentication signal using a content protection state machine responsive to the plurality of synchronization signals, a filtered control signal, and the clock signal;
- generating a filtered control signal from the control signal and a filter parameter signal; and
- generating a filtered parameter signal from the control signal, wherein the filter parameter signal is updated based on a set of characteristics of the control signal.
8. A method as is claim 7, wherein the generating of the authentication signal is achieved using a content protection state machine implemented procedure.
9. A method as is claim 7, wherein the generating of the filtered parameter signal is achieved using a control machine implemented procedure.
10. A method as is claim 7, wherein the generating a control signal, a plurality of synchronization signals, and the clock signal is achieved at least in part by demodulating at least one or the plurality of data signals and the clock signal to develop the control signal, the plurality of synchronization signals, and the clock signal.
11. A method as is claim 7, wherein the generating or a filtered control signal is achieved at least in part by filtering to develop the filtered control signal from the control signal and the filter parameter signal.
12. A method as is claim 7, wherein:
- the generating of the authentication signal is achieved using a content protection state machine implemented procedure;
- the generating of the filtered parameter signal is achieved using a control machine implemented procedure;
- the generating of the control signal, the plurality of synchronization signals, and the clock signal is achieved at least in part by demodulating at least one or the plurality of data signals and the clock signal to develop the control signal, the plurality of synchronization signals, and the clock signal; and
- the generating or a filtered control signal is achieved at least in part by filtering to develop the filtered control signal from the control signal and the filter parameter signal.
13. A transmitter for use in a serial link, the transmitter being responsive to an authentication signal and operative to generate a plurality of data signals and a clock signal on a plurality of differential pairs; and, means for communicating at least some of the a plurality of data signals and a clock signal to a receiver.
Type: Application
Filed: Mar 19, 2007
Publication Date: Aug 16, 2007
Inventor: James Lyle (Santa Clara, CA)
Application Number: 11/725,738
International Classification: H04N 7/16 (20060101); H04L 9/32 (20060101); H04N 7/167 (20060101); G06F 17/30 (20060101); G06F 7/04 (20060101); G06K 9/00 (20060101); H03M 1/68 (20060101); H04K 1/00 (20060101); H04L 9/00 (20060101);