Semiconductor package having an optical device and a method of making the same
A semiconductor package having an optical device and a method of making the same, the package including a chip, an upper metal redistribution layer, a transparent insulating layer, and a lower metal redistribution layer. The chip has an active surface, a back surface, at least one through hole, an optical device, and at least one upper pad. The optical device is electrically connected to the upper pad. The through hole is filled with a metal post. An insulating layer is between the through hole wall and the metal post. The upper metal redistribution layer is on the chip active surface, and connects the upper pad and the metal post. The transparent insulating layer is on the active surface. The lower metal redistribution layer is on the back surface of the chip, and is connected to the metal post. A simplified manufacturing process having reduced cost is provided.
This is a divisional application of application Ser. No. 11/363,197, filed on Feb. 28, 2006, which is hereby incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to a semiconductor package and a method of making the same, and more particularly, to a semiconductor package having an optical device and a method of making the same.
2. Description of the Related Art
Referring to
Referring to
Therefore, it is necessary to provide a semiconductor package having an optical device and a method of making the same to solve the above problems.
SUMMARY OF THE INVENTIONThe objective of the invention is to provide a semiconductor package having an optical device and a method of making the same, which is suitable for packaging an optical device. The process of the method is simple and cost-saving.
In order to achieve the above purpose, the invention provides a method of packaging a semiconductor package having an optical device, which includes:
(a) providing a wafer having an active surface and a back surface, wherein the active surface has at least one upper pad and an optical device electrically connected to the upper pad;
(b) forming at least one hole on the active surface of the wafer;
(c) forming an insulating layer on the wall of the hole;
(d) forming an upper metal layer on the active surface of the wafer, wherein the hole is filled with the metal layer;
(e) patterning the upper metal layer to form an upper metal redistribution layer, for electrically connecting the upper pad to the metal within the hole;
(f) attaching a transparent insulating layer on the active surface of the wafer;
(g) removing a part of the back surface of the wafer for exposing the metal in the hole to the back surface of the wafer;
(h) forming a lower metal redistribution layer, which is electrically connected to the metal in the hole, on the back surface of the wafer; and
(i) sawing the wafer to form a plurality of individual semiconductor packages.
The invention further provides a semiconductor package having an optical device. The semiconductor package comprises a chip, an upper metal redistribution layer, a transparent insulating layer, and a lower metal redistribution layer. The chip has an active surface, a back surface, and at least one through hole. The active surface has at least one upper pad and an optical device electrically connected to the upper pad. The through hole is filled with a metal post and an insulating layer is disposed between the wall of the through hole and the metal post. The upper metal redistribution layer is disposed on the active surface of the chip and connects the upper pad and the metal post. The transparent insulating layer is disposed on the active surface of the wafer. The lower metal redistribution layer is disposed on the back surface of the wafer and electrically connected to the metal post.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 6 to 23 are schematic views corresponding to the steps in
Referring to
Firstly, in step S101, a wafer 30 is provided. The wafer 30 has an active surface 301, a back surface 302, and a plurality of sawing lines 305. The active surface 301 has at least one upper pad 304 and an optical device 303 thereon, wherein the optical device 303, for example, a Complementary Metal-Oxide Semiconductor (CMOS), is electrically connected to the upper pad 304. A plurality of chips 306 are defined by the sawing lines 305 as shown in
Then, in step S102, a dielectric layer 31 is formed on the active surface 301 of the wafer 30, as shown in
Then, in step S103, at least one hole 32 is formed on the active surface 301 of the wafer 30, as shown in
Then, in step S104, an insulating layer 34 is formed on the wall of the hole 32. In this embodiment, the step S104 is accomplished as follows. Firstly, a photoresist layer 33 is formed on the dielectric layer 31, as shown in
Next, in step S105, an upper metal layer 35 is formed on the dielectric layer 31 on the active surface 301 of the wafer 30. If there is no dielectric layer 31, the upper metal layer 35 is formed on the active surface 301 of the wafer 30. The hole 32 is filled with the upper metal layer 35 to form a metal post 36, as shown in
Then, in step S106, the upper metal layer 35 is patterned to form an upper metal redistribution layer (RDL) 37. The upper pad 304 is electrically connected to the metal (i.e., the metal post 36) within the hole 32 through the upper metal redistribution layer 37, as shown in
Then, in step S107, a transparent insulating layer 38 (for example, a glass layer) is attached on the dielectric layer 31 on the active surface 301 of the wafer 30 by an adhesive layer 39, as shown in
Then, in step 108, a part of the back surface 302 of the wafer 30 is removed so as to expose the metal (i.e., the metal post 36) within the hole 32 outside the back surface 302 of the wafer 30, as shown in
Then, in step S109, a compliance layer 40 is formed on the back surface 302 of the wafer 30, wherein the lower surface of the metal post 36 is not covered by the compliance layer 40, as shown in
Then, in step S10, a lower metal redistribution layer 41 is formed on the compliance layer 40 on the back surface 302 of the wafer 30, wherein the lower metal redistribution layer 41 is connected to the lower surface of the metal post 36, as shown in
Then, in step S11, a solder mask 42 is formed on the lower metal redistribution layer 41 and the compliance layer 40, as shown in
Then, step S112 is a ball mounting process. A plurality of solder balls 44 are formed on the lower pad 43, as shown in
Finally, step S113 is a sawing process. In the embodiment, a notch 45 is formed on the position corresponding to the sawing line 35 of the wafer 30 before sawing, as shown in
Referring to
The chip 306 has an active surface 301, a back surface 302 and at least one through hole 46. The active surface 301 has at least one upper pad 304 and an optical device 303 electrically connected to the upper pad 304. The through hole 46 is filled with a metal post 36, and an insulating layer 34 is disposed between the wall of the through hole 46 and the metal post 36.
The upper metal redistribution layer 37 is disposed on the active surface 301 of the chip 30 and connects the upper pad 304 and the metal post 36. Preferably, a dielectric layer 31 is disposed between the upper metal redistribution layer 37 and the active surface 301 of the wafer 30. The transparent insulating layer 38 (for example, a glass layer) is disposed on the active surface 301 of the wafer 30. Preferably, an adhesive layer 39 is disposed between the transparent insulating layer 38 and the active surface 301. The lower metal redistribution layer 41 is disposed on the back surface 302 of the wafer 30 and electrically connected to the lower surface of the metal post 36. Preferably, a compliance layer 40 is further disposed between the back surface 302 of the wafer 30 and the lower metal redistribution layer 41.
The solder mask 42 is disposed on the lower surface of the compliance layer 40 and the lower metal redistribution layer 41. The solder mask 42 has at least one opening, which defines lower pad 43 of the lower metal redistribution layer 41. The solder balls 44 are disposed on the lower pad 43.
While an embodiment of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope as defined in the appended claims.
Claims
1. A semiconductor package having an optical device, comprising:
- a chip, having an active surface, a back surface, and at least one through hole, wherein the active surface has at least one upper pad and an optical device electrically connected to the upper pad, and the through hole is filled with a metal post, and an insulating layer is disposed between the wall of the through hole and the metal post;
- an upper metal redistribution layer, disposed on the active surface of the chip, wherein the upper metal redistribution layer connects the upper pad and the metal post;
- a transparent insulating layer, disposed on the active surface of the wafer; and
- a lower metal redistribution layer, disposed on the back surface of the wafer, the lower metal redistribution layer being electrically connected to the metal post.
2. The package according to claim 1, further comprising a dielectric layer disposed between the upper metal redistribution layer and the active surface of the wafer.
3. The package according to claim 1, further comprising a compliance layer disposed between the back surface of the wafer and the lower metal redistribution layer.
4. The package according to claim 1, further comprising a solder mask disposed on the lower surface of the lower metal redistribution layer.
5. The package according to claim 4, wherein the solder mask has at least one opening by which a lower pad of the lower metal redistribution layer is defined.
6. The package according to claim 5, further comprising a plurality of solder balls disposed on the lower pad.
7. The package according to claim 1, further comprising a plurality of solder balls disposed on the lower metal redistribution layer.
Type: Application
Filed: Apr 24, 2007
Publication Date: Aug 23, 2007
Inventor: Yao-Hsin Feng (Kaoshiung)
Application Number: 11/790,150
International Classification: H01L 23/02 (20060101);