Power modelling in circuit designs
A system and method is described for generating a power model of a circuit from a lower level description, such as Gate-level or RTL. In one aspect, simulation data is converted into a series of messages or transactions. Power is then determined on a per message or per transaction basis. In another aspect, an abstract power model is generated using a neural network. The neural network generates a system of weighted equations representing an accurate power model.
Priority is claimed to U.S. provisional patent application 60/748,957, filed Dec. 8, 2005, which is hereby incorporated by reference.
FIELD OF THE INVENTIONThe present invention generally relates to simulation, and more particularly to modelling power of a simulated circuit.
BACKGROUNDThe complexity of integrated circuits (ICs) being designed nowadays is continuously increasing and has resulted in complete system-on-chip (SoC) solutions. Even more, the complexity of such integrated systems is exploding thanks to advances in process fabrication. The limiting factor is now the ability to design, manage and verify such systems rather than the ability to fabricate them.
The typical design process begins with a software program that describes the behavior or functionality of a circuit. This software program is written in a hardware description language (HDL) that defines a behavior to be performed with limited implementation details. Logic synthesis tools convert the HDL program into a gate netlist description. The RTL description is used to verify functionality and ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.
As SoC's are becoming larger, the only way to efficiently design such dense SoC's, both from the design complexity and time-to-market aspects, is by embedding Intellectual Property (IP) cores. Standards for such cores are currently evolving. Ideally, they should be reusable, pre-characterized and pre-verified. But it is often desirable to change the design to create the next generation. For example, as fabrication technology changes, it is desirable to convert or migrate the design to the new process parameters. For example, an IP core may be designed and tested for 90 nm technology, but it is desirable to convert the IP core to a new process of 60 nm technology. Or it may be desirable to update the design and incorporate changes in order to create the next generation design.
In order to test and explore such changes in the design, simulation must be performed, which is very time consuming. A few seconds of real-time simulation can take weeks or even months. If the simulation results are not desirable, then the design process must start over again by changing the high-level code and re-simulating.
Because of such delays in simulation, designers are beginning to move the design process to a higher level of abstraction (meaning less focus on design details). At the higher level of abstraction, design exploration can be performed to evaluate which performance can be achieved, which parts to use, etc. The preferable higher level of abstraction is called Transaction Level Modeling (TLM), which refers to the evolving design and verification space called Electronic System Level (ESL) with methodologies that begin at a higher level of abstraction than the current mainstream Register Transfer Level (RTL). The main ESL design language SystemC, is driven from C/C++ rather than from hardware languages like Verilog and VHDL.
Power consumption is another important aspect of design exploration. There are three main power ingredients: static, dynamic, and internal. There are a variety of techniques currently available in order to analyze power. One technique is to estimate power statistically based on gate count and technology parameters. Another technique is to estimate power based on average activity extracted from simulation. More accurate techniques for power determinations are based on netlist and place and route manipulations. In any event, there are two main power tool types on the market today: physical power solutions and ESL power solutions. Physical power solutions generally reduce power through netlist and physical manipulations. Such solutions focus on gate and interconnect levels and lack any functional or architecture-level perspective to support power management at the system level. Some ESL power solutions focus on software and algorithmic optimizations. There are some techniques that statistically characterize the power consumption of system tasks. However, the drawback is that they often assume statically scheduled systems and do not account for dynamic effects and are not accurate as data power is estimated. Other techniques are based on system simulation, with low-level power models of individual components, memories and system busses. Such techniques are computationally expensive making them unsuitable for system-level design space exploration.
SUMMARYA system and method is disclosed for generating a high-level power model of a circuit from a lower level description, such as RTL or HDL.
In one aspect, simulation data is converted into a series of messages or transactions. Power is then determined on a per message or per transaction basis.
In another aspect, an abstract power model is generated using a neural network. The neural network generates a system of weighted equations. Input patterns are used to calculate a difference between the actual output values (using the equations) and desired values (using simulated data). The weights of the equations can then be modified to obtain an accurate power model.
These features and others of the described embodiments will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
A compiler 42 compiles the design and the protocol library 44. The compiler 42 may be any desired compiler and is usually included as part of a simulator package. The protocol library 44 includes messages and transactions associated with a protocol used by the circuit. A sequence of messages form a transaction. Examples of messages include a request and an acknowledge of the bus, whereas a transaction is a complete operation, such as any of a variety of types of Read or Write transactions or control or setup transactions. A simulation kernel 46 simulates the compiled design in a well-known manner, as already described. The simulation kernel 46 outputs the simulation data 48 in any desired format. Box 48 can also represent a pre-simulated design data (VCD format).
A message recognition module 50 reads the simulation data 48 and analyzes the data to convert it to messages of the protocol stored in the protocol library 44.
A transaction recognition module 52 reads the messages determined by the message recognition module 50 and converts the messages into transactions using a comparison of a series of messages to predetermined messages within the protocol library 44. If a match is found, then the transaction recognition module stores the series of messages as a transaction. The result is that the messages are converted into a series of transactions.
A transaction sequence recognition module 54 converts multiple transactions into a single super-transaction sequence. For example, several Writes can be converted into a single control operation. This conversion from multiple transactions to a super-transaction sequence is described further below in relation to
In any event, the simulated circuit description is taken to a higher level of abstraction, as the simulation data is converted first to messages, then to transactions, and finally to transaction sequences. The transaction sequences are at a higher level of abstraction.
The compiler 42, simulator kernel 46, and modules 50, 52, 54, may all be run on the same computer. Alternatively, the circuit description may be compiled and simulated in a different location so that the resultant simulation data 48 is merely on a storage medium to be input into the message recognition module 50. In such a case, as shown at 58, it is desirable that the some of the protocol data from the protocol library 44 is incorporated into the simulation data in a pre-processing step.
In process box 264, a netlist is simulated using a simulation sequence as a testbence. For example, a VCD (Value Change Dump) sequence can be used as a testbence. The VCD sequence is a sequence of messages that are run back through the netlist including monitors in order to perform the tracing of how much power a message uses.
In process box 266, a power database is output with power data on a per message or per transaction basis. This power database is used in the learning process as the power data is passed through a neural network.
The power model is based on accumulated dynamic power and non-active (leakage) power. The formula that can be used in calculating power is: Power=message power (load+cell)+leakage power@parameters. The load is the load switching power. The cell is the cell internal switching power (short circuit). The leakage is the non-active power. The load per gate is estimated as load=(activity)*F*C*Vdd(2), where F is the clock frequency, C is the capacitance (internal gates and external wire and fan-out) and Vdd is the supply voltage.
In a place and route incremental power engine 356, the power functions generated by the neural network 354 are corrected based on back-annotated place and route information from place and route engine 328. The result is that RTL or HDL files and gate-level designs are converted to TLM equivalent models with accurate power and performance behavior. Such models can be simulated as-is to run pure performance analysis of a system, or can be plugged into TLM functional models and used to provide timing and power behavior during fully functional simulation. The power model is also hierarchical so that it can support a top-down approach where users can start with a high-level power model and gradually refine it along with implementation and the data that is available at each step downstream. One possible application includes having a power model associated with each IP core in a system. Instantaneous power of the overall system may be computed quickly. Moreover, an IP core can be removed or replaced and the affect on power may be visualized quickly.
The system described maps actual power behavior up to the message or transaction levels where it can be budgeted and managed. At these levels, optimization can be traded with performance, while maintaining a high level of accuracy and speed.
Having illustrated and described the principles of the illustrated embodiments, it will be apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles.
For example, in some systems, a full conversion to transactions is unnecessary if only messages are to be used.
In view of the many possible embodiments, it will be recognized that the illustrated embodiments include only examples of the invention and should not be taken as a limitation on the scope of the invention. Rather, the invention is defined by the following claims. We therefore claim as the invention all such embodiments that come within the scope of these claims.
Claims
1. A method for analyzing power of a circuit design, comprising:
- receiving simulation data of the circuit design;
- converting the simulation data into a series of messages or transactions; and
- using the simulation data, determining power in the circuit design on a per message or per transaction basis.
2. The method of any of claim 1, further including learning the power behavior using the determined power and generating a power model of the circuit including equations representing the power used by the circuit on a per message or per transaction basis.
3. The method of claim 1, wherein converting simulation data includes analyzing two or more switching signals on simulated hardware lines;
- comparing the switching signals to known patterns of messages in a protocol; and
- determining a match between the switching signals and a message in the protocol.
4. The method of claim 1, wherein determining transactions includes:
- comparing a sequence of messages to known transactions, which include sequences of messages of the protocol; and
- determining a match between the sequence of messages obtained from the simulation data and a transaction.
5. The method of claim 1, wherein determining power includes:
- extracting power by tracing how a message affects gates of the circuit; and
- for each gate affected, associating the message with the power used in that gate.
6. The method of claim 1, further including calculating power in a message by adding the power of each gate affected by the message.
7. The method of claim 1, further including calculating power in a transaction by adding the power of each message comprised in the transaction.
8. The method of claim 1, further including generating an abstract model including a system of equations that represent the power on a per message or per transaction basis.
9. The method of claim 8, wherein generating an abstract model includes learning the circuit using neural networks or any other machine learning or statistical algorithm.
10. The method of claim 9, wherein learning includes:
- generating a system of weighted equations representing the power of the circuit on a per message or per transaction basis;
- applying input patterns to the system of equations to generate actual output values;
- calculating an error by using a difference between the actual values and desired values;
- modifying the weightings in the system of equations based on the calculated error.
11. The method of claim 8, wherein the circuit description is in a register transfer level and the abstract model is a transaction-level model having a different level of abstraction than the register transfer level.
12. The method of claim 1, wherein at least part of the method is performed on a client computer coupled to a network and part of the method is performed on a server computer coupled to the network.
13. A computer-readable medium including instructions stored thereon for performing the method of claim 1.
14. An apparatus to model power in a circuit, comprising:
- a power extraction engine to determine power used on a per message or per transaction basis using simulation data; and
- a neural network coupled to the power extraction engine and using the power determined to generate an abstract power model of the circuit.
15. The apparatus of claim 14, further including a technology library coupled to the power extraction engine, the technology library including information regarding power consumption of gates within the circuit.
16. The apparatus of claim 14, wherein part of the apparatus is located on a client computer and another part is located on a server computer.
17. The apparatus of claim 14, wherein the abstract model is in an electronic-system-level model.
18. The apparatus of claim 14, further including a place and route incremental power engine coupled to the neural network.
19. An apparatus to model power in a circuit, comprising:
- means for receiving simulation data of the circuit design;
- means for converting the simulation data into a series of messages or transactions; and
- means for generating a power model that determines power in the circuit design on a per message or per transaction basis.
20. The apparatus of claim 19, further including means for back annotating power based on place and route information.
21. The apparatus of claim 19, further including simulation means coupled to the means for converting.
Type: Application
Filed: Jun 11, 2007
Publication Date: Nov 29, 2007
Inventors: Yossi Veller (Herzliya), Vasile Hanga (Netanya), Alexander Rozenman (Rishon Lezion), Rami Rachamim (Tel Aviv)
Application Number: 11/811,680
International Classification: G06F 17/50 (20060101);