SEQUENTIAL MEMORY AND ACCESSING METHOD THEREOF
A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the nth transistor are respectively transformed into a source voltage and a drain voltage in an nth reading period, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mth transistor are respectively transformed into the source voltage and the drain voltage in an mth reading period. The source voltage equals the ground voltage.
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1. Field of the Invention
The invention relates in general to a sequential memory and an accessing method thereof, and more particularly to a sequential memory and an accessing method thereof capable of saving the operation time and reducing the operation power.
2. Description of the Related Art
Memories have been currently used in the field of data storage widely. The memory has a plurality of memory cells disposed in an array usually. Each row of memory cells corresponds to one word line, and each column of memory cells corresponds to one bit line. Each memory cell includes a transistor, which has a first terminal coupled to a bit line, a second terminal coupled to another bit line, and a control terminal coupled to a corresponding word line.
The conventional memory operates in several steps, which usually include a charge step, a sense step and a discharge step. The discharge step is very important. If no discharge step is performed to clear the residual charges in the previous access period, initial voltages of the first terminal and the second terminal of the transistor may be different from each other in the current access period. In addition, the memory cell may have the residual charges after being read or programmed, thereby causing the leakage current or other unpredictable errors.
When the data stored in the nth memory cell is read, that is, in the nth reading period Tn, a bit line timing control bl_clk of a bit line corresponding to the nth memory cell has a low level voltage between the time instants t0 and t1 and the nth memory cell does not operate, and then has a high level voltage between the time instants t1 and t4, and the nth memory cell is being accessed.
In the charge period from the time instants t1 to t2, the bit line (drain side) of the nth memory cell is charged, and the voltage level of the charge pulse “charge” is transformed into the high level voltage. Next, in the sense period from the time instants t2 to t3, the nth memory cell is sensed (data evaluation), and the voltage level of a sense pulse sa_en is transformed into the high level voltage. Thereafter, in the discharge period from the time instants t3 to t4, the bit line of the nth memory cell is discharged, and the voltage level of a discharge pulse “discharge” is transformed into the high level voltage.
In addition, when the conventional memory is operating, it is also possible to perform the discharge operation followed by the charge and sense operations. If one row of memories has m memory cells, m discharge periods are required to read/program the row of memories. When the memory is being verified and if the verification error occurs, the m discharge periods have to be spent to read or program the memories again, thereby wasting a lot of time and disabling the memories from operating at the high speed. In the meanwhile the memory operation power consumption raises substantially.
In addition, when the number of memory cells corresponding to the same bit line increases, the overall capacitance of the bit line also increases. Consequently, the discharge period (i.e., the time instants t3 to t4 in
It is therefore an object of the invention to provide a sequential memory and an accessing method thereof, wherein the smart method prevents the discharge period from being spent in the access period when the memory cells in the sequential memory are accessed, the memory can operate at a high speed, the operation time can be shortened, and the operation power can be reduced.
The invention achieves the above-identified object by providing a method of sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. The at least one row of transistors includes m transistors, the xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m. The method includes the following steps. First, voltage levels of the first terminals and the second terminals of the transistors are equalized to a ground voltage in apre-discharge period. Next, the voltage level of the first terminal of the nth transistor is transformed into a source voltage, the voltage level of the second terminal of the nth transistor is transformed into a drain voltage, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage in an nth reading period, wherein n is a positive integer smaller than m. Then, the voltage level of the first terminal of the mth transistor is transformed into the source voltage, and the voltage level of the second terminal of the mth transistor is transformed into the drain voltage in an mth reading period. The source voltage is equal to the ground voltage.
The invention also achieves the above-identified object by providing a sequential memory including (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. The row of memory cells has m memory cells, each of which has a transistor. The xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m. Voltage levels of the first terminals and the second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. The voltage level of the first terminal of the nth transistor is transformed into a source voltage, the voltage level of the second terminal of the nth transistor is transformed into a drain voltage, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage in an nth reading period, wherein n is a positive integer smaller than m. The voltage level of the first terminal of the mth transistor is transformed into the source voltage, and the voltage level of the second terminal of the mth transistor is transformed into the drain voltage in an mth reading period. The source voltage is equal to the ground voltage.
The invention also achieves the above-identified object by providing a method for sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. The at least one row of transistors has m transistors. The xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m. The method includes the following steps. First, voltage levels of the first terminals and the second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage level of the second terminal of the (m−n+1)th transistor is transformed into a source voltage, the voltage level of the first terminal of the (m−n+1)th transistor is transformed into a drain voltage, and the voltage level of the first terminal of the (m−n)th transistor is transformed into an isolation voltage in an nth program period, wherein n is a positive integer smaller than m. The voltage level of the second terminal of the first transistor is transformed into the source voltage and the voltage level of the first terminal of the first transistor is transformed into the drain voltage in an mth program period. The source voltage is equal to the ground voltage.
The invention also achieves the above-identified object by providing a sequential memory including (m+1) bit lines and at least one row of memory cells, wherein m is a positive integer. The at least one row of memory cells has m memory cells, each of which has a transistor. A first terminal of the xth transistor is coupled to the xth bit line, a second terminal of the xth transistor is coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m. Voltage levels of the first terminals and the second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. The voltage level of the second terminal of the (m−n+1)th transistor is transformed into a source voltage, the voltage level of the first terminal of the (m−n+1)th transistor is transformed into a drain voltage, and the voltage level of the first terminal of the (m−n)th transistor is transformed into an isolation voltage in an nth program period, wherein n is a positive integer smaller than m. The voltage level of the second terminal of the first transistor is transformed into the source voltage, and the voltage level of the first terminal of the first transistor is transformed into the drain voltage in an mth reading period. The source voltage is equal to the ground voltage.
The invention also achieves the above-identified object by providing a method for sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. The at least one row of transistors comprises m transistors. The xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m. The xth transistor has a first bit and a second bit. The method includes the following steps. First, voltage levels of the first terminals and the second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage level of the first terminal of the nth transistor is transformed into a source voltage, the voltage level of the second terminal of the nth transistor is transformed into a drain voltage, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage in an nth reading period, wherein n is a positive integer smaller than m. The voltage level of the first terminal of the mth transistor is transformed into the source voltage, and the voltage level of the second terminal of the mth transistor is transformed into the drain voltage in an mth reading period. Then voltage levels of the first terminals and the second terminals of the transistors are equalized to the ground voltage in a middle-discharge period. Afterwards the voltage level of the second terminal of the (m−n+1)th transistor is transformed into the source voltage, the voltage level of the first terminal of the (m−n+1)th transistor is transformed into the drain voltage, and the voltage level of the first terminal of the (m−n)th transistor is transformed into the isolation voltage in an nth inverse reading period. Next, the voltage level of the second terminal of the first transistor is transformed into the source voltage and the voltage level of the first terminal of the first transistor is transformed into the drain voltage in an mth inverse reading period. The source voltage is equal to the ground voltage.
The invention also achieves the above-identified object by providing a method for sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. The at least one row of transistors comprises m transistors. The xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m. The xth transistor has a first bit and a second bit. The method includes the following steps. First, voltage levels of the first terminals and the second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage level of the second terminal of the (m−n+1)th transistor is transformed into a source voltage, the voltage level of the first terminal of the (m−n+1)th transistor is transformed into a drain voltage, and the voltage level of the first terminal of the (m−n)th transistor is transformed into an isolation voltage in an nth program period. The voltage level of the second terminal of the first transistor is transformed into the source voltage and the voltage level of the first terminal of the first transistor is transformed into the drain voltage in an mth program period, wherein n is a positive integer smaller than m. Afterwards voltage levels of the first terminals and the second terminals of the transistors are equalized to the ground voltage in a middle-discharge period. Then the voltage level of the first terminal of the nth transistor is transformed into the source voltage, the voltage level of the second terminal of the nth transistor is transformed into the drain voltage, and the voltage level of the second terminal of the (n+1)th transistor is transformed into the isolation voltage in an nth inverse program period. The voltage level of the first terminal of the mth transistor is transformed into the source voltage, and the voltage level of the second terminal of the mth transistor is transformed into the drain voltage in an mth inverse program period. The source voltage is equal to the ground voltage.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
The invention provides a sequential memory and an accessing method thereof capable of preventing the discharge period from being spent in the access period when the memory cells in the sequential memory are accessed. Thus, the memory can operate at a high speed, the operation time can be shortened, and the operation power can be reduced.
Next, step 304 transforms the voltage level of the first terminal of the nth transistor into a source voltage S and the voltage level of the second terminal of the nth transistor into a drain voltage D, and transforms the voltage level of the second terminal of the (n+1)th transistor into an isolation voltage ISO in the nth reading period, wherein n is a positive integer smaller than m. As correspondingly shown in
Similarly, the voltage level of the first terminal of the transistor of the memory cell 20n is transformed into the source voltage S in the nth reading period, the voltage level of the second terminal of the transistor of the memory cell 20n is transformed into the drain voltage D, and the voltage level of the second terminal of the transistor of the memory cell 20(n+1) is transformed into the isolation voltage ISO. The source voltage S is substantially equal to the ground voltage GND, so the voltage level of the first terminal of the transistor of the memory cell 20n is equql to the ground voltage GND in the (n+1)th reading period, such that the residual charges are cleared without performing the discharge step.
In addition, step 304 transforms the voltage levels of the first terminal and the second terminal of the nth transistor into the voltage levels for substantially reading the data stored in the nth transistor (memory cell 20n). The isolation voltage substantially approximates the drain voltage D. The nth transistor (memory cell 20n) is isolated from the (n+2)th transistor (memory cell 20(n+2)) through the (n+1)th transistor (memory cell 20(n+1)), thereby solving the problem of the leakage current.
Then, step 306 transforms the voltage level of the first terminal of the mth transistor into the source voltage S and the voltage level of the second terminal of the mth transistor into the drain voltage D in the mth reading period. As correspondingly shown in
As correspondingly shown in
Besides, if each of the transistors of the memory cells 201˜20m has a first bit and a second bit, the transistor can read the two bits by the method this invention disclosed.
Step 508 equalizes voltage levels of the first terminals and the second terminals of the transistors to the ground voltage GND in the middle-discharge period (i.e., after all first bits of the memory cells have been read). Then step 510 transforms the voltage level of the second terminal of the (m−n+1)th transistor into the source voltage S and the voltage level of the first terminal of the (m−n+1)th transistor into the drain voltage D, and transforms the voltage level of the first terminal of the (m−n)th transistor into the isolation voltage ISO in the nth inverse reading period, wherein n is a positive integer smaller than m. As shown in
Similarly, the voltage level of the second terminal of the transistor of the memory cell 20(m−n+1) is transformed into the source voltage S, the voltage level of the first terminal of the transistor of the memory cell 20(m−n+1) is transformed into the drain voltage D, and the voltage level of the first terminal of the transistor of the memory cell 20(m−n) is transformed into the isolation voltage ISO in the nth inverse reading period. Then, step 512 transforms the voltage level of the second terminal of the first transistor into the source voltage S and the voltage level of the first terminal of the first transistor into the drain voltage D in the mth inverse reading period. As correspondingly shown in
As correspondingly shown in
Next, step 704 transforms the voltage level of the second terminal of the (m−n+1)th transistor into the source voltage S and the voltage level of the first terminal of the (m−n+1)th transistor into the drain voltage D, and transforms the voltage level of the first terminal of the (m−n)th transistor into the isolation voltage ISO in the nth program period, wherein n is a positive integer smaller than m. As shown in
Similarly, the voltage level of the second terminal of the transistor of the memory cell 20(m−n+1) is transformed into the source voltage S, the voltage level of the first terminal of the transistor of the memory cell 20(m−n+1) is transformed into the drain voltage D, and the voltage level of the first terminal of the transistor of the memory cell 20(m−n) is transformed into the isolation voltage ISO in the nth program period. The source voltage S is substantially equal to the ground voltage GND, so the residual charges can be cleared without performing the discharge step.
In addition, step 704 transforms the voltage levels of the first terminal and the second terminal of the (m−n+1)th transistor into the voltage levels for substantially programming the (m−n+1)th transistor (memory cell 20(m−n+1)). The isolation voltage GND substantially approximates the drain voltage D. The (m−n+1)th transistor (memory cell 20(m−n+1)) is isolated from the (m−n−1)th transistor (memory cell 20(m−n−1)) through the (m−n)th transistor (memory cell 20(m−n)), and the problem of the leakage current is thus solved.
Then, step 706 transforms the voltage level of the second terminal of the first transistor into the source voltage S and the voltage level of the first terminal of the first transistor into the drain voltage D in the mth program period. As correspondingly shown in
As correspondingly shown in
Then, the memory cell 20n is charged and the voltage level of the charge pulse “charge” is transformed into the high level voltage in the charge period between the time instants t1 and t2. Next, the memory cell 20n is sensed in the sense period between the time instants t2 and t3, wherein the voltage level of the sense pulse sa_en is transformed into the high level voltage. Obviously, compared with the prior art method, the discharge period is saved.
In addition, if all the memory cells are to be programmed in dual bits, similar to that shown in
In the sequential memory and the accessing method thereof according to the embodiment of the invention, no discharge period will be spent in the access period when the memory cells of the sequential memory are being accessed, and only one discharge period is spent in the access process. Thus, the operation time is greatly saved, the memory can operate at the high speed and the operation power can be reduced.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims
1. A method for sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer, the at least one row of transistors comprises m transistors, the xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m, the method comprising the steps of:
- equalizing voltage levels of the first terminals and the second terminals of the transistors to a ground voltage in a pre-discharge period;
- transforming the voltage level of the first terminal of the nth transistor into a source voltage, transforming the voltage level of the second terminal of the nth transistor into a drain voltage, and transforming the voltage level of the second terminal of the (n+1)th transistor into an isolation voltage in an nth reading period, wherein n is a positive integer smaller than m; and
- transforming the voltage level of the first terminal of the mth transistor into the source voltage, and transforming the voltage level of the second terminal of the mth transistor into the drain voltage in an mth reading period,
- wherein the source voltage is equal to the ground voltage.
2. The method according to claim 1, wherein the step of transforming the voltage levels of the first terminal and the second terminal of the nth transistor in the nth reading period reads data stored in the nth transistor.
3. The method according to claim 1, wherein the isolation voltage approximates the drain voltage such that the nth transistor is isolated from the (n+2)th transistor through the (n+1)th transistor.
4. The method according to claim 1, further comprising the step of:
- transforming the voltage level of the second terminal of the mth transistor into the ground voltage in a discharge period.
5. A sequential memory, comprising:
- (m+1) bit lines, wherein m is a positive integer; and
- at least one row of memory cells having m memory cells, each of which has a transistor, wherein the xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m, wherein:
- voltage levels of the first terminals and the second terminals of the transistors equal a ground voltage in a pre-discharge period;
- the voltage level of the first terminal of the nth transistor is transformed into a source voltage, the voltage level of the second terminal of the nth transistor is transformed into a drain voltage, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage in an nth reading period, wherein n is a positive integer smaller than m;
- the voltage level of the first terminal of the mth transistor is transformed into the source voltage, and the voltage level of the second terminal of the mth transistor is transformed into the drain voltage in an mth reading period; and
- the source voltage is equal to the ground voltage.
6. The memory according to claim 5, wherein the transistors are floating gate field effect transistors.
7. The memory according to claim 5, wherein data stored in the nth memory cell is read in the nth reading period.
8. The memory according to claim 5, wherein the isolation voltage approximates the drain voltage such that the nth transistor is isolated from the (n+2)th transistor through the (n+1)th transistor.
9. The memory according to claim 5, wherein the voltage level of the second terminal of the mth transistor is transformed into the ground voltage in a discharge period.
10. A method for sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer, the at least one row of transistors has m transistors, the xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m, the method comprising the steps of:
- equalizing voltage levels of the first terminals and the second terminals of the transistors to a ground voltage in a pre-discharge period;
- transforming the voltage level of the second terminal of the (m−n+1)th transistor into a source voltage, transforming the voltage level of the first terminal of the (m−n+1)th transistor into a drain voltage, and transforming the voltage level of the first terminal of the (m−n)th transistor into an isolation voltage in an nth program period, wherein n is a positive integer smaller than m; and
- transforming the voltage level of the second terminal of the first transistor into the source voltage and transforming the voltage level of the first terminal of the first transistor into the drain voltage in an mth program period,
- wherein, the source voltage is equal to the ground voltage.
11. The method according to claim 10, wherein the step of transforming the voltage levels of the first terminal and the second terminal of the (m−n+1)th transistor in the nth program period programs the (m−n+1)th transistor.
12. The method according to claim 10, wherein the isolation voltage approximates the drain voltage such that the (m−n+1)th transistor is isolated from the (m−n−1)th transistor through the (m−n)th transistor.
13. The method according to claim 10, further comprising the step of:
- transforming the voltage level of the first terminal of the first transistor into the ground voltage in a discharge period.
14. A sequential memory, comprising:
- (m+1) bit lines, wherein m is a positive integer; and
- at least one row of memory cells having m memory cells, each of which has a transistor, wherein a first terminal of the xth transistor is coupled to the xth bit line, a second terminal of the xth transistor is coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m, wherein:
- voltage levels of the first terminals and the second terminals of the transistors equal a ground voltage in a pre-discharge period;
- the voltage level of the second terminal of the (m−n+1)th transistor is transformed into a source voltage, the voltage level of the first terminal of the (m−n+1)th transistor is transformed into a drain voltage, and the voltage level of the first terminal of the (m−n)th transistor is transformed into an isolation voltage in an nth program period, wherein n is a positive integer smaller than m;
- the voltage level of the second terminal of the first transistor is transformed into the source voltage, and the voltage level of the first terminal of the first transistor is transformed into the drain voltage in an mth reading period; and
- the source voltage is equal to the ground voltage.
15. The memory according to claim 14, wherein the transistors are floating gate field effect transistors.
16. The memory according to claim 14, wherein the (m−n+1)th memory cell is programmed in the nthprogram period.
17. The memory according to claim 14, wherein the isolation voltage approximates the drain voltage such that the (m−n+1)th transistor is isolated from the (m−n−1)th transistor through the (m−n)th transistor.
18. The memory according to claim 14, wherein the voltage level of the first terminal of the first transistor is transformed into the ground voltage in a discharge period.
19. A method for sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer, the at least one row of transistors comprises m transistors, the xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m, the xth transistor has a first bit and a second bit, the method comprising the steps of:
- equalizing voltage levels of the first terminals and the second terminals of the transistors to a ground voltage in a pre-discharge period;
- transforming the voltage level of the first terminal of the nth transistor into a source voltage, transforming the voltage level of the second terminal of the nth transistor into a drain voltage, and transforming the voltage level of the second terminal of the (n+1)th transistor into an isolation voltage in an nth reading period, wherein n is a positive integer smaller than m;
- transforming the voltage level of the first terminal of the mth transistor into the source voltage, and transforming the voltage level of the second terminal of the mth transistor into the drain voltage in an mth reading period;
- equalizing voltage levels of the first terminals and the second terminals of the transistors to the ground voltage in a middle-discharge period;
- transforming the voltage level of the second terminal of the (m−n+1)th transistor into the source voltage, transforming the voltage level of the first terminal of the (m−n+1)th transistor into the drain voltage, and transforming the voltage level of the first terminal of the (m−n)th transistor into the isolation voltage in an nth inverse reading period; and
- transforming the voltage level of the second terminal of the first transistor into the source voltage and transforming the voltage level of the first terminal of the first transistor into the drain voltage in an mth inverse reading period;
- wherein, the source voltage is equal to the ground voltage.
20. The method according to claim 19, wherein the step of transforming the voltage levels of the first terminal and the second terminal of the nth transistor in the nth reading period reads data stored in the first bit of the nth transistor.
21. The method according to claim 19, wherein the step of transforming the voltage levels of the first terminal and the second terminal of the (m−n+1)th transistor in the nth inverse reading period reads data stored in the second bit of the (m−n+1)th transistor.
22. The method according to claim 19, wherein the isolation voltage approximates the drain voltage such that the nth transistor is isolated from the (n+2)th transistor through the (n+1)th transistor.
23. The method according to claim 19, wherein the isolation voltage approximates the drain voltage such that the (m−n+1)th transistor is isolated from the (m−n−1)th transistor through the (m−n)th transistor.
24. The method according to claim 1, further comprising the step of:
- transforming the voltage level of the first terminal of the first transistor into the ground voltage in a discharge period.
25. A method for sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer, the at least one row of transistors comprises m transistors, the xth transistor has a first terminal coupled to the xth bit line and a second terminal coupled to the (x+1)th bit line, and x is a positive integer smaller than or equal to m, the xth transistor has a first bit and a second bit, the method comprising the steps of:
- equalizing voltage levels of the first terminals and the second terminals of the transistors to a ground voltage in a pre-discharge period;
- transforming the voltage level of the second terminal of the (m−n+1)th transistor into a source voltage, transforming the voltage level of the first terminal of the (m−n+1)th transistor into a drain voltage, and transforming the voltage level of the first terminal of the (m−n)th transistor into an isolation voltage in an nth program period;
- transforming the voltage level of the second terminal of the first transistor into the source voltage and transforming the voltage level of the first terminal of the first transistor into the drain voltage in an mth program period, wherein n is a positive integer smaller than m;
- equalizing voltage levels of the first terminals and the second terminals of the transistors to the ground voltage in a middle-discharge period;
- transforming the voltage level of the first terminal of the nth transistor into the source voltage, transforming the voltage level of the second terminal of the nth transistor into the drain voltage, and transforming the voltage level of the second terminal of the (n+1)th transistor into the isolation voltage in an nth inverse program period; and
- transforming the voltage level of the first terminal of the mth transistor into the source voltage, and transforming the voltage level of the second terminal of the mth transistor into the drain voltage in an mth inverse program period;
- wherein, the source voltage is equal to the ground voltage.
26. The method according to claim 25, wherein the step of transforming the voltage levels of the first terminal and the second terminal of the (m−n+1)th transistor in the nth program period programs the first bit of the (m−n+1)th transistor.
27. The method according to claim 25, wherein the step of transforming the voltage levels of the first terminal and the second terminal of the nth transistor in the nth inverse program period programs the second bit of the nth transistor.
28. The method according to claim 19, wherein the isolation voltage approximates the drain voltage such that the nth transistor is isolated from the (n+2)th transistor through the (n+1)th transistor.
29. The method according to claim 19, wherein the isolation voltage approximates the drain voltage such that the (m−n+1)th transistor is isolated from the (m−n−1)th transistor through the (m−n)th transistor.
30. The method according to claim 1, further comprising the step of:
- transforming the voltage level of the second terminal of the mth transistor into the ground voltage in a discharge period.
Type: Application
Filed: Dec 27, 2006
Publication Date: Jul 3, 2008
Applicant:
Inventors: Chang-Ting Chen (Hsinchu), Chung-Kuang Chen (Taipei)
Application Number: 11/645,708