Data transmission unit for high bit-rate signals, especially high bit-rate optical data signals greater than 1 gbit/s

Abstract

The invention relates to a data transmission unit for high bit-rate optical data signals, in particular, high bit-rate optical data signals with a backplane (3), which has a line structure connecting several (n) plug-in positions (5, 7, 9) for several (m) receiver or transceiver cards (11, 13, 15) to each other and/or to one or more additional data processing cards, with several receiver or transceiver cards (11, 13, 15), which are each held in one of the plug-in positions (5, 7, 9) and which each have at least one input port (11b, 13b, 15b) for a high bit-rate data signal. According to the invention, each of the receiver or transceiver cards has at least one output port, to which the relevant one or more high bit-rate data signals can be fed, and each of these output ports (5b, 7b, 9b) is connected via a serial data line (29, 31, 33) between the plug-in position (5, 7, 9) holding the relevant receiver or transceiver card (11, 13, 15) and an input port (23a) of a central selection unit (23) with the relevant input port (23a). In addition, each of these output ports is connected by means of a serial data line between the plug-in position holding the relevant receiver or transceiver card to the relevant input port, wherein the central selection unit (23) has an output port (23b) to which one of the high bit-rate data signals can be fed in a controllable way.

Description

The invention relates to a data transmission unit for high bit-rate data signals, especially high bit-rate optical data signals greater than 1 Gbit/s, with the features of the preamble of claim 1. In addition, the invention relates to a receiver or transceiver card for such a data transmission unit according to claim 8.

In electrical and optical data networks, data errors sometimes occur. When such problems are identified, the data transmission unit realizing a network node or terminating a transmission path must be tested. Here, the testing is performed by conventional protocol testers, which must be connected to the relevant data transmission unit, in particular, the receiver or transceiver units, which can be constructed as receiver or transceiver cards.

In known data transmission units, when such a test is performed, the data traffic frequently must be interrupted, because the test device must be connected to a port that is typically connected for further processing of the high bit-rate data signal by means of downstream electronics.

Therefore, a “service time window,” in which the relevant data traffic is shut down, must be provided by the operator of a data transmission network or a data transmission path. This usually takes place on the weekend and causes high administrative expense. In this “service time window,” the connection of the test device, the measurement, and the disconnection of the test device can then be performed.

In addition, there is the possibility of allowing the test equipment to also be connected during operation after its installation within a “service time window” and to disconnect the test equipment again when the error leading to the negative effect on the data transmission quality is found. For this purpose, a “service time window” must be created and used again.

In the case of an optical transmission path or an optical data transmission network, it is further known to integrate, for example, at the reception location, an optical splitter into the optical transmission path, wherein test equipment can be connected to the free arm of the splitter. This has the disadvantage, however, that an operator of a network or a data transmission path must already have invested in providing such splitters when the system is set up, and these splitters may never be needed. In addition, such a splitter has the disadvantage of corresponding insertion attenuation in the transmission path.

Finally, it is known to perform electrical mirroring of a high bit-rate data signal on a still free terminal of an interface, for example, a receiver or transceiver card, that is, the identical high bit-rate data signal that was received and optionally prepared with respect to the clock and the signal form is fed to this free terminal or output port of an interface.

In this known solution, the test device can be connected at arbitrary times to the relevant free terminal or output port of the appropriate interface. In this case, interrupting the data traffic is not necessary.

Here, however, it is disadvantageous that a data transmission device for realizing a network node or an end point of a transmission path frequently has a backplane, which possesses several plug-in positions for holding interface cards, for example, receiver or transceiver cards. In the way described above, if a “test output part” is provided on each interface, then each input port of the test device must be connected directly to the relevant free terminal of each interface, wherein testing a plurality of high bit-rate data signals on various interface cards is associated with high costs.

Starting from this state of the art, the invention is based on the task of creating a data transmission unit for high bit-rate data signals, in particular, high bit-rate optical data signals, with a backplane and several plug-in positions for holding several interface cards, in which a simple connection of test equipment for testing the high bit-rate signals is possible. In addition, the invention is based on the task of creating a receiver or transceiver card that can be used for such a data transmission unit.

The invention emerges from the knowledge that the expense for performing tests for the high bit-rate data signals can be dramatically reduced if one of the high bit-rate data signals that are fed to the receiver or transceiver cards is passed transparently to a single output port. Each receiver or transceiver card has at least one output port to which the high bit-rate data signal or one of the high bit-rate data signals can be fed, wherein these signals are fed to the relevant receiver or transceiver card. There is a high-speed connection line between these output ports or between the relevant pins of the plug-in positions in which the receiver or transceiver cards are located and an input port of a central selection unit. The selection unit is here constructed so that, in a controlled way, it transparently passes the high bit-rate signal fed to one of its input ports to a single output port. Thus it is possible to also feed high bit-rate electrical data signals in a controllable (and selectable) way from several receiver or transceiver cards each via a signal path to the backplane of a selection unit, wherein this unit advantageously passes one of the high bit-rate data signals transparently to an output port.

Here, a receiver or transceiver card can have only a single input port, to which a (single) high bit-rate (receive) data signal is fed. Obviously, however, a receiver or transceiver card can also have several input ports, wherein each one of the high bit-rate data signals fed to these input ports is fed to an associated output port. In this case, each of the several output ports is connected to an input port of the central selection unit via connection lines between the relevant pin of the plug-in position in which the receiver or transceiver card is held.

Finally, a receiver or transceiver card can also have several input ports and only one output port, wherein, here, one or the received high bit-rate data signals can be fed to the single output port in a controllable way.

A (receive) data signal can be fed to a corresponding output port in a known way by “mirroring” the relevant electrical signal.

According to one implementation of the invention, the one or more high bit-rate data signals fed to one of the receiver or transceiver cards can be an optical data signal. In this case, a unit for the optoelectrical conversion of the high bit-rate data signal is connected downstream of each receive port of the receiver or transceiver card.

According to the invention, the selection unit can be either arranged fixed on the backplane or provided similarly on an interface card that is held in a plug-in position.

The central selection unit can also comprise a signal processing circuit which compensates for negative effects on the signal in the transmission of the relevant signal between the output port of the relevant receiver or transceiver card and the relevant input port of the selection unit.

In addition, the selection unit can be integrated with a signal processing unit, which can perform, for example, a protocol test with respect to the signal fed to it or some other kind of test on the signal.

According to one construction of the invention, the central selection unit can be constructed as a switch.

According to one preferred embodiment of the invention, the output ports of the receiver or transceiver cards and/or the input ports and/or the output port of the central selection unit can be formed by high-speed interfaces of a field programmable gate array (FPGA). In this way, it is possible also advantageously to switch through high bit-rate signals of at least 1 Gbit/s transparently via the backplane to the output of the selection unit.

A corresponding FPGA can simultaneously also perform the mirroring of each electrical signal to the output port of a receiver or transceiver card. Such an FPGA can obviously also perform additional or practically all of the processing steps realized on a receiver or transceiver card, so that the FPGA is practically the only essentially active component on such a card.

Additional embodiments of the invention result from the subordinate claims.

The invention will be explained below with reference to an embodiment shown in the drawing.

The single FIGURE shows a schematic block diagram of a data transmission unit according to the invention.

The data transmission unit 1 shown in the FIGURE comprises a backplane 3, which can be constructed, for example, as a printed-circuit board. On the backplane 3 there are several plug-in positions 5, 7, and 9 each for a receiver or transceiver card 11, 13, 15.

Each plug-in position 5, 7, 9 can be realized by a plug-in bar 5a, 7a, 9a, in which a plug-in contact region 11a, 13a, 15a of the relevant receiver or transceiver card 11, 13, 15 is held.

Each receiver or transceiver card 11, 13, 15 has, in the embodiment shown in the single FIGURE, two input ports 11b, 13b, 15b, to each of which a high bit-rate signal is fed. The high bit-rate signals can be fed electrically or in the form of optical signals, wherein, in this case, an optical waveguide is connected to the relevant input port 11b, 13b, 15b.

On each receiver or transceiver card, an FPGA 17, 19, 21 is provided, by which means essentially all of the necessary steps for signal processing and signal processing are realized on the corresponding receiver or transceiver card 11, 13, 15.

In the shown embodiment, the FPGAs 17, 19, 21 take over, among other things, the function of mirroring one of the high bit-rate data signals received on the input port 11b, 13b, 15b (optionally after optoelectrical conversion) to an output port 11c, 13c, 15c of the receiver or transceiver cards 11, 13, 15. For this (controllable) mirroring function, absolutely no interruption of the transmission path is necessary.

Because the output ports 11c, 13c, 15c are each connected to the relevant connection pin of the corresponding plug-in bar 5a, 7a, 9a, the relevant mirrored, high bit-rate data signal can be fed by means of each serial connection line 29, 31, 33 to an input port 23a of a central selection unit 23. The central selection unit 23 is similarly held in a plug-in position 25, which is realized by a plug-in bar 25a.

The central selection unit 23 is constructed in the shown embodiment as a standalone interface card. However, this can also be obviously integrated rigidly onto the backplane 3.

The central selection unit 23 can similarly have an FPGA 27, which takes over practically all of the processing steps required on the interface card or in the central selection unit 23 for the supplied high bit-rate data signals. In particular, by means of this FPGA, a high-speed interface can be realized for each data signal fed to an input port 23a.

The serial connection lines 29, 31, 33 can each be realized in a known way by means of two lines, over which the relevant high bit-rate data signal is transmitted as a differential signal.

The central selection unit 23 switches, in a controlled way, one of the high bit-rate data signals fed to an input port 23a to an output port 23b. The output port 23b can be connected, as shown in the FIGURE, to an output port 35 of the backplane 3. This output port 35 is then used for connecting test equipment, for example, a protocol tester (not shown).

As already mentioned, the passing one of the high bit-rate data signals supplied to an input port 23a to the output port 23b is performed advantageously transparently, so that on the output port 35 a data signal is applied that is identical (with respect to its data) to the high bit-rate data signals received at one of the input ports 11b, 13b, 15b.

In the shown embodiment, the FPGA 17, 19, 21 of the receiver or transceiver card 11, 13, 15 mirrors one of the high bit-rate data signals received on one of the input ports 11b, 13b, 15b in a controllable (and selectable) way to the relevant output port 11c, 13c, 15c. One of these mirrored electrical signals can then be switched through by means of the central selection unit 23, which can also be realized as a switch, to the output port 35 of the backplane 3.

Obviously, (not shown) control signals, which are fed to the central selection unit 23 or to the receiver or transceiver cards 11, 13, 15, can be fed to the backplane 3 shown in the FIGURE. Through a corresponding evaluation of these control signals by the FPGA 17, 19, 21, or 27 then each selected input port 11b, 13b, 15b is switched through to the output port 11c, 13c, 15c or the relevant input port 23a to the output port 23b.

The central selection unit 23 or the FPGA 27 advantageously comprises a signal processing circuit (not shown), which processes the high bit-rate data signals fed to the input port 23a, in particular, in order to compensate for negative effects on these signals during transmission via the serial connection lines 29, 31, 23.

Here, such a circuit for signal processing can be assigned to each of the input ports 23a or all of the input ports 23a together, wherein each performs only the signal processing of the current, transparently switched-through high bit-rate data signal.

It is possible in this way to transmit the high bit-rate data signals not only within highly integrated circuits, for example, the FPGA 17, 19, 21 or 27, but also via the relatively long, serial connection lines 29, 31, 33.

The data transmission unit 1 according to the invention thus allows the simple connection of a (not shown) unit for testing one of the high bit-rate signals fed to the data transmission unit 1 on the output port 35.

Claims

1. Data transmission unit for high bit-rate data signals, especially high bit-rate optical data signals greater than 1 Gbit/s,

(a) with a backplane (3), which has a line structure connecting several (n) plug-in positions (5, 7, 9) for several (m) receiver or transceiver cards (11, 13, 15) to each other and/or to one or more other data processing cards,

(b) with several receiver or transceiver cards (11, 13, 15), which are each held in one of the plug-in positions (5, 7, 9) and which each have at least one input port (11b, 13b, 15b) each for a high bit-rate data signal, characterized in that,

(c) each of the receiver or transceiver cards (11, 13, 15) has at least one output port (11c, 13c, 15c), to which the relevant one or more high bit-rate data signals can be fed, and

(d) each of these output ports (5b, 7b, 9b) is connected via a serial data line (29, 31, 33) between the plug-in position (5, 7, 9) holding the relevant receiver or transceiver card (11, 13, 15) and an input port (23a) of a central selection unit (23) with the relevant input port (23a),

(e) wherein the central selection unit (23) has an output port (23b) to which one of the high bit-rate data signals can be fed in a controllable way.

2. Data transmission unit according to claim 1, characterized in that the one or more high bit-rate data signals fed to one of the receiver or transceiver cards (11, 13, 15) are optical data signals and in that each of these data signals is optoelectrically converted and fed to the relevant output port (11c, 13c, 15c).

3. Data transmission unit according to claim 1 or 2, characterized in that the selection unit (23) is arranged fixed on the backplane (3).

4. Data transmission unit according to claim 1 or 2, characterized in that the selection unit (23) is similarly held in a plug-in position (25).

5. Data transmission unit according to one of the preceding claims, characterized in that the selection unit (23) has a signal processing circuit, which compensates for negative effects on the signal during the transmission of the relevant signal between the output port (11c, 13c, 15c) of the relevant receiver or transceiver card (11, 13, 15) and the relevant input port (23a) of the selection unit (23).

6. Data transmission unit according to one of the preceding claims, characterized in that the selection unit (23) is constructed integrated with a signal evaluation unit.

7. Data transmission unit according to one of the preceding claims, characterized in that the evaluation unit (23) is constructed as a switch.

8. Data transmission unit according to one of the preceding claims, characterized in that the output ports (11c, 13c, 15c) of the receiver or transceiver cards (11, 13, 15) and/or the input ports (23a) of the central selection unit (23) are formed by high-speed interfaces of a field programmable gate array (27).

9. Receiver or transceiver card for a data transmission unit according to one of the preceding claims, characterized in that the output port (11c, 13c, 15c), to which at least one of the optoelectrically converted data signals can be fed, is assigned to at least one pin (5b, 7b, 9b) of a connection contact bar (5a, 7a, 9a).

10. Receiver or transceiver card according to claim 9, characterized in that the output ports (11c, 13c, 15c) of the receiver or transceiver card (11, 13, 15) are formed by a high-speed interface of a field programmable gate array (17, 19, 21).