Shift-add based multiplication
A system for multiplication of multi-bit first and second values. A processor is provided that has first and second memories with bit-positions that can all be zero or one and where the first memory has a low bit (LB). The first value is arranged in the first memory so its LSB is in the first memory LB, and the remaining bit-positions in the first memory are set to zero. The second value is arranged in the second memory such that its LSB is in the bit-position of the second memory that is next higher in order than the MSB of the first value in the first memory, and the remaining bit-positions in the second memory are set to zero. A +* operation is then performed a quantity of times equaling the number of significant bits in the first value, inclusive, thus obtaining the product of the first and second values.
This application claims the benefit of U.S. Provisional Application No. 60/974,820 entitled “Shift-Add Mechanism,” filed Sep. 24, 2007 by at least one common inventor, which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION1. Technical Field
The present invention relates generally to electrical computers and digital processing systems having processing architectures and performing instruction processing, and more particularly to processes for multiplication that can be implemented in such.
2. Background Art
Powerful and efficient operational codes (op-codes) are critical for modern computer processors to perform many tasks. For example, some such tasks are multiplication and producing sequences of pseudorandom numbers.
BRIEF SUMMARY OF THE INVENTIONAccordingly, it is an object of the present invention to provide a shift-add based multiplication process that is useful for various operations in a processor.
Briefly, a preferred embodiment of the present invention is a system for multiplication of multi-bit first and second values that each has a least significant bit (LSB) and a most significant bit (MSB). A processor is provided that has first and second memories with bit-positions that can all be zero or one, and where the first memory has a low bit (LB). A logic arranges the first value in the first memory such that its LSB is in the LB, and sets each of the bit-positions remaining in the first memory to zero. A logic arranges the second value in the second memory such that its LSB is in the bit-position of the second memory that is next higher in order than the MSB of the first value in the first memory, and sets each of the bit-positions remaining in the second memory to zero. A logic then performs a +* op-code a quantity of iterations equaling how many bits comprise the MSB through the LSB of the first value, inclusive, thus obtaining a product of the first and second values.
These and other objects and advantages of the present invention will become clear to those skilled in the art in view of the description of the best presently known mode of carrying out the invention and the industrial applicability of the preferred embodiment as described herein and as illustrated in the figures of the drawings.
The purposes and advantages of the present invention will be apparent from the following detailed description in conjunction with the appended tables and figures of drawings in which:
TBLS. 1-4 represent the values in the T-register and the S-register in a SEAforth™ 24a device in a set of hypothetical +* (shift-add mechanism) examples.
TBLS. 5-10 represent the values in the T-register and the S-register in a SEAforth™ 24a device in a set of hypothetical +* (shift-add mechanism) multiplication examples.
In the various figures of the drawings, like references are used to denote like or similar elements or steps.
DETAILED DESCRIPTION OF THE INVENTIONA preferred embodiment of the present invention is a shift-add based multiplication process. As illustrated in the various drawings herein, and particularly in the view of
The present inventive shift-add based multiplication process 200 (
The shift-add mechanism 100 (
As general background, the SEAforth™ 24a has 24 stack based microprocessor cores that all use the Venture Forth™ programming language.
There are two distinct approaches that can be taken when a programmer is selecting the bits that will make up the 18 bit wide register space in a SEAforth™ 24a (with limited exceptions for some op-codes that use the A-register). The first of these is to divide this space into four equal slots that can be called: slot 0, slot 1, slot 2, and slot 3. The bit lengths of these slots are not all equal, however, because division of 18 by 4 results in a remainder. The first three slots, slot 0, slot 1, and slot 2; therefore can each hold 5 bits while slot 3 holds only three bits.
The second approach that a programmer can use when selecting the bits that will make up the 18-bit wide register space in the SEAforth™ 24a is to simply not divide the 18-bit wide register into slots, and to instead consider the register as containing a single 18-bit binary value. This may appear at first to be a completely different approach than the slot-based approach, but both representations are actually equivalent.
TBLS. 1-4 represent the values in the T-register and the S-register in a set of hypothetical +* examples. For simplicity, only 4-bit field widths are shown. It is important to note in the following that the value in the T-register (T) is changed while the value in the S-register (S) remains unchanged during execution of the +* op-code. [N.b., to avoid confusion between the bits making up values and the locations in memory that may hold such, we herein refer to bits in values and to bit-positions in memory. It then follows that a value has a most significant bit (MSB) and a least significant bit (LSB), and that a location in memory has a high bit (HB) position and a low bit (LB) position.]
TBL. 1 shows the value one (1) initially placed in the T-register and the value three (3) placed in the S-register. Because the low bit (LB) position of T here is a 1, during execution of the +* op-code:
-
- (1) S and T are added together and the result is put in T (TBL. 2 shows the result of this); and
- (2) the contents of T are shifted to the right and a 0 is placed in bit 4 (TBL. 3 shows the result of this).
The reason for bit 4 being filled with a 0 is saved for later discussion.
The contents of T an S in TBL. 3 are now used for a second example. Because the LB position of T is now a 0, during another execution of the +* op-code:
-
- (1) the contents of T are simply shifted to the right and a 0 is placed in bit 4 (TBL. 4 shows the result of this).
Again, the reason for bit 4 being filled with a 0 is saved for later discussion. Additionally, it should be noted that the shift to the right of all of the bits in T is not associated in any way with the fact that a 1 or 0 filled the LB position of T prior to the execution of the +* op-code. Instead, and more importantly, the shift of all the bits to the right in T is associated with the +* op-code itself.
These two examples demonstrate nearly all of the actions associated with the +* op-code. What was not fully described was why 0 is used to fill bit 4. The following covers this.
The General Case of The +* Op-CodeA general explanation of the +* op-code is that it executes a conditional add followed by a bit shift of all bits in T in the direction of the low order bits when either a 1 or a 0 fills the high bit (HB) position of T after the shift.
Turning first to the shift sub-process 102, when the LB of T is 0, in a step 110 the content of the HB position of T is examined. When the HB position of T is 0, in a step 112 the contents of T are shifted right, in a step 114 the HB position of T is filled with a 0, and in a step 116 T contains its new value. Alternately, when the HB position of T is 1, in a step 118 the contents of T are shifted right, in a step 120 the HB position of T is filled with a 1, and step 116 now follows where T now contains its new value.
Turning now to the conditional add sub-process 104, when the LB position of T is 1, in a step 122 the contents of T and S are added and in a step 124 whether this produces a carry is determined. If there was no carry, the shift sub-process 102 is entered at step 110, as shown. Alternately, if there was a carry (the carry bit is 1), the shift sub-process 102 is entered at step 118, as shown. Then the +* op-code process (the shift-add mechanism 100) continues with the shift sub-process 102 through step 116, where T will now contain a new value.
While the actions associated with the +* op-code are easy to define,
The most general case of a +* op-code is now described using a pseudo-code algorithm. For this description it is assumed that the +* op-code is executed on an n-bit machine wherein an nt-bit width number t is initially placed in T and an ns-bit width number s is initially placed in S. Furthermore, it is assumed that only one additional bit is available to represent a carry, even if the +* op-code produces a carry that is theoretically more than one bit can represent. There is no restriction on the lengths of nt and ns, only that their individual bit lengths should be less than or equal to the bit width of n. The pseudo-code is as follows:
-
- 1. If the LB position of T is a 1:
- 1a. Add the value t in T to the value s in S where the sum of t+s, call this t′, replaces the present t in T and S is left unchanged.
- 1a1. If the HB position of T is a 1:
- 1a1a. If the addition of t and s resulted in a carry:
- 1a1a1. Shift all bits in T to the right one bit. Bit 0 of t′ after the shift contains the contents of bit 1 before the shift. Bit 1 of t′ after the shift contains the contents of bit 2 before the shift. In the same way, the rest of t′ is filled where bit m, m<n, being filled after the shift contains the contents of bit m+1 before the shift. This process leaves bit n devoid while effectively destroying bit 0 of t′ before the shift. Bit n of t′ after the shift will be filled with a 1.
- 1a1b. If the addition of t and s did not result in a carry:
- 1a1b1. Shift all bits in T to the right one bit. Bit 0 of t′ after the shift contains the contents of bit 1 before the shift. Bit 1 of t′ after the shift contains the contents of bit 2 before the shift. In the same way, the rest of t′ is filled where bit m, m<n, being filled after the shift contains the contents of bit m+1 before the shift. This process leaves bit n devoid while effectively destroying bit 0 of t′ before the shift. Bit n of t′ after the shift will be filled with a 1.
- 1a2. If the HB position of T is a 0:
- 1a2a. If the addition of t and s resulted in a carry:
- 1a2a1. Shift all bits in T to the right one bit. Bit 0 of t′ after the shift contains the contents of bit 1 before the shift. Bit 1 of t′ after the shift contains the contents of bit 2 before the shift. In the same way, the rest of t′ is filled where bit m, m<n, being filled after the shift contains the contents of bit m+1 before the shift. This process leaves bit n devoid while effectively destroying bit 0 of t′ before the shift. Bit n of t′ after the shift will be filled with a 1.
- 1a2b. If the addition of t and s did not result in a carry:
- 1a2b1. Shift all bits in t to the right one bit. Bit 0 of t′ after the shift contains the contents of bit 1 before the shift. Bit 1 of t′ after the shift contains the contents of bit 2 before the shift. In the same way, the rest of t′ is filled where bit m, m<n, being filled after the shift contains the contents of bit m+1 before the shift. This process leaves bit n devoid while effectively destroying bit 0 of t′ before the shift. Bit n of t′ after the shift will be filled with a 0.
- 1a1. If the HB position of T is a 1:
- 1a. Add the value t in T to the value s in S where the sum of t+s, call this t′, replaces the present t in T and S is left unchanged.
- 2. If the LB position of T is a 0:
- 2a. If the HB position of T is a 1:
- 2a1. Shift all bits in T to the right one bit. Bit 0 of t′ after the shift contains the contents of bit 1 before the shift. Bit 1 of t′ after the shift contains the contents of bit 2 before the shift. In the same way, the rest of t′ is filled where bit m, m<n, being filled after the shift contains the contents of bit m+1 before the shift. This process leaves bit n devoid while effectively destroying bit 0 of t′ before the shift. Bit n of t′ after the shift will be filled with a 1.
- 2b. If the HB position of T is a 0:
- 2b1. Shift all bits in T to the right one bit. Bit 0 of t′ after the shift contains the contents of bit 1 before the shift. Bit 1 of t′ after the shift contains the contents of bit 2 before the shift. In the same way, the rest of t′ is filled where bit m, m<n, being filled after the shift contains the contents of bit m+1 before the shift. This process leaves bit n devoid while effectively destroying bit 0 of t′ before the shift. Bit n of t′ after the shift will be filled with a 0.
- 2a. If the HB position of T is a 1:
- 1. If the LB position of T is a 1:
It is important to note in the preceding that the +* op-code always involves a bit shift to the right (in the direction of the low order bits) of all bits in T. This bit shift is not the result of any event before, during, or after the execution of the +* op-code. The bit shift is an always executed event associated with the +* op-code.
Multiplication Utilizing the +* Op-CodeIt has been implied herein that the shift-add mechanism 100 can be used for multiplication. An example is now presented followed by an explanation of the general case of utilizing the +* op-code to execute complete and correct multiplication.
Let us suppose that a person would like to multiply the numbers nine (9) and seven (7) and that the letter T is used to represent an 8-bit memory location where the nine is initially placed, and S is used to represent an 8-bit memory location where the seven is initially placed. [Nb., for simplicity we are not using the 18-bit register width of the SEAforth™ 24a device here, although the underlying concept is extendable to that or any bit width.]
TBLS. 5-10 represent the values in the T-register and the S-register in a set of hypothetical +* multiplication examples. TBL. 5 shows the value nine (9) initially placed in the T-register and the value seven (7) placed in the S-register. Next, the value in T is right justified in the 8-bit field width such that the four leading bits are filled with zeros. Conversely, the value in S is left justified in the 8-bit field width so that the four trailing bits are filled with zeroes. TBL. 6 shows the result of these justifications.
Correct multiplication here requires the execution of four +* op-codes in series. The first +* operation has the following effects. The LB position of T is 1 (as shown in TBL. 6), so the values in T and S are added and the result is placed in T (as shown in the left portion of TBL. 7). Next, the value in T is shifted to the right one bit in the same manner described in 1a2b1. (above). The values after this first +* operation are shown in the right portion of TBL. 7.
The second +* operation is quite simple, because the LB position of T is 0. All of the bits in T are shifted right in the manner described in 2b1. (above). The values after this second +* operation are shown in TBL. 8.
The third +* operation is similar to the second, because the LB position of T is again 0. All of the bits in T are again shifted right in the manner described in 2b1. (above). The values after this third +* operation are shown in TBL. 9.
The fourth and final +* operation is similar to the first +* operation. The LB position of T is 1 (as shown in TBL. 9), so the values in T and S are added and the result is placed in T (as shown in the left portion of TBL. 10). Next, the value in T is shifted to the right one bit in the same manner described in 1a2b1. (above). The values after this fourth +* operation are shown in the right portion of TBL. 10.
The resultant T in TBL. 10 is the decimal value 63, which is what one expects when multiplying the numbers nine and seven.
A +* Pseudo-Code Algorithm for MultiplicationThe multiplication of a positive value with a positive value will result in a correct product when the sum of the significant bits in T and S prior to the execution of this pseudo-code is less than or equal to 16 bits. And the multiplication of a positive value with a negative value will result in a correct product when the sum of the significant bits in T and S prior to the execution of the pseudo-code is less than or equal to 17 bits. Note that S should contain the two's complement of the desired negative value in S prior to the execution of this pseudo code.
-
- 1. If the desired multiplication is of a positive value with a positive value.
- 1a. Right justify t in the n bit field width of T.
- 1a1. Fill all leading bits in T after the MSB of t with zeros. The number of leading bits to fill should be exactly n-nt.
- 1b. Justify s in the n bit field width of S so that the LSB of s is located one bit higher than the MSB of t in T.
- 1b1. Fill all leading and trailing bits in S with zeros. The number of bits to fill should be exactly n-ns.
- 1c. Perform the multiplication.
- 1c1. Complete a for-loop indexing from 1 to nt.
- 1c1a. Execute the +* pseudo-code as described for the general case above.
- 1c1. Complete a for-loop indexing from 1 to nt.
- 1a. Right justify t in the n bit field width of T.
- 2. If the desired multiplication is of a positive value with a negative value.
- 2a. Right justify t in the n bit field width of T.
- 2a1. Fill all leading bits in T after the MSB of t with zeros. The number of leading bits to fill should be exactly n-nt.
- 2b. Perform the two's complement of the value s in S.
- 2b1. Bit shift the value s in S towards the HB of S by the number of significant bits nt.
- 2c. Perform the multiplication.
- 2c1. Complete a for-loop indexing from 1 to nt.
- 2c1a. Execute the +* pseudo-code as described for the general case above.
- 2c1. Complete a for-loop indexing from 1 to nt.
- 2a. Right justify t in the n bit field width of T.
- 3. If the desired multiplication is of a negative value with a negative value.
- 3a. Perform the two's complement of the value t in T.
- 3b. Perform the two's complement of the value s in S.
- 3b. Execute 1a-1c.
- 1. If the desired multiplication is of a positive value with a positive value.
Of course, the multiplication of a negative value with a positive value is the same as 2. (above) for multiplication, as long as the negative value is in T and the positive value in S.
While various embodiments have been described above, it should be understood that they have been presented by way of example only, and that the breadth and scope of the invention should not be limited by any of the above described exemplary embodiments, but should instead be defined only in accordance with the following claims and their equivalents.
Claims
1. A system for multiplication of multi-bit first and second values each having a least significant bit (LSB) and a most significant bit (MSB), comprising:
- (a) a processor having first and second memories with bit-positions that can all be zero or one and wherein said first memory has a low bit (LB);
- (b) a logic to arrange the first value in said first memory such that the LSB of the first value is in said LB and to set each of said bit-positions remaining in said first memory to zero;
- (c) a logic to arrange the second value in said second memory such that the LSB of the second value is in said bit-position of said second memory which is next higher in order than the MSB of the first value in said first memory and to set each of said bit-positions remaining in said second memory to zero;
- (d) a logic to perform a +* op-code for a quantity of iterations equaling how many bits comprise the MSB through the LSB of the first value, inclusive, thereby obtaining a product of the first and second values.
2. The system of claim 1, wherein said processor includes a plurality of registers and said first memory comprises one or more said registers, or said second memory comprises one or more said registers, or both.
3. A method for multiplication of multi-bit first and second values in a processor, wherein the first and second values each have a least significant bit (LSB) and a most significant bit (MSB), and wherein the processor has first and second memories with bit-positions that can all be zero or one and the first memory has a low bit (LB), the method comprising:
- (a) arranging the first value in the first memory such that the LSB of the first value is in the LB and such that each of the bit-positions remaining in said first memory is set to zero;
- (b) arranging the second value in the second memory such that the LSB of the second value is in the bit-position of the second memory which is next higher in order than the MSB of the first value in the first memory and such that each of the bit-positions remaining in said second memory is set to zero;
- (c) performing a +* op-code for a quantity of iterations equaling how many bits comprise the MSB through the LSB of the first value, inclusive, thereby obtaining a product of the first and second values.
4. The method of claim 3, wherein the processor includes a plurality of registers and the first memory includes one or more said registers, or the second memory includes one or more said registers, or both.
Type: Application
Filed: Apr 18, 2008
Publication Date: Mar 26, 2009
Inventor: Charles H. Moore (Sierra City, CA)
Application Number: 12/148,509