Apparatus and method for clock signal synchronization in JTAG testing in systems having modules processing clock signals at different rates

Abstract

In a test and debug system in which a plurality of modules under test have different operational rates, the system clock and the return clock signals from the modules lose synchronism. An error signal is produced when the clock signal makes a transition to a logic state that is the same logic state of the return clock signal of all of the modules. Apparatus is provided for generating logic signals when all of the return clock signals are in the same logic state. Two logic states are possible for all the return clock signals. A current state is latched until all the return clock signals are in the other state, at which time the second logic signal state is latched. The apparatus can be reset by an external signal.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the application of a system clock to a plurality of modules that process the clock signals at different rates. In particular, the modules process test and debug signals, such as JTAG signals, at different clock rates.

2. Background of the Invention

In certain processing units, different modules can process input signals a different clock rates. For example, modules of the ARM Corporation processing units process test and debug signals at different rates. In the JTAG test and debug format, not only is a clock (CLK) signal required, but a return clock (RCKL) signal must be present.

Referring to FIG. 1, the problem engendered by the variable processing rate modules is illustrated. The processing system under test includes modules 1-N. Each module has a (system) CLK signal applied to an input terminal thereof. Each module processes data according to its own internal clock. When the processing of the data is complete, the modules generate RCKL(1) through RCKL(N) signals. In FIG. 1, the application of rest data in TDI(1) through test data out TDI(N) to the modules is illustrated. After processing, the test data out TDO(1) through test data out TDO(N) is retrieved from the modules. In the important JTAG example, the TDI(1) through the TDI(N) are applied, in a series data format, to the modules and the TDO(1) and TDO(N) are retrieved in series format from the modules. Consequently, it is necessary the system clock signal not conflict with any of the RCLK(h) signals or the serial retrieval of the data signals can be compromised. Expressed in another manner, the TDI(k) are entered in the module, processed during the system clock interval and the TDO(k) retrieved from the modules for analysis.

As will be clear, either through failure of the system clock or as a result of variations in the time to process the data signals entered into each module, a timing error can occur and compromise the retrieved data.

It is therefore a feature of the apparatus and associated method to determine when a timing error has occurred in a group of modules that can process portions of a data stream at different rates. It would be yet another feature of the apparatus and associated method to determine when all the return clock signals from the a plurality of modules have a first logic state. It is yet another feature of the present invention to determine when all the module return clock signals have a second logic state. It is yet another feature of the present invention to determine when the return clock signals are inconsistent with the system clock signals. It is a more particular feature of the apparatus and associated method to provide an ERROR signal in the event of potential data corruption in a JTAG test and debug procedure. It is yet a further particular feature of the apparatus and associated to reset the apparatus after the generation of an error signal in response to an externally applied initiation signal.

SUMMARY OF THE INVENTION

The aforementioned and other features are accomplished, according to the present invention, by a first circuit that provides a signal when all of the RCK signals from the modules are in a first state and a second circuit that provides a second signal when the RCLK signals are in a second state. The output signals from the first and second circuits are latched until the opposite state signal is generated. The latched signal is compared to the system clock signal, the system clock being the system clock signal for all of the modules. When the comparison is positive, activity of the modules is continued. When the comparison is negative, an ERROR signal is generated and the results of the previous activity of the modules are discarded. In one implementation, when the ERROR signal is generated, an external signal can initialize the apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a system having a plurality of modules processing data signals at different rates according to the prior art.

FIG. 2 is a block diagram of a system having a plurality of modules processing data signals at different rates according to the present invention.

FIG. 3 illustrates the signals generated by the circuit of FIG. 2.

FIG. 4 is a block diagram showing an implementation of the circuits for generating a composite RCLK signal according to the present invention.

FIG. 5 illustrates waveforms from the apparatus in FIG. 4 when an error is generated by the operation of the circuits.

FIG. 6 illustrates a circuit for generating an ERROR signal and for initializing the circuit after generation of the error signal according to the present invention.

FIG. 7 illustrates the waveforms of the circuit of FIG. 6 including the initialization of the circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

1. Detailed Description of the Figures

FIG. 1 has been described with respect to the Related Art.

Referring to FIG. 2, a block diagram of the present invention is shown. As In FIG. 1, module 1 through module N process input data signals TDI(1) through TDI(N), respectively, at different rates. In the preferred embodiment, the TDI(1) through TDI(N) are shifted into the modules over a serial conducting path. A system clock CLK signal is applied to each of the module. The RCLK(1) through RCLK(N) signals are applied to adder circuit 20 where the signals are combined. The output signal from the adder circuit 20 is the RCLK signal.

Referring to FIG. 3, the clock waveforms for two modules is shown. The CLK signal provides the system clock for all of the modules. The modules process signals at different rates. Therefore, the RCLK(1) signal and the RCLK(2) signal are not in general synchronized with the system clock or with each other. The adder circuit 20 combines the two RCLK signal by providing composite signal when all of the component RCLK signals have begun (i.e., each component RCLK signal have begun). Similarly, the RCLK signal is initiated when all of the RCLK(k) signals have been initiated. In the example of FIG. 3, the RCLK(1) signal is activated and deactivated last. Therefore, the RCLK(1) signal and the RCLK signal are synchronized.

Referring to FIG. 4, an implementation of the adder circuit 20 of FIG. 2 is shown. In the example of FIG. 4, four modules are assumed to be present. The RCLK(1) through RCLK(4) signal are applied to I of logic AND gate 41 and these same signals are applied to inverting terminals of logic AND put terminals of logic AND gate 42. The output terminal of logic AND gate 41 is applied to the T terminal of DQ flip-flop 43. The output terminal of logic AND gate 44 is coupled to the T terminal of DQ flip-flop 43. A POR (Power On Reset) signal is applied to the R terminals of logic ADD gate 43 and to the R terminal of logic ADD gate 44. The Q′ terminal of DQ flip-flop 43 is applied to the D terminal of DQ flip-flop 43.The Q terminal of DQ flip-flop 43 is applied to the D terminal of DQ flip-flop 44 and to a first input terminal of exclusive OR gate 45. The Q terminal of DQ flip-flop 44 is applied to a second input terminal of exclusive OR gate 45. The output signal of exclusive OR gate 45 is latched and is transmitted through amplifier 46 to become the RTCLK signal. FIG. 4 also indicates that the CLK signal is the CLK signal for the modules 1 through 4. In the dotted box 49, a second implementation of a latch circuit is shown. The output terminal of logic AND gate 41 is coupled to an inverting terminal of logic NOR gate 49A, while the output terminal of logic AND gate 42 is coupled to an inverting terminal of logic NOR gate 49B. The output terminal of logic NOR gate 49A is coupled to a second input terminal of logic NOR gate 49B, while the output terminal of logic NOR gate 49B is coupled to a second input terminal of logic NOR gate 49A. The output terminal of logic NOR gate 49A provides a latched RCLK signal.

Referring to FIG. 5, the relationship of the clock signals that provides an ERROR signal is shown. In this example, the second clock pulse returns to zero while the RDLK signal is still zero, i.e., at least one of the RCLK(h) signals is still zero. At this time, an ERROR signal is generated.

Referring to FIG. 6, in order to create the ERROR signal of FIG. 5 an Error Detection and Initialization Unit 60 is shown. Components 41, 42, 43, 44, 45 and 46 are the same as in FIG. 4 except that the POR signal is not directly applied to the R terminals of DQ flip-flop 43 and DQ flip-flop 44. Instead, the POR signal is applied to a first terminal of logic OR gate 48, to a first terminal of logic OR gate 62, and to a first input terminal of logic NOR gate 64. The output terminal of logic OR gate 45, in addition to being applied to amplifier 46, is applied to a D terminal of DQ flip-flop 63 and to a D terminal of DQ flip-flop 64. The output terminal of logic NAND gate 42 is applied to a first terminal of logic AND gate 61. The first input terminal of exclusive OR gate 45 is coupled to an inverting second terminal of logic AND gate 61, the second input terminal of exclusive OR gate 45 is coupled to an inverting third input terminal of AND gate 61, and the ERROR signal is applied to a fourth terminal of Logic AND gate 61. The ERROR signal is also applied to a second input terminal of logic OR gate 48. The SYS_CLK signal is applied to an inverting fifth terminal of logic AND gate 61, to a T terminal of DQ flip-flop 63, and to a T terminal of DQ flip-flop 64. The output terminal of logic AND gate 61 is coupled to a second input terminal of logic OR gate 62. The output terminal of logic OR gate 62 is applied to a reset terminal of DQ flip-flop 63 and to a reset terminal of DQ flip-flop 64. The Q terminal of DQ flip-flop 63 is coupled to a second input terminal of logic NOR gate 64, while the q terminal of DQ flip-flop 64 is coupled to a third input terminal of logic NOR gate 64. The ERROR signal is applied to the output terminal of logic NOR gate 64.

2. Operation of the Preferred Embodiment

The operation of the present invention can be understood as follows. A first circuit has all the return clock signals applied thereto. When all the return signals have the same state, a first logic signal is latched. This first logic signal remains latched until all of the return clock signals reach the opposite state. At this point, a second logic signal is latched. The latched signal is compared to the logic level of the transitioning clock signal. When the clock signal transitions to the same logic level as the latched signal, an ERROR signal is generated. The ERROR signal remains latched until an initialize (POR) signal is applied to the circuit.

Using the circuit shown in FIG. 6, the ERROR signal is generated, but the ERROR signal is also available to help reinitialize the ERROR signal generating circuit. In addition to the ERROR signal, the initialization requires an externally applied signal. In FIG. 6, this signal is labeled the POR signal.

While the invention has been described with respect to the embodiments set forth above, the invention is not necessarily limited to these embodiments. Accordingly, other embodiments, variations and improvements not described herein are not necessarily excluded from the scope of the invention, the scope of the invention being defined by the following claims.

Claims

1. In a test and debug system having a plurality of modules operating at different rates, the modules receiving a common CLK signal and each module generating an RCLK signal, the method for providing an ERROR signal comprising:

combining the RCKL signals in a composite RCLK signal;

comparing the composite RCLK signal with the CLK signal; and

generating an ERROR signal when a transition of one signal results in the same state as the other signal.

2. The method as recited in claim 1 further comprising:

generating a composite; RCLK signal when the RCLK signals from the modules all have the same state; and

latching the most recent composite RCLK signal.

3. The method as recited in claim 1 wherein the test and debug system uses the JTAG format.

4. The method as recited in claim 1 further comprising initializing the apparatus generating the ERROR signal with a combination of the ERROR signal and an external signal.

5. An apparatus for detecting an error in the clocking of a test and debug procedure, the apparatus comprising;

a plurality of modules processing data signals applied thereto at different rates, the modules having a clock signal applied thereto, each module generating a return clock signal;

an first adder circuit having the return clock signals applied thereto, the first adder circuit generating a first signal when all of the return clock signals have first logic state;

a second adder circuit having the return clock signals applied thereto, the second adder circuit generating a second signal when the return clock signal have second logic state;

a latching circuit for latching the most recently generated to the first and the second output signal, and

a comparison circuit responsive to the clock signal, the first signal and the second signal, the comparison circuit generating an ERROR signal when the clock signal transition to the same logic state of the first or second signal.

6. The apparatus as recited in claim 5 wherein the test and debug procedure is a JTAG procedure.

7. The apparatus as recited in claim 5 further comprising a reset circuit responsive to the ERROR signal and an external signal, the reset circuit removing the ERROR signal.

8. In a test and debug system wherein a plurality of modules under test operates at different rates, an apparatus for generating a ERROR signal when a clock error is identified, the apparatus comprising:

a first summing circuit responsive to the return clock signals from the modules, the first summing circuit generating a first logic signal when all of the return clock signals have a first preselected value;

a second summing circuit responsive to the return clock signals from the modules, the second summing circuit generating a second logic signal when all of the return clock signals have a second preselected value;

a latching circuit having the first and the second preselected value applied thereto, the latching circuit latching one logic signal until the other logic signal is generated; and

a comparison circuit, the comparison circuit comparing the output signal of the latch circuit to a system clock signal, the comparison circuit generating an ERROR signal when the output signal has predetermined relationship with the system clock signal.

9. The apparatus as recited in claim 8 wherein the test and debug system is a JTAG test and debug system.

10. The apparatus as recited claim 8 wherein the modules being tested include module in processing machines by ARM Corporation.

11. The apparatus as recited in claim 10 wherein the predetermined relationship is an identity in the logic state of the system clock and the logic state of the of RCLK.

12. The apparatus as recited in claim 8 further comprising a reset circuit, the reset circuit responsive to the ERROR signal and an external signal for removing the ERROR signal.