PARTIAL SCRAMBLING TO REDUCE CORRELATION

Abstract

Decorrelation is provided between data stored in respective pairs of adjacent memory cells in a plurality of bit lines of a flash memory. Each of the pairs of adjacent memory cells is located along a respective one of the bitlines and common to two adjacent wordlines. The decorrelation is achieved by storing scrambled data in at least one memory cell of each of the pairs of adjacent memory cells and storing unscrambled data in at least one memory cell of at least one of the pairs of adjacent memory cells.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of provisional application 61/051,997, filed May 9, 2008, entitled “Partial Scrambling,” naming Ori Stem, Tal Heller, and Menahem Lasser as inventors, which application is incorporated herein by reference in its entirety.

This application is related to co-pending application entitled “Partial Scrambling to Reduce Correlation,” naming Ori Stem, Tal Heller and Menahem Lasser as inventors, U.S. application Ser. No. ______ (Attorney Docket No. 023-0080), filed on the same date as the current application, and which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to flash memories and, more particularly, to addressing correlation problems among data in flash memories.

2. Description of the Related Art

Modem NAND flash memories (e.g., 56 nm and smaller) have a strong coupling between adjacent wordlines and are inherently susceptible to specific data patterns. Thus, a write operation to one wordline might cause a programming effect to a different wordline. Specific patterns on the bit lines can result in stronger coupling and, therefore, more likely will result in an undesired programming affect. Such effects are particularly problematic in memory arrays storing multiple bits per cell (MBC arrays), and these effects can cause one or more cells to generate a read error as a function of specific user data patterns. It would be desirable to avoid such undesired programming effects in an efficient manner.

SUMMARY

Accordingly, in one embodiment, a method is provided for decorrelating between data stored in respective pairs of adjacent memory cells in a plurality of bit lines of a flash memory. Each of the pairs of adjacent memory cells is located along a respective one of the bitlines, and each of the pairs of adjacent memory cells is located on two adjacent wordlines common to all the pairs. The method includes storing scrambled data in at least one memory cell of each of the pairs of adjacent memory cells and storing unscrambled data in at least one memory cell of at least one of the pairs of adjacent memory cells.

In another embodiment, an apparatus is provided that includes a NAND flash memory including pairs of adjacent memory cells. Each of the pairs of adjacent memory cells is located along a respective one of a plurality of bitlines and each of the pairs of the adjacent memory cells is located on adjacent first and second wordlines common to all the pairs. A scrambler circuit is coupled to the flash memory and operable to perform selective scrambling on data for the flash memory to scramble data for at least one memory cell of each of the pairs of adjacent memory cells and to leave unscrambled data for at least one memory cell of at least one of the pairs of adjacent memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 illustrates an approach to scrambling in which all the data on every page is scrambled.

FIG. 2 illustrates a scrambler implementation that may be utilized in an embodiment of the invention.

FIG. 3 illustrates a flash memory system that implements scrambling using a microcontroller.

FIG. 4 implements a checkerboard scrambling pattern according to an embodiment of the invention.

FIG. 5 illustrates additional details of a flash memory illustrating adjacent cells of the flash memory in adjacent wordlines.

FIG. 6 illustrates a scrambling pattern in which every other wordline is scrambled according to an embodiment of the invention.

FIG. 7 illustrates a scrambling pattern in which a cube is sized at half the wordline according to an embodiment of the invention.

FIG. 8 illustrates scrambling of logical pages and their relationship to the physical wordlines of FIG. 4.

FIG. 9 illustrates exemplary pseudo code implementing a scrambling operation according to an embodiment of the invention.

The use of the same reference symbols in different drawings indicates similar or identical items.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

To address the issue of undesired programming effects due to correlation between wordlines, techniques have been devised using system level data scrambling or randomization to eliminate the particularly problematic data patterns in the user data before programming into a flash memory. The scrambled data is then stored into the flash memory as shown in FIG. 1. One approach, illustrated in FIG. 1, is to scramble or randomize all the data within each page with a different scrambler series. That results in each page using a different scrambling pattern so the most likely problematic user data patterns between pages are eliminated. Thus, as shown in FIG. 1, all the data of each page is scrambled and each page is scrambled with a different scrambler pattern. Note that each of the pages shown in FIG. 1 may be a separate wordline or portion of a wordline. Note also that management information (not shown in FIG. 1), which is typically stored in multiple locations in long wordlines, may not be scrambled in certain implementations.

As used herein, the terms “scrambling” or “randomizing” mean to subject original data to be stored in the flash memory to a randomization or scrambling process prior to storing the data in the flash memory. When reading the scrambled data, that scrambled data has to be unscrambled before use. One embodiment of that randomization process is illustrated with respect to FIG. 2 in which the data is randomized by XORing the data to be stored in the flash memory with a scrambler pattern. That scrambler pattern may be a pseudo-random pattern or a pattern specifically selected to address particular program disturb affects. One embodiment of a scrambler implementation is shown in FIG. 2. The 32-bit data word 201 that is unscrambled is XORed with a 32-bit scrambler pattern in shift register 203 to form a 32-bit scrambled data word 205. Implementations may XOR one or more bits at a time. The initial value of the shift register or seed may be different for every page to reduce correlation between pages. In an exemplary embodiment, a page is 4096 bytes and a wordline is 16384 bytes. Other embodiments may, of course, have different page and wordline sizes.

Referring to FIG. 3, in order to implement the scrambling approach in an embodiment, a microcontroller 301 is utilized. Other embodiments may use a hardware solution or a mixture of hardware and software. One problem with the randomization approach described in FIG. 1 is that the bandwidth of RAM bus 303 may not be enough to simultaneously perform multiple operations related to scrambling. For example, assume the microcontroller 303 wants to (1) read sector #1 from the RAM 305, and (2) write scrambled sector #1 back to the RAM. Further assume that the DMA machine in NAND flash controller 307 wants to read scrambled sector #0 from the RAM to write it to the NAND flash memory 309. Contention for the RAM bus 303 between the read and write operations by the microcontroller and the DMA by NAND flash controller 307 can slow the ability to write data to the flash memory or slow the write or read scrambling operations. In addition, microcontroller resources and time are utilized to perform the scrambling operations.

While the approach described with respect to FIG. 1 substantially eliminates undesired correlations between adjacent physical wordlines by scrambling both wordlines, the need for scrambling can reduce the device performance, as described with relation to FIG. 3. Assuming software scrambling, the CPU time may become a bottleneck if CPU processing takes longer than the data path stage. In addition, data buses might become a bottleneck as data is read, scrambled, and returned to the flash memory. When using page copy sequences, pages need to be de-scrambled and re-scrambled with a new page key. Thus, device performance can be adversely affected by the need to scramble to avoid undesired correlation between wordlines.

Accordingly, an improved scrambling approach is shown in FIG. 4. Rather than scramble or randomize all the bits or cells on each wordline, only half the data or cells need to be scrambled. As shown in FIG. 4, each wordline, WL #0, WL #1, etc., is divided into sections (also referred to herein as cubes) of data. For the first group of sections 401 in WL #0, each of the sections 403 is scrambled, whereas each of the sections 405 is not scrambled. As shown in FIG. 4, on WL #0, half of the sections are scrambled. In WL #1, the other half of the sections are scrambled, i.e., those sections in the locations that are not scrambled in WL #0, so that for any adjacent sections on separate wordlines, at least one is scrambled. Thus, the first section 407 in WL #1, which is adjacent to the first scrambled section in the group of sections 401 in WL #0, is not scrambled. A similar pattern holds for the remaining wordlines shown in FIG. 4, so that adjacent sections in adjacent wordlines are alternatively scrambled and not scrambled as one traverses down the wordlines.

Referring to FIG. 5, a portion of a NAND flash array is shown in greater detail. As shown in FIG. 5, respective pairs of adjacent memory cells, e.g., adjacent memory cells 501 and 503, and adjacent memory cells 505 and 507, are on a plurality of bit lines 502 and 504 of a flash memory. Each of the pairs of adjacent memory cells (501, 503 and 505, 507), are located along a respective one of the bitlines (502 and 504) and common to two adjacent wordlines 508 and 510. According to an embodiment of the invention, scrambled data is stored in at least one memory cell of each of the pairs of adjacent memory cells, and unscrambled data is stored in at least one memory cell of at least one of the pairs of adjacent memory cells. For example, scrambled data may be stored in 501 and 507, while unscrambled data is stored in cells 505 and 510. In that way, decorrelation is achieved between the data stored in the cell pair 501 and 503 and between the cell pair 505 and 507. Of course, as shown in FIG. 4, the number of cells that contain scrambled data may include multiple contiguous cells, e.g., sections of 32 cells or greater. Similarly, the section size of unscrambled data may be, e.g., 32 cells or greater. Other embodiments may have more or fewer cells forming the sections of scrambled and unscrambled data.

Thus, in various embodiments each section of cells in a wordline may vary from a single cell up to the entire wordline. Referring to FIG. 6, an exemplary embodiment is illustrated where the cube or section size is the entire wordline. Thus, WL#0 is scrambled and WL#1 is not scrambled. That pattern is repeated for the remaining wordlines, where alternating ones of the wordlines are scrambled. Referring to FIG. 7, illustrated is an embodiment where the section size is half the wordline. As in FIG. 4, alternating sections are scrambled for adjacent wordlines so that for any two adjacent cells on the same bitline and in adjacent wordlines, at least one of the cells will contain scrambled data. Note that in certain embodiments, management information may always remain unscrambled in the wordline. Thus, the embodiments shown in those FIGS. 4, 6, and 7, may be showing scrambling of data exclusive of the management information, which remains unscrambled. In other embodiments, even the management information is scrambled.

In modern flash memories, logical pages exist that do not align with the physical wordlines. While, in some implementations, a page may correspond to a wordline, in other embodiments, a page may map physically into a portion of a wordline. Referring to FIGS. 4 and 8, illustrated is the way, in one embodiment, that wordlines shown in FIG. 4 relate to the logical pages shown in FIG. 8. For example, in FIG. 8, logical page 0 (P#00) is found on EL00, which is (wordline 0, even lower) shown in FIG. 4. Similarly, logical page 1 (P#01) in FIG. 8 is found on OL00, which is physically (wordline 00, odd lower). Logical page 2 (P#02) is found on EL01, which is physically (wordline 01, even lower). A logical page number may be used to determine the scrambling pattern, but the particular section that is scrambled is determined by the wordline to ensure that adjacent sections in adjacent wordlines are alternately scrambled and unscrambled.

By scrambling only half the data, the decorrelation between cells in the sections (one section scrambled and one section not scrambled) is sufficient to substantially avoid undesired programming effects from correlation of adjacent cells on separate wordlines. Referring again to FIG. 3, scrambling or randomizing half the data reduces by half the computational effort associated with scrambling any particular pair of adjacent wordlines, as only half of the data in the adjacent wordlines needs to be scrambled. In addition, the traffic on RAM bus 303 is reduced as less data needs to be read, scrambled, and stored back into the RAM 305. While the efficiency is gained from scrambling half the data, other embodiments may choose to scramble more than half, with the recognition that efficiency is gained if less than all of the data is scrambled, and effective decorrelation is achieved if at least half the data is scrambled.

In flash memories with multi-bit cells, scrambling all the data bits in a cell with scrambled data may be optimal. However, in certain embodiments, some level of decorrelation can be achieved by scrambling less than all the bits stored in the cell. Thus, for example, for a multi-bit cell containing four bits, scrambling three of the bits may provide a sufficient level of decorrelation, depending, e.g., on such factors as the number of bits stored in the cell, the scrambling pattern used, and the particular programming effects to which a particular flash memory is susceptible. Thus, as used herein, the term “storing scrambled data” in a cell includes storing data in a cell that has had at least one bit of the data scrambled or randomized. Similarly, when referring to “scrambling (also referred to herein as randomizing) data,” it includes both the scrambling of all the bits to be stored in a cell and the scrambling of only some (one or more) of the bits to be stored in a cell, leaving unscrambled the other bits to be stored in the cell.

In an embodiment, the scrambling is implemented in a programmed microcontroller such as microcontroller 301 in FIG. 3. Referring to FIG. 9, exemplary pseudo code to implement the scrambling is shown that may be used to implement the scrambling on appropriate sections of data to be stored in the flash memory. As can be seen in the pseudo code, in the code labeled 1 the wordline number is determined from the page number. In step 2, the decision is made whether to start scrambling on the first section or cube in the wordline. That may be determined from the wordline being even or odd as shown. In step 3, the scrambling key is determined. In step 4 the initial shift register value is determined. In step 5, the cube size in 32 bit words is determined. Other ways to determine the scrambling key may be utilized as well. In an embodiment, the scrambling key is produced using the previous wordline data and current incoming user data. In step 6, if the scramble ThisCube is false, the cube is not scrambled and, otherwise, scrambling is performed on the cube. As will be appreciated by those of skill in the art, the particular implementation shown in FIG. 9 is exemplary and many other implementations may be utilized. For example, one could easily adapt the code shown in FIG. 9 to scramble alternate wordlines as shown in FIG. 6. In addition, rather than implementing the scrambling in a programmed microcontroller, the scrambling operation may be implemented entirely in hardware, or a portion of it may be implemented in hardware.

The foregoing description has described only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended by way of illustration, and not by way of limitation. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of this invention. Moreover, the embodiments described above are specifically contemplated to be used alone as well as in various combinations. Accordingly, other embodiments, variations, and improvements not described herein are not necessarily excluded from the scope of the invention.

Claims

1. An apparatus comprising:

a NAND flash memory including a plurality of pairs of adjacent memory cells, each of the pairs of adjacent memory cells being located along a respective one of a plurality of bitlines and each of the pairs of the adjacent memory cells being located on adjacent first and second wordlines common to all the pairs; and

a scrambler circuit coupled to the flash memory and operable to perform selective scrambling on data for the flash memory to scramble data for at least one memory cell of each of the pairs of adjacent memory cells and to leave unscrambled data for at least one memory cell of at least one of the pairs of adjacent memory cells.

2. The apparatus as recited in claim 1 wherein the scrambler circuit comprises a programmed microcontroller.

3. The apparatus as recited in claim 1 wherein the scrambler circuit is configured to scramble half of data to be stored in the pairs of adjacent memory cells.

4. The apparatus as recited in claim 1 wherein the scrambler circuit is operable to scramble data only for one of each of a plurality of adjacent wordlines including the first and second wordlines.

5. The apparatus as recited in claim 1 wherein the scrambler circuit is configured to scramble data for additional wordlines so as to form a checkerboard pattern of scrambled and unscrambled data in a plurality of wordlines of the NAND flash memory when the scrambled and unscrambled data is stored to the NAND flash memory, the plurality of wordlines including the two adjacent wordlines and the additional wordlines.

6. The apparatus as recited in claim 1 wherein the apparatus is operable to store scrambled data in a first plurality of memory cells in a first wordline of the two adjacent wordlines and to store unscrambled data in a second plurality of memory cells in a second wordline of the adjacent wordlines, the first and second plurality of cells forming at least some of the pairs of adjacent memory cells.

7. The apparatus as recited in claim 6 wherein the apparatus is operable to

store unscrambled data in a third plurality of memory cells in the first wordline of the two adjacent wordlines and to store scrambled data in a fourth plurality of memory cells in the second wordline of the adjacent wordlines, the third and fourth plurality of cells forming at least others of the pairs of adjacent memory cells.

8. The apparatus as recited in claim 6 wherein the first plurality of memory cells form a first contiguous group of memory cells across the first wordline and the second plurality of memory cells form a second contiguous group of memory cells across the second wordline.

9. The apparatus as recited in claim 6 wherein the first plurality of memory cells is a subset of memory cells of the first wordline and the second plurality of memory cells is a subset of memory cells of the second wordline.

10. The apparatus as recited in claim 6 wherein the first plurality of memory cells includes all cells in the first wordline and the second plurality includes all cells in the second wordline.

11. The apparatus as recited in claim 6 wherein the first plurality of memory cells includes all cells in the first wordline, exclusive of cells holding data for management, and the second plurality includes all cells in the second wordline.

12. The apparatus as recited in claim 1 wherein the apparatus is operable to store scrambled data in half of each pair of the memory cells of the adjacent wordlines.

13. The apparatus as recited in claim 1 wherein the scrambler circuit is operable to utilize numbers associated with respective wordlines to determine whether to scramble data for a first section of cells in the respective wordline.

14. The apparatus as recited in claim 1 wherein each of the adjacent wordlines is divided into a plurality of sections of memory cells and the scrambler circuit is operable to scramble data for every other section in each wordline.

15. The apparatus as recited in claim 1 wherein the scrambler circuit is operable to scramble data for the at least one memory cell by scrambling one or more bits to be stored in the at least one memory cell.

16. The apparatus as recited in claim 1 wherein the scrambler circuit is operable to scramble data for the at least one memory cell by scrambling one or more bits to be stored in the at least one memory cell and leaving unscrambled at least one bit to be stored in the memory cell with the one or more bits that are scrambled.

17. An apparatus comprising:

a NAND flash memory including respective pairs of adjacent memory cells, each of the pairs of adjacent memory cells being located along a respective one of a plurality of bitlines and each of the pairs being located on two adjacent wordlines common to all the pairs; and

means for storing randomized data in at least one memory cell of each of the pairs of adjacent memory cells and for storing non-randomized data in at least one memory cell of at least one of the pairs of adjacent memory cells.

18. The apparatus as recited in claim 17 apparatus comprising:

means for randomizing data for at least one memory cell of each of the pairs of adjacent memory cells and for leaving non-randomized data for at least one memory cell of at least one of the pairs of adjacent memory cells.

19. An apparatus comprising:

a scrambler circuit operable to scramble data for at least one memory cell of each of a plurality of pairs of adjacent memory cells in a flash memory and to leave unscrambled, data for at least one memory cell of at least one of the pairs of adjacent memory cells, each of the pairs of adjacent memory cells being located along a respective one of a plurality of bitlines and each of the pairs of memory cells being located on two adjacent wordlines common to all pairs.

20. The apparatus as recited in claim 19 wherein the scrambler circuit is operable to use a number associated with a respective one of wordlines to determine whether to scramble data for a first plurality of cells in the respective wordline.

21. The apparatus as recited in claim 19 further comprising the flash memory.

22. The apparatus as recited in claim 19 wherein the scrambler circuit comprises a programmed microcontroller.

23. The apparatus as recited in claim 19 wherein the scrambler circuit is configured to scramble half of data to be stored in the pairs of adjacent memory cells.

24. The apparatus as recited in claim 19 wherein the scrambler circuit is operable to scramble data only for one of each of a plurality of adjacent wordlines including the two adjacent wordlines.