INTEGRATOR-BASED COMMON-MODE STABILIZATION TECHNIQUE FOR PSEUDO-DIFFERENTIAL SWITCHED-CAPACITOR CIRCUITS
A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.
1. Field of the Invention
The present invention generally relates to pseudo-differential switched-capacitor circuits, referred to as an integrator-based common-mode stabilization technique.
2. Description of the Prior Art
High-precision switched-capacitor circuits require high-gain and high-linearity amplifiers, which dominate the performance of the switched-capacitor circuits. The modern process tends toward low operating voltage to improve the circuit performance. This tendency leads to limited signal range and thus the design complexity. Further, the amplifiers may consume more power in order to maintain the signal-to-noise ratio.
Fully differential amplifier 10, as shown in
The pseudo-differential switched-capacitor circuit as discussed above needs an effective mechanism to stabilize the common-mode voltage in order to keep sufficient signal swing for a low operating-voltage process. There are some techniques disclosed in the scientific/technical literature, which are discussed in the following paragraphs.
1. Common-Mode Feedback Circuit (CMFB)The common-mode feedback circuit (CMFB) is the most direct answer to stabilizing the output common-mode voltage.
For the pseudo-differential switched-capacitor circuit, in the sample phase, the common-mode voltage disturbance (Δ Vcm) is sampled by two capacitors, or equivalently speaking, common-mode voltage disturbance Δ Vcm, provided that the two capacitors have the same capacitance C, is sampled by the two capacitors, resulting in common-mode gain of two (2). It may be possible to decrease the common-mode gain to relieve the effect of the common-mode voltage disturbance on the circuit, by decreasing the degree of sampling the common-mode voltage disturbance (Δ Vcm). This goal can be obtained, for example, by applying a differential floating sampling scheme (DFS) as shown in
Due to the disadvantages of the prior techniques for the common mode stabilization of the peudo-differential switched-capacitor circuits, a need has arisen to propose an innovative technique that could effectively decrease the common-mode voltage drift due to the charge injection effect caused by associated switches.
SUMMARY OF THE INVENTIONIn view of the foregoing, it is an object of the present invention to provide a common-mode stabilization technique, particularly an integrated-based technique, for pseudo-differential switched-capacitor circuit, such that the common-mode voltage drift due to the charge injection effect caused by associated switches can be substantially improved.
According to one embodiment, a differential floating sampling (DFS) technique is employed to make the pseudo-differential architecture with unity common-mode gain, which only bypasses the input common-mode disturbance to the output of the switched-capacitor circuit. Therefore, the input common-mode disturbance and the common-mode error caused by the switch charge injection can be sensed at the output of the switched-capacitor circuit. An integrator is employed to sense the total output common-mode disturbance and feed back its output cmi to the switched-capacitor circuit with the DFS technique. thereby stabilizing output common-mode level at a desirable level. Specifically, during the amplify phase (ψ 2), the integrator detects common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−). During the sample phase (ψ 1), the integrator performs integration and feeds the output of the integrator amplifier back to the switched-capacitor circuit, thus forming a common-mode negative feedback loop to adjust the differential positive output (Vout+) and negative output (Vout−).
The pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique 802, in the embodiment, includes a positive path and a negative path. In the positive path, the input node of a first single-ended amplifier 8021 is electrically coupled to first ends of a first capacitor C1 and a second capacitor C2, which are electrically connected in parallel. In the specification, the term “electrically” coupled or connected means that two elements/nodes are either directly connected through conductive wire or are indirectly connected via switch(s), and may be understood in context with the associated figure and description. The output node of the first amplifier 8021 provides the positive output Vout+. The two ends of the first capacitor C1 and the second capacitor C2 are electrically connected to the positive input Vin+. The first capacitor C1 is electrically connected between the positive input Vin+ and the input node of the first amplifier 8021 via the ψ 1 and ψ 2 controlled switches in the following manner: in the sample phase, the first capacitor C1 is directly connected between the positive input Vin+ and the output node of the integrator 804 cmi; in the amplify phase, the bottom plate of the first capacitor C1 is connected to the positive output voltage Vout+, and the top plate of the first capacitor C1 is disconnected to the output node of the integrator 804 cmi. The second capacitor C2 is electrically connected between the positive input Vin+ and the input node of the first amplifier 8021 via the ψ 1 and ψ 2 controlled switches in the following manner: in the sample phase, the bottom plate of the second capacitor C2 is connected to the positive input Vin+ and the upper plate of the second capacitor C2 is floating, which means no DC path at this node; in the amplify phase, the bottom plate of the second capacitor C2 is connected to a reference voltage VR and the upper plate of the second capacitor C2 is connected to the input node of the first amplifier 8021.
In the negative path, a second single-ended amplifier 8022, a third capacitor C3 and a fourth capacitor C4 are connected in a manner similar to that of the first single-ended amplifier 8021, the second capacitor C2 and the first capacitor C1 as discussed above. That is, the second single-ended amplifier 8022 configures similarly as the first single-ended amplifier 8021 does, the third capacitor C3 configures similarly as the second capacitor C2 does, and the fourth capacitor C4 configures similarly as the first capacitor C1 does. The connections of the above-mentioned elements are summarized in the following Table 1.
In brief, in the sample phase (with active ψ 1), the capacitor C1 and the capacitor C4 sample the input common-mode disturbance (via ψ 1-controlled switches), while the upper plates of the capacitor C2 and the capacitor C3 are floating (due to floating switch surrounded by the dash rectangular). The capacitor C1 or the capacitor C4 will sample the common-mode voltage disturbance (ΔVcm) to get the common-mode voltage disturbance charge (1×C×Δ Vcm), but the floating capacitor C2 or the capacitor C3 will sample no charge. Accordingly, the common-mode gain of the circuit 80 has a value of one (1), and the input common-mode voltage disturbance will not be amplified. The DFS circuit 802, similar to the circuit 60 (
The integrator 804, which is configured as a non-inverted integrator in the embodiment, is utilized to overcome the charge injection effect. The integrator 804 has two inputs, which are respectively coupled to the outputs Vout+ and Vout− of the DFS circuit 802 electrically. The negative input node of an integrator amplifier 8040 is electrically coupled, via ψ 1-controlled switch, to parallel-connected sample capacitors Ci1 and Ci2, and the positive input node of the amplifier 8040 receives an input bias Vb and is electrically coupled, via ψ 2-controlled switch, to parallel-connected sample capacitors Ci1 and Ci2. Further, the non-inverting input node is connected to output node (cmi) with an integrator capacitor Ci3. The output node (cmi) of the amplifier 8040 is coupled to the input node of the amplifiers 8021/8022 via ψ 1-controlled switches.
In the integrator sampling phase (with active ψ 2), the integrator 804 is coupled to the DFS circuit 802 viaψ 2-controlled switches, and is used to detect the common-mode voltage disturbance at the output node Vout+ and Vout−, which contains the input common-mode disturbance and the common-mode error induced by the charge injection in the DFS circuit. In this phase, the bottom plates of the capacitors Ci1 and Ci2 are connected to the DFS circuit 802, while the upper plates of the capacitors Ci1 and Ci2 are connected to the positive input node of the amplifier 8040. In the integrating phase (with active ψ 1), the bottom plates of the capacitors Ci1 and Ci2 are connected to common-mode voltage Vcm which is the desired output common-mode voltage of the DFS circuit, and the upper plates are connected together to the (negative) input node of the amplifier 8040. In this phase, the integrator 804 performs the common-mode disturbance integration, and feeds the output voltage cmi back to the upper plates of the capacitors C1 and C4, thus forming a common-mode negative feedback loop. As the integrator 80 is capable of accumulating charge, the integrator 80 thus can gradually adjust the output voltage Vout+/Vout−, thereby stabilizing the output common-mode level at a desirable level. The connections of the above-mentioned elements are summarized in the following Table 2.
In designing the integrator 804, some guidelines may be followed:
- 1. The sample capacitors Ci1/Ci2 and the integrator capacitor Ci3 should be properly selected, such that the integrator 80 can be sufficiently stable. In general, the sample capacitors Ci1/Ci2 should have value less than the integrator capacitor Ci3.
- 2. As the gain of the amplifier 8040 affects the common-mode voltage at the output Vout+/Vout−, the smaller the gain is, the greater the common-mode error (or noise) is. In practice, according to one simulation, an amplifier with gain of 20 dB causes output common-mode error of 30 mV, which is mostly tolerable. When the feedback control scheme disclosed above is applied, for example, to each of cascaded circuit stages, we can use a single-stage amplifier to implement the integrator 804 provided that the common-mode error in each stage is controllably comparable to the error caused by the integrator amplifier 8040.
According to the embodiment, the additional integrator 804 may be implemented merely by a single-stage, low-gain and low-power amplifier. The integrator 804 consumes substantially less power than the analog adder/subtractor 704 of the CMFF circuit 70 (
Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.
Claims
1. A pseudo-differential switched-capacitor circuit, comprising:
- a differential floating sampling (DFS) circuit that has a pseudo-differential architecture with a common-mode gain value of one (1), said DFS circuit having a differential positive input (Vin+) and a negative input (Vin−), and said DFS circuit having a first single-ended amplifier and a second single-ended amplifier, wherein the first single-ended amplifier has having a differential positive output (Vout+) and the second single-ended amplifier has a differential negative output (Vout−); and
- an integrator electrically coupled to the differential positive/negative outputs, the integrator controllably feeding back integrator output to inputs of the first single-ended amplifier and the second single-ended amplifier of the DFS circuit, and the integrator receiving by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) of the DFS circuit at a desirable level;
- wherein the integrator includes: an integrator amplifier having a positive input and a negative input; a first sample capacitor and a second sample capacitor which are connected in parallel; and an integrator capacitor which is connected between an output of the integrator amplifier and the negative input of the integrator amplifier; wherein the integrator amplifier is connected to the first and second sample capacitors via switches.
2. The pseudo-differential switched-capacitor circuit of claim 1, wherein the integrator is configured as a non-inverted integrator.
3. (canceled)
4. The pseudo-differential switched-capacitor circuit of claim 1, wherein the integrator performs integration and feeds the output of the integrator amplifier back to the DFS circuit during an integrating phase (ψ1), thus forming a common-mode negative feedback loop to adjust the differential positive output (Vout+) and negative output (Vout−).
5. The pseudo-differential switched-capacitor circuit of claim 4, wherein the integrator detects common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−) during an integrator sampling phase (ψ2).
6. The pseudo-differential switched-capacitor circuit of claim 5, wherein the integrator further includes integrate-phase (ψ1) controlled switches and sample-phase (ψ2) controlled switches.
7. The pseudo-differential switched-capacitor circuit of claim 6, wherein, during the integrating phase, the first and second sample capacitors are connected to common-mode voltage via the ψ1 controlled switches, and are connected to the negative input of the integrator amplifier via one of the ψ1 controlled switches.
8. The pseudo-differential switched-capacitor circuit of claim 7, wherein, during the integrator sampling phase, the first and second sample capacitors are respectively connected to the differential positive output (Vout+) and negative output (Vout−) via the ψ2 controlled switches, and are connected to the positive input of the integrator amplifier via one of the ψ2 controlled switches.
9. The pseudo-differential switched-capacitor circuit of claim 8, wherein the DFS circuit includes:
- a positive path including the first single-ended amplifier, a first capacitor and a second capacitor, wherein the first and second capacitors are electrically coupled in parallel; and
- a negative path including the second single-ended amplifier, a third capacitor and a fourth capacitor, wherein the third and fourth capacitors are electrically coupled in parallel;
- wherein the output of the integrator amplifier is connected to inputs of the first and second single-ended amplifiers via the ψ1 controlled switches, and the outputs of the first and second single-ended amplifiers respectively provide the differential positive output (Vout+) and negative output (Vout−).
10. The pseudo-differential switched-capacitor circuit of claim 9, wherein:
- the first capacitor is connected between the positive input (Vin+) and the output of the integrator in the integrator sampling phase; in the, and in an amplify phase a bottom plate of the first capacitor is connected to the positive output (Vout+); and
- the second capacitor is electrically connected between the positive input (Vin+) and the input of the first single-ended amplifier via the ψ1 and ψ2 controlled switches in the following manner: in the integrator sampling phase a bottom plate of the second capacitor is connected to the positive input (Vin+) and an upper plate of the second capacitor is floating, and in the amplify phase the bottom plate of the second capacitor is connected to a reference voltage and the upper plate of the second capacitor is connected to the input node of the first singled-ended amplifier.
11. The pseudo-differential switched-capacitor circuit of claim 10, wherein:
- the fourth capacitor is connected between the positive input (Vin+) and the output of the integrator in the integrator sampling phase, and in the amplify phase a bottom plate of the fourth capacitor is connected to the positive output (Vout+); and
- the third capacitor is electrically connected between the negative input (Vin−) and the input of the second single-ended amplifier via the ψ1 and ψ2 controlled switches in the following manner: in the integrator sampling phase a bottom plate of the third capacitor is connected to the negative input (Vin−) and an upper plate of the third capacitor is floating, and in the amplify phase the bottom plate of the third capacitor is connected to the reference voltage and the upper plate of the third capacitor is connected to the input node of the second singled-ended amplifier.
Type: Application
Filed: Dec 2, 2008
Publication Date: Jun 3, 2010
Inventors: Soon-Jyh Chang (Tainan), Jin-Fu Lin (Tainan), Chih-Haur Huang (Tainan)
Application Number: 12/326,854
International Classification: G06G 7/184 (20060101);