Quadrature-Corrected Feedforward Control Apparatus and Method for DC-AC Power Conversion

Abstract

An apparatus and method for controlling the delivery of a pre-determined amount of power from a DC source to an AC grid includes an inverter and an inverter controller. The inverter includes an input converter, an energy storage capacitor, and an output converter. The inverter controller includes an input converter controller and an output converter controller. The input converter controller includes feedforward controller configured to perform a calculation to determine a value for the duty cycle for the input converter such that: (1) the input converter delivers the pre-determined amount of power and (2) the magnitude of a ripple signal reflected into the input source is attenuated toward zero. The input converter controller may also include a quadrature corrector configured to determine the effectiveness of the calculation in attenuating the ripple and to adaptively alter the calculation to improve the effectiveness.

Description

CROSS-REFERENCE TO RELATED U.S. PATENT APPLICATIONS

The present application is a continuation application of U.S. application Ser. No. 12/902,049, now U.S. Pat. No. 8,503,200, entitled “Quadrature-Corrected Feedforward Control Apparatus and Method For DC-AC Power Conversion” by Patrick L. Chapman et al., which was filed on Oct. 11, 2010, the entirety of each of which is hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates, generally, to methods and apparatuses for controlling power converters that convert DC power to AC power and, more particularly, to methods and apparatuses for controlling DC-to-AC converters configured to deliver power from a photovoltaic source to an AC grid.

BACKGROUND

One application of alternative energy sources is the delivery of power to an alternating-current (AC) utility grid. In such applications, an inverter (i.e., a DC-AC power conditioner) is required in order to convert the DC power delivered by the alternative energy source into sinusoidal alternating-current (AC) power at the grid frequency. Certain inverters (e.g., those used by residential customers or small businesses) convert the DC power delivered by the alternative energy source into single-phase AC power and deliver a sinusoidal current to the AC grid at the grid frequency. One figure of merit for such inverters is the utilization ratio, which is the percentage of available power that the inverter can extract from an energy source. Ideally, an inverter will achieve a utilization ratio of 100%.

A basic electrical property of a single-phase AC power system is that the energy flow includes both an average power portion that delivers useful energy from the energy source to the load and a double-frequency portion that flows back and forth between the load and the source:

p(t)=Po+Po*cos(2ωt+φ)

In applications involving inverters, the double-frequency portion (Po*cos(2ωt+φ)) represents undesirable ripple power that, if reflected back into the DC power source, may compromise performance of the source. Such concern is particularly worrisome for photovoltaic cells.

Photovoltaic cells have a single operating point at which the values of the current and voltage of the cell result in a maximum power output. This “maximum power point” (“MPP”) is a function of environmental variables, including light intensity and temperature. Inverters for photovoltaic systems typically comprise some form of maximum power point tracking (“MPPT”) as a means of finding and tracking the maximum power point (“MPP”) and adjusting the inverter to exploit the full power capacity of the cell at the MPP. Extracting maximum power from a photovoltaic cell typically requires that the cell operate continuously at its MPP; fluctuations in power demand, caused, for example, by double-frequency ripple power being reflected back into the cell, will compromise the ability of the inverter to deliver the cell's maximum power. Thus, to maximize the utilization ratio, an inverter for photovoltaic energy systems should draw only the average power portion of the energy flow from the photovoltaic cells at the inverter input. Such inverters should therefore comprise means to manage the double-frequency ripple power without reflecting the ripple power back into the source.

To manage double-frequency ripple power, energy needs to be stored and delivered at twice the AC frequency. One way to manage the double-frequency ripple power is to use passive filtering in the form of capacitance across a DC bus of the inverter. However, passive filtering alone may require a relatively large capacitance value to filter the double-frequency power, since the double-frequency energy exchange needs to be supported by the capacitor without imposing significant voltage ripple on the DC bus. Controlling the duty cycle of a regulator that is connected between the source and the DC bus may enable further attenuation, over and above that provided by the bus capacitor alone, in the amount of the double-frequency ripple power that is reflected back into the source.

Another way to manage double-frequency ripple power is to use an active filter circuit that supplies the double-frequency ripple power by means of a capacitor internal to the active filter. Whereas the passive filtering approach requires a relatively large filter capacitor, the internal capacitor in an active filter may be made relatively smaller, since it is only required to store and deliver the double-frequency ripple power and is not required to support the DC bus voltage. Because the active filter “isolates” the internal capacitor from the DC bus, the voltage variation across the internal capacitor can be relatively large and the value of the capacitor may be made relatively small.

SUMMARY

According to one aspect, an apparatus for controlling the delivery of power from a unipolar input source to an alternating-current (AC) grid, the AC grid characterized by a grid voltage, V_rms, a nominal grid frequency w, and a grid phase θ, may include an inverter and an inverter controller. The inverter may include (i) an input converter configured to deliver power from the unipolar input source to a unipolar bus, (ii) an energy storage element coupled to the unipolar bus and configured to supply energy to and absorb energy from the unipolar bus, and (iii) an output converter coupled to the unipolar bus and configured to deliver power from the unipolar bus to the AC grid in the form of a substantially sinusoidal current at the grid frequency. The inverter controller may be coupled to the inverter and may include (i) an output converter controller coupled to the output converter and configured to control the output converter to deliver power to the AC grid and (ii) an input converter controller coupled to the input converter and configured to control a duty cycle of the input converter to control delivery of a pre-determined amount of power from the input source to the unipolar bus.

In some embodiments, the input converter controller may include (i) means for setting a magnitude of the pre-determined amount of power, (ii) a feedforward controller configured to perform a calculation to determine a value for the duty cycle for the input converter such that: (1) the input converter delivers the pre-determined amount of power and (2) the magnitude of a ripple signal reflected into the input source is attenuated toward zero, and (iii) a quadrature corrector configured to determine the effectiveness of the calculation in attenuating the ripple and to adaptively alter the calculation to improve the effectiveness of the calculation.

Additionally, in some embodiments, the input source may be embodied as a photovoltaic (“PV”) cell and the means for setting a magnitude may be embodied as a Maximum Power Point Tracking controller. In some embodiments, the energy storage element is a capacitor. Additionally, the ripple signal may include a ripple component at a harmonic of the AC grid frequency and/or a second harmonic of the AC grid frequency.

In some embodiments, the feedforward controller may be configured to receive a signal, d₀, from the means for setting a magnitude. The signal d₀ may be indicative of the duty cycle that is required to deliver the pre-determined amount of power. In such embodiments, the quadrature corrector may be configured to deliver a phase correction term, δ, and a gain correction term, k, to the feedforward controller. Additionally, the feedforward controller calculates a duty cycle, d, of the form: d=d₀−k·C.

Additionally, in some embodiments, the energy storage element is embodied as a storage capacitor of value C_bus. In such embodiments, the feedforward controller may be configured to receive (i) measurements indicative of the value of the rms value of the AC grid voltage, V_rms, (ii) the rms value of the substantially sinusoidal current delivered by the output converter, I_rms, and (iii) the value of the unipolar bus voltage, V_bus0; and to set

$C=\left(1-d_0\right)\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}}\sin \left(2\omega t\right).$

In some embodiments, the feedforward controller may be configured to receive (i) a measurement indicative of the value of the power delivered by the inverter to the AC grid, P_out, and (ii) a value φ indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage; and to set

$C=\left(1-d_0\right)\frac{P_{\mathrm{out}}}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t\right).$

In some embodiments, the feedforward controller is configured to receive (i) a measurement indicative of the power delivered by the unipolar input source, P_s; (ii) a value φ indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage; and (iii) a value η indicative of the operating efficiency of the inverter; and to set

$C=\left(1-d_0\right)\frac{P_s}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t\right).$

Additionally, in some embodiments, the feedforward controller may be configured to receive (i) measurements indicative of the value of the voltage delivered by the unipolar input source, V_s, (ii) measurements indicative of the value of the current delivered by the unipolar input source, I_s, (iii) a value φ indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage, and (iv) a value η indicative of the operating efficiency of the inverter; and to set

$C=\left(1-d_0\right)\frac{V_sI_s}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t\right).$

In some embodiments, the quadrature corrector may include a first low pass filter that is configured to receive a measurement indicative of the magnitude of an input current delivered by the unipolar input source, i_in, and to deliver a double-frequency signal, ĩ_in, indicative of the magnitude of the component of the input current ripple that is twice the frequency of the AC grid frequency. Additionally, in some embodiments, the quadrature corrector may further include a phase error detector configured to generate a phase error signal based upon a difference between the phase of the double-frequency signal and the grid phase, θ. In such embodiments, the phase error signal may have a zero average value when said difference is substantially zero.

Additionally, in some embodiments, the phase error detector may include a first phase comparator that receives a signal indicative of the grid phase, θ, and delivers a signal, Q₂, such that

$Q_2=\{\begin{array}{cc}1& \mathrm{if}\frac{\pi }{4}<\mathrm{mod}\left(\theta ,\pi \right)<\frac{3\pi }{4}\\ -1& \mathrm{otherwise}.\end{array}$

The phase error detector may also include a first multiplier that delivers a phase error signal, e₂=Q₂·ĩ_in, a second low pass filter configured to deliver a signal e₂ indicative of the average value of e₂, and a first proportional-integral filter configured to receive e₂ and deliver the phase correction term, δ.

In some embodiments, the quadrature corrector may further include a gain error detector that generates a gain error signal based upon the magnitude of the double-frequency signal. In such embodiments, the gain error signal may have a zero average value when said magnitude is substantially zero. Additionally, in some embodiments, the gain error detector may include a second phase comparator that receives a signal indicative of the phase of the AC grid and delivers a signal:

$Q_1=\{\begin{array}{cc}1& \mathrm{if}0<\mathrm{mod}\left(\theta ,\pi \right)<\frac{\pi }{2}\\ -1& \mathrm{otherwise}.\end{array}$

The gain error detector may also include a second multiplier that delivers a gain error signal, e₁=Q₁·ĩ_in, a third low pass filter configured to deliver a signal e₁ indicative of the average value of e₁, and a second proportional-integral filter configured to receive e₁ and deliver the gain correction term k.

Additionally, in some embodiments the input converter may be embodied as a current-controlled converter. In some embodiments, the input converter is embodied as a boost switching power converter. Further, in some embodiments, the boost switching power converter may include an isolation transformer for providing galvanic isolation between the input source and the unipolar bus. Additionally, in some embodiments, the output converter controller is configured to control the output converter to deliver power to the AC grid in the form of a substantially sinusoidal current at the grid frequency. Additionally, in some embodiments, the inverter may further include an output filter connected between the output converter and the AC grid.

In some embodiments, the average power delivered to the AC grid by the output converter is controlled by the output converter controller to be substantially equal to the power delivered by the unipolar source less the substantial total of the power losses in the inverter. Additionally, in some embodiments, the power delivered to the grid may be controlled by the output controller to comprise an average power component and a time-varying power component. Further, in some embodiments, the output converter may be embodied as a full-bridge switching circuit comprising controllable switches configured to receive power from the unipolar bus and deliver power to the AC grid.

In some embodiments, the output converter controller may include a feedforward controller configured to receive a measurement of the power delivered to the input converter by the unipolar input source, P_s, a measurement of the rms grid voltage, V_rms, a measurement of the grid phase, θ, a pre-determined setpoint value of a power factor angle, φ. In such embodiments, the feedforward controller may be configured to control the output converter to deliver to the AC grid a time-varying component of current essentially equal to:

i_LFF(t)=(√{square root over (2)}·P_s/V_rms)·(cos(θ+φ)/cos(φ).

Additionally, in such embodiments, the energy storage element may be embodied as a capacitor, C_bus and the output converter controller may include a feedback controller that receives (i) a measurement of the average voltage across the unipolar bus, V_bus0, and (ii) a pre-determined setpoint value indicative of a desired average value of the unipolar bus voltage, V_bus*. In such embodiments, the feedback controller may control the output converter to deliver to the AC grid an additional time-varying component of current, which, when combined with i_LFF(t), causes V_bus0 to be substantially equal to V_bus*. Additionally, in such embodiments, the output converter controller may be configured to alter the magnitude of V_bus* as a function of selected inverter operating conditions. Further, the selected inverter operating conditions comprise the operating power of the converter and the AC grid voltage. Additionally, in some embodiments, the output converter controller may include a filter that receives a measurement of the voltage across the unipolar bus, V_bus, and delivers the measurement of the average voltage across the unipolar bus, V_bus0. Additionally, the filter may include a low-frequency rolloff filter having a pole at a frequency equal to one-tenth of the grid frequency.

According to another aspect, a method for controlling an inverter that is configured to deliver power from a unipolar input source to an alternating-current (“AC”) grid at a grid voltage and grid phase, may include delivering a pre-determined amount of power from the unipolar input source to a unipolar bus using an input converter, supplying energy to and absorbing energy from the unipolar bus using an energy storage capacitor, delivering power from the unipolar bus to the AC grid using an output converter, and controlling the operation of the inverter using an inverter controller. In some embodiments, controlling the operation of the inverter may include (i) calculating a duty cycle for the input converter such that (a) the input converter delivers the pre-determined amount of power and (b) the magnitude of a ripple signal reflected into the input source may be attenuated toward zero, and (ii) determining the effectiveness of the calculation in attenuating the ripple and adaptively altering the calculation to improve the effectiveness of the calculation.

Additionally, in some embodiments, delivering the predetermined amount of power may include delivering the predetermined amount of power from the unipolar input source to the unipolar bus using an input converter comprising a switching power converter, and controlling the operation of the input converter may include controlling the input converter using an input converter controller of the inverter controller. Further, in some embodiments, delivering power from the unipolar bus to the AC grid may include delivering power from the unipolar bus to the AC grid using an output converter comprising a switching power converter, and controlling the operation of the output converter may include controlling the output converter using an output converter controller of the inverter controller to deliver power to the AC grid.

In some embodiments, the energy storage element may be embodied as a bus capacitor and the input converter may be embodied as a switching power converter. In such embodiments, controlling the input converter may include (i) providing to the inverter controller: a value indicative of the size of the bus capacitor, C_bus, a value indicative of the grid frequency, ω, a measurement of the rms grid voltage, V_rms, a measurement of the rms inverter output current, I_rms, a measurement of the unipolar bus voltage, V_bus0, a measurement of the grid phase, θ; (ii) calculating a duty cycle for the input converter by: adjusting a nominal duty cycle, d₀, to a value that is consistent with delivering the pre-determined amount of power, calculating a correction term, {tilde over (d)}, for attenuating a reflected ripple signal, ĩ_r, at a frequency 2ω:

$\tilde{d}=k\left(1-d_0\right)\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}}\sin \left(2\omega t+\delta \right),$

and setting the input converter duty cycle equal to: d={tilde over (d)}+d₀; and (iii) assessing the effectiveness of the calculation of the correction term in attenuating the said reflected ripple signal and adaptively altering the values of k and δ to improve the effectiveness.

Additionally, in some embodiments, controlling the input converter may include (i) providing to the inverter controller: a value indicative of the size of the bus capacitor, C_bus, a value ω indicative of the grid frequency, a value φ indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage, a measurement of the inverter output power, P_out, a measurement of the unipolar bus voltage, V_bus0, a measurement of the grid phase, θ; (ii) calculating a duty cycle for the input converter by: adjusting a nominal duty cycle, d₀, to a value that is consistent with delivering the pre-determined amount of power, calculating a correction term, {tilde over (d)}, for attenuating a reflected ripple signal, ĩ_r, at a frequency 2ω:

$\tilde{d}=k\left(1-d_0\right)\frac{P_{\mathrm{out}}}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t+\delta \right),$

and setting the input converter duty cycle equal to: d={tilde over (d)}+d₀; and (iii) assessing the effectiveness of the calculation of the correction term in attenuating the said reflected ripple signal and adaptively altering the values of k and δ to improve the effectiveness.

Additionally, in some embodiments, controlling the input converter may include (i) providing to the inverter controller: a value C_bus indicative of the size of the bus capacitor, a value ω indicative of the grid frequency, a value η indicative of the operating efficiency of the inverter, a value φ indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage, a measurement P_s of the power delivered by the unipolar input source, a measurement V_bus0 of the unipolar bus voltage, a measurement θ of the grid phase; (ii) calculating a duty cycle for the input converter by: adjusting a nominal duty cycle, d₀, to a value that is consistent with delivering the pre-determined amount of power, calculating a correction term, {tilde over (d)}, for attenuating a reflected ripple signal, ĩ_r, at a frequency 2ω:

$\tilde{d}=k\left(1-d_0\right)\frac{P_s}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t+\delta \right),$

and setting the input converter duty cycle equal to: d={tilde over (d)}+d₀; and (iii) assessing the effectiveness of the calculation of the correction term in attenuating the said reflected ripple signal and adaptively altering the values of k and δ to improve the effectiveness.

Additionally, in some embodiments, controlling the input converter may include (i) providing to the inverter controller: a value C_bus indicative of the size of the bus capacitor, a value ω indicative of the grid frequency, a value η indicative of the operating efficiency of the inverter, a value φ indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage, a measurement of the voltage delivered by the unipolar input source, V_s, a measurement of current delivered by the unipolar input source, I_s, a measurement V_bus0 of the unipolar bus voltage, a measurement of the grid phase, θ; (ii) calculating a duty cycle for the input converter by: adjusting a nominal duty cycle, d₀, to a value that is consistent with delivering the pre-determined amount of power; calculating a correction term, {tilde over (d)}, for attenuating a reflected ripple signal, ĩ_r, at a frequency 2ω:

$\tilde{d}=k\left(1-d_0\right)\frac{V_sI_s}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t+\delta \right),$

and setting the input converter duty cycle equal to: d={tilde over (d)}+d₀; and (iii) assessing the effectiveness of the calculation of the correction term in attenuating the said reflected ripple signal and adaptively altering the values of k and δ to improve the effectiveness.

Additionally, in some embodiments, assessing the effectiveness may include generating a signal, Q₁:

$Q_1=\{\begin{array}{cc}1& \mathrm{if}0<\mathrm{mod}\left(\theta ,\pi \right)<\frac{\pi }{2}\\ -1& \mathrm{otherwise};\end{array}$

then multiplying Q₁ and the reflected ripple signal to generate an error signal, e₁=Q₁·ĩ_in; and controlling the value of k to reduce the average value of e₁ towards zero.

Yet further, in some embodiments, assessing the effectiveness may include generating a signal, Q₂:

$Q_2=\{\begin{array}{cc}1& \mathrm{if}\frac{\pi }{4}<\mathrm{mod}\left(\theta ,\pi \right)<\frac{3\pi }{4}\\ -1& \mathrm{otherwise};\end{array}$

then multiplying Q₂ and the reflected ripple signal to generate an error signal, e₂=Q₂·ĩ_r; and controlling the value of δ to reduce the average value of e₂ towards zero.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one embodiment of an DC-to-AC inverter;

FIG. 2 is a block diagram of one embodiment of an input current controller for the inverters of FIGS. 1 and 9;

FIG. 3 is a block diagram of another embodiment of an input current controller for the inverters of FIGS. 1 and 9;

FIGS. 4 through 6 illustrate simulated inverter waveforms for the inverter of FIG. 9;

FIG. 7 is a block diagram of another embodiment of an input current controller for the inverters of FIGS. 1 and 9;

FIGS. 8A through 8E are simulated waveforms for the controller of FIG. 7;

FIG. 9 is a schematic of another embodiment of a DC-to-AC inverter;

FIG. 10 is a block diagram of another embodiment of an input current controller for the inverter of FIG. 9;

FIG. 11 is a block diagram of one embodiment of an output current controller for the inverter of FIG. 9;

FIG. 12 is a simplified schematic of one embodiment of an output filter for the inverter of FIG. 9;

FIGS. 13A through 13D are simulated waveforms for the inverter of FIGS. 9 through 12; and

FIGS. 14 through 17 are simplified flow diagrams of methods for controlling an input converter of the inverter of FIGS. 1 and 9.

DETAILED DESCRIPTION

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific exemplary embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

In the disclosure that follows, use of the same symbols for both actual and measured signals is for ease of discussion. The measured signals may be measured, converted between the analog and digital domains and vice versa, scaled, level-shifted, filtered, or isolated by known means as needed and it may also be assumed that power or other composite signals may be calculated from voltage and current signals. Furthermore, the fundamental and/or RMS value of the line voltage, V_line, as well as its phase angle, θ, may be determined by known means.

A simplified system topology for a DC-AC inverter 100 is shown in FIG. 1. The inverter 100 is configured to control the delivery of power from a unipolar input source 102 (e.g., a DC source, a photovoltaic solar cell or module, a fuel cell, or other unipolar input source) to an alternating-current (“AC”) grid 104 and, in some embodiments, loads coupled to the AC grid 104. In the discussion that follows, the unipolar input source 102 is assumed to be a photovoltaic cell (PV cell) as illustrated in FIG. 1. However, as discussed above, the unipolar input source 102 may be embodied as other unipolar input sources in other embodiments.

The AC grid 104 may be embodied as a utility power grid that supplies utility AC power to residential and industrial users. Such a grid is characterized by a substantially sinusoidal bipolar voltage (e.g., voltage V_line shown in FIG. 1, which may be 240VAC rms); a substantially constant grid frequency, f (e.g., f=ω/2π=50 Hz or 60 Hz); and a grid phase, θ, that is a function of the time integral of the grid frequency, ω (i.e., θ=θ₀+∫ωdt), where θ₀ is a constant and ω may vary with time). For clarity of the disclosure, the discussion that follows assumes a constant AC grid frequency (e.g. f=ω/2π=50 Hz or 60 Hz) and the phase of sinusoids is expressed as θ=(2πf)(t)=ωt. However, it should be appreciated that in practice there may be variations in AC grid frequency and a practical inverter may use known means to extract and use the actual time-varying AC grid phase: θ=θ₀+∫ωdt, as previously described.

The illustrative inverter 100 of FIG. 1 includes a current-fed input converter 106, output converter 110, and an inverter controller 119. The input converter 106 is configured to boost the relatively low PV cell voltage (e.g., 25V), V_s, to a unipolar bus 118 voltage, V_bus, where the DC value of V_bus is sufficiently high (e.g. 400V) to supply energy (via the output converter 110) to the AC grid 104 at the AC grid voltage, V_line (e.g., 240V, rms). Although the input converter 106 illustrated in FIG. 1 is a non-isolated boost switching power converter, it should be appreciated that an isolated boost switching power converter may be used in other embodiments (see, e.g., the isolated boost switching power converter 162 illustrated in FIG. 9).

The inverter controller 119 includes an input converter controller 120 and an output converter controller 140. The input converter controller 120 controls one or more switch(es) 114 of the input converter 106 to operate the PV cell at its maximum power point (“MPP”). A bus capacitor C_bus 187, is positioned across the voltage bus 118 and provides energy storage. Ideally, all of the double-frequency power that is delivered to the AC grid 104 is supplied by the bus capacitor 187. The output converter controller 140 operates the output converter 110 to deliver the energy supplied by the input converter 106 to the AC grid 104 as a substantially sinusoidal current, I_line, at the grid frequency.

Referring now to FIG. 2, in one embodiment, the input converter controller 120 may be embodied as an input converter controller 120a. The input converter controller 120a includes a maximum power point tracking (MPPT) controller 122, a feedback controller 124 (e.g., a proportional-integral (PI) controller), an average current mode (ACM) feedback control block 126, and a PWM control block 128. In one particular embodiment, the MPPT controller 122 and the PI controller 124 are implemented in firmware, and the ACM control block 126 and the PWM control block 128 are implemented in hardware. However, in other embodiments, each of the MPPT controller 122, the PI controller 124, the ACM control block 126, and the PWM control block 128 may be implemented in firmware and/or hardware.

In use, the MPPT controller 122 is configured to establish a maximum power point, P_mpp, for the PV cell 102 and calculates and delivers an input voltage command V_s*, indicative of the value of the PV cell 102 voltage, V_s, at the cell's MPP. It should be appreciated that the MPPT controller 122 may use any one of a number of different MPPT algorithms to establish the maximum power point (see, e.g., U.S. Pat. No. 7,681,090, issued Mar. 16, 2010 and entitled “Ripple Correlation Control Based on Limited Sampling” by Jonathan W. Kimball et al.).

The PI feedback controller 124 is configured to compare the voltage command, V_s*, received from the MPPT controller 122 to the actual value of the PV cell 102 voltage, V_s, and generate a converter input current setpoint, i_s* based thereon. The ACM control block 126 receives the input current command i_s* from the PI feedback controller 124 and is configured to generate and deliver a duty cycle command, d, to the PWM switch controller 128. The PWM switch controller 128 is configured to control the duty cycle of the input converter switch(es) 114 (see FIG. 1) based on the duty cycle command, d, so that the input converter input current, i_s, is controlled to be substantially equal to the value indicated by the command value i_s*.

Referring now to FIG. 3, in another embodiment, the input converter controller 120 may be embodied as an input converter controller 120b. The input converter controller 120b includes a maximum power point tracking (MPPT) controller 132; a feedforward active filter (FFAF) block 136; and a PWM control block 138. In the illustrative controller 120b of FIG. 3, the MPPT controller 132 is configured to measure the PV cell 102 voltage, V_s, and converter input current, i_s, (or PV cell current, i_pv, as discussed below). The MPPT controller 132 generates (using any of many known MPP algorithms as discussed above) a nominal duty cycle, d₀, at which the input converter 106 may withdraw maximum power from the PV cell 102. The FFAF block 136 receives the duty cycle, d₀, from the MPPT controller 132. Additionally, the FFAF block 136 receives a current signal, I_rms, indicative of the root-mean-square (rms) value of the inverter AC output current, I_line; a voltage signal, V_rms, indicative of the root-mean-square (rms) value of the AC grid voltage, V_line; a voltage signal, V_bus0, indicative of the average value of the unipolar bus voltage, V_bus; and a phase signal, θ=ωt=(2πf(t), indicative of the phase of the AC grid. Using these input signals, a computation block 137 of the FFAF block 136 is configured to calculate a time-varying correction term, {tilde over (d)}, that is added to the nominal duty cycle, d₀, to generate the input converter duty cycle signal, d={tilde over (d)}+d₀. The FFAF block 136 delivers the input converter duty cycle signal, d, to the PWM controller 138, which operates the input converter switch(es) 114 of the inverter 100 at the indicated duty cycle, d. As discussed in more detail below, the correction term, {tilde over (d)}, may enable substantially all of the double-frequency ripple to be filtered out of V_s.

The formula used in the calculation block 137 to calculate the correction term, {tilde over (d)}, may be derived from the average value model of the system shown in the FIG. 1. For example, using the input inductor current, i_s, and the bus capacitor voltage, V_bus, as state variables, the average value model can be expressed as follows:

$\begin{array}{cc}{L}_s\frac{i_s}{t}=V_s-\left(1-d\right)V_{\mathrm{bus}}& \left(1\right)\\ C_{\mathrm{bus}}=\frac{V_{\mathrm{bus}}}{t}=\left(1-d\right)i_s-i_b& \left(2\right)\end{array}$

where, with reference to FIG. 1, d is the duty cycle of the switch 114; L_s is the value of the input inductor 179; C_bus is the value of the bus capacitor 187; i_b is the magnitude of the current flowing into the output converter and filter 110; and V_bus, V_s, and i_s are, respectively, the unipolar bus 118 voltage, PV cell 102 voltage and input converter 106 input current, as shown in FIG. 1 and described above.

Representing each of the variables of equations (1) and (2) as a constant value (represented by variables that include a zero in their subscript) plus a time-varying double-frequency disturbance (represented by variables accented above with a tilde) provides:

i_s=I_s0+ĩ_s  (3)

V_s=V_s0+{tilde over (V)}_s  (4)

V_bus=V_bus0+{tilde over (V)}_s  (5)

i_b=I_b0+ĩ_b  (6)

d={tilde over (d)}+d₀  (7)

and using small-signal analysis and linearization:

$\begin{array}{cc}{L}_s=\frac{{\tilde{i}}_s}{t}={\tilde{V}}_s-\left(1-d\right){\tilde{V}}_{\mathrm{bus}}+\tilde{d}V_{\mathrm{bus}0}& \left(8\right)\end{array}$

Elimination of double-frequency ripple in i_s requires that:

ĩ_s=0.  (9)

Consequently:

{tilde over (V)}_s=0.  (10)

Substituting (9) and (10) into (8) and solving for {tilde over (d)} lead to:

$\begin{array}{cc}\tilde{d}=\left(1-d_0\right)\frac{{\tilde{V}}_{\mathrm{bus}}}{V_{\mathrm{bus}0}}.& \left(11\right)\end{array}$

Ideally, it is desired that the bus capacitor 187, C_bus, stores all the double-frequency energy. To do so:

$\begin{array}{cc}{C}_{\mathrm{bus}}\frac{\tilde{V}\mathrm{bus}}{t}=-{\tilde{i}}_b.& \left(12\right)\end{array}$

The inverter output power P_out is given as:

P_out=V_rmsI_rms[1+cos(2ωt)],  (13)

Where:

ω=2πf and f=AC grid frequency.  (14)

Assuming that the output converter and filter 110 is 100% efficient,

$\begin{array}{cc}\begin{array}{c}{i}_b=\frac{P_{\mathrm{out}}}{V_{\mathrm{bus}0}}\\ =\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{V_{\mathrm{bus}0}\left[1+\cos \left(2\omega t\right)\right]}.\end{array}& \left(15\right)\end{array}$

Therefore:

$\begin{array}{cc}{\tilde{i}}_b=\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{V_{\mathrm{bus}0}}\cos \left(2\omega t\right)& \left(16\right)\end{array}$

Using (12) and (16):

$\begin{array}{cc}{\tilde{V}}_{\mathrm{bus}}=-\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{2\omega V_{\mathrm{bus}0}C_{\mathrm{bus}}}\sin \left(2\omega t\right).& \left(17\right)\end{array}$

Combining (11) and (17) results in:

$\begin{array}{cc}\tilde{d}=-1\left(1-d_0\right)\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{2\omega V_{\mathrm{bus}0}C_{\mathrm{bus}}}\sin \left(2\omega t\right).& \left(18\right)\end{array}$

Thus, the double frequency rippled reflected back to V_s (i.e., the unipolar input source 102) may be filtered out by commanding the duty ratio d to be:

$\begin{array}{cc}d=d_0-1\left(1-d_0\right)\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{2\omega V_{\mathrm{bus}0}C_{\mathrm{bus}}}\sin \left(2\omega t\right).& \left(19\right)\end{array}$

where d₀ is provided by the MPPT controller 134 of FIG. 3 and the correction term {tilde over (d)} is computed by the computation block 137 in FFAF block 136 using the formulation shown in Equation 18.

Power balances in the inverter require that the power delivered to the AC grid equal the power delivered by the PV cell, less any circuit losses: hence, P_out=ηV_sI_s=ηP_s, where P_out is the power delivered by the inverter to the AC grid 104; V_s and I_s are, respectively, the PV cell 102 voltage and current; η is the inverter operating efficiency; and P_s is the power delivered by the PV cell 102. In the general case, P_out=V_rmsI_rms cos(φ) and thus:

$\begin{array}{c}{V}_{\mathrm{rms}}I_{\mathrm{rms}}=\frac{P_{\mathrm{out}}}{\cos \left(\phi \right)}\\ =\frac{P_s}{\cos \left(\phi \right)}\\ =\frac{V_sI_s}{\cos \left(\phi \right)}\end{array}$

(where φ is a pre-determined power factor angle representing a desired phase shift between the current delivered by the inverter and the AC grid voltage). The PV cell 102 voltage and current may be measured in some applications, and, in such embodiments, alternative formulations for the commanded duty cycle may therefore include:

$\begin{array}{cc}d=d_0-\left(1-d_0\right)\frac{P_{\mathrm{out}}}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t\right),& \left(19A\right)\\ d=d_0-\left(1-d_0\right)\frac{V_sI_s}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t\right),\mathrm{and}& \left(19B\right)\\ d=d_0-\left(1-d_0\right)\frac{P_s}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}\cos \left(\phi \right)}\sin \left(2\omega t\right).& \left(19C\right)\end{array}$

In the following description, certain modifications and alterations to the formulation given by Equation 19 will be discussed. However, it should be appreciated that those modifications and alterations are equally applicable to the formulations of Equations 19A through 19C, as well as to any equivalent formulations.

While the equations derived above are based on the non-isolated boost converter shown in FIG. 1, they are also valid for an isolated boost converter (see, e.g., boost converter 162 of FIG. 9) because the division of {tilde over (V)}_bus by V_bus0 (Equation 11) cancels out the effect of the isolation transformer turns ratio, n.

It should be appreciated that in the input converter controller 120b of FIG. 3, the wideband ACM feedback loop 126 and the feedback controller 124 are eliminated. Additionally, the determination of the duty cycle correction term, {tilde over (d)} (Equation 18), may be performed in firmware. Elimination of the wideband ACM current loop 126 may also eliminate the need to perform a wideband measurement of ĩ_s enabling ĩ_pv to be used instead of ĩ_s as the input to the MPPT controller 132 (e.g., as shown in FIG. 3). Because, in practice, ĩ_pv may be a “cleaner” signal than ĩ_s, and because the measurement bandwidth requirement may be relaxed, board layout and current sensing may be simplified.

In theory, controlling the input duty cycle, d, in conformance with Equation 19 may result in substantially zero reflected double-frequency ripple across the PV cell 102. In practice, however, a number of factors may cause the attenuation to be imperfect, including voltage and current measurement tolerances and errors; firmware-induced calculation errors; and unit-to-unit variations in the initial value, as well as time, temperature, and voltage-induced variations in the operating value of C_bus 187 that may cause the actual circuit value of C_bus to differ from the estimated value used to calculate {tilde over (d)} (e.g., in Equation 18). Likewise, if PV cell 102 power is used in calculating {tilde over (d)} (e.g., as in Equations 19A and 19B) variations in the actual operating value of inverter circuit efficiency may cause the actual value of η to differ from the estimated value used to calculate {tilde over (d)} (e.g., in Equations 19A, 19B). It should be appreciated that the preceding analysis also assumes there is no phase shift between input-reflected ripple disturbances and the AC grid 104. In practice, however, phase shift may be introduced by isolation transformers (in an isolated inverter, see, e.g., transformer 175 in isolated converter 162 of FIG. 9) and by the inverter output filter 110, or it may be purposely introduced as a power factor angle, φ, representing a desired amount of phase shift between the AC grid voltage and the current delivered by the inverter. Because Equation 19 assumes zero phase shift, and does not take such magnitude and phase effects into account, the calculated value of {tilde over (d)} may result in sub-optimal attenuation of reflected ripple. Thus, in practice, both magnitude and phase errors may contribute to errors or other imperfections in the calculation of {tilde over (d)} and these errors and imperfections may result in degradation in attenuation of the input-reflected double-frequency ripple.

In an example of the effect of circuit parameter variation, simulations were performed for an inverter 200 of the kind shown in FIG. 9, with a controller of the kind shown in FIG. 3, the results of which are illustrated in FIGS. 4-6. The inverter of FIG. 9 includes an isolated boost switching power converter 162 that receives power from PV cell 102 and delivers power to DC bus 118 at a nominal voltage of 400 VDC. Additionally, in the simulated embodiment, C_bus=23.4 microfarads and L_s=44 microhenries. The MPPT 132 algorithm used in the simulations performs a conventional hill-climbing algorithm that updates once in every AC line cycle with a step change of 0.1 V. The graph of FIG. 4 shows ripple in the PV cell current, i_pv, with all of the parameters in Equation 19 set equal to their corresponding values in the inverter circuit 100. The graph of FIG. 5 shows ripple in i_pv with the FFAF disabled (i.e., correction term {tilde over (d)}=0). The graph of FIG. 6 shows ripple in i_pv with the FFAF enabled and all of the parameters used in Equation 19 set equal to their corresponding values in the inverter circuit 100, with the exception of the value of C_bus which, in the converter circuit, is reduced to 70% of the nominal value used in Equation 19. Comparison of FIGS. 4 and 5 illustrates that an increased input ripple cancellation may be achieved if FFAF calculation parameters conform to their corresponding circuit parameters, whereas comparison of FIGS. 6 and 4 illustrates that differences between circuit parameters and FFAF calculation parameters may cause degradation in the ripple-reduction performance of an FFAF controller 136.

Referring now to FIG. 7, in another embodiment, the input converter controller 120 may be embodied as an input converter controller 120c, which is configured to automatically compensate for magnitude and phase errors that would otherwise contribute to errors or other imperfections in the calculated value of {tilde over (d)}. The input converter controller 120b includes a FFAF block 136a having a calculation block 137a configured to calculate a value of {tilde over (d)} that is modified, relative to the value calculated by Equation 18, by inclusion of a phase correction term, δ, and a gain correction term, k:

$\begin{array}{cc}\tilde{d}=k\left(1-d_0\right)\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}}\sin \left(2\omega t+\delta \right).& \left(20\right)\end{array}$

The correction terms, δ and k, are provided by a quadrature correction block 150, which receives measurements of the AC grid phase, θ=ωt, and the PV cell 102 current i_pv. A high-pass filter 152 extracts the double-frequency ripple component, ĩ_pv, from i_pv. The quadrature signals Q₁ and Q₂, delivered, respectively, by phase comparator blocks 154, 156 are defined as:

$\begin{array}{cc}{Q}_1=\{\begin{array}{cc}1& \mathrm{if}0<\mathrm{mod}\left(\mathrm{\omega t},\pi \right)<\pi /2\\ -1& \mathrm{otherwise}\end{array}& \left(21\right)\\ Q_2=\{\begin{array}{cc}1& \mathrm{if}\pi /4<\mathrm{mod}\left(\omega t,\pi \right)<3\pi /4\\ -1& \mathrm{otherwise}\end{array}& \left(22\right)\end{array}$

where the function mod(x,y) returns the remainder of the division of x by y (said another way, for y≠0, mod(x,y) has a value ω such that x=P·y+w, where P is an integer and w<y).

Various waveforms of the input converter controller 120 are illustrated in FIGS. 8a-8c. The graph of FIG. 8A shows the waveform of the AC grid voltage, V_line (FIG. 8A). Additionally, the graph of FIG. 8B shows the waveform for Q_j (FIG. 8B) and the graph of FIG. 8C shows the waveform for Q₂(FIG. 8C). As illustrated in FIGS. 8B and 8C, both signals Q₁ and Q₂ have zero average value and a fundamental frequency equal to twice the AC grid frequency (which corresponds to the frequency of the double-frequency ripple).

It should be appreciated that if only the phase, but not the magnitude, of the calculated value of {tilde over (d)} is incorrect, the locations of the peaks of the resultant double-frequency ripple, {tilde over (V)}_bus, will shift in phase (relative to the phase of the AC grid, ωt) as a function of the amount of phase error. If the phase of {tilde over (d)} is adjusted towards a correct value at which the ripple goes to zero, however, the phase shift in the locations of the peaks of {tilde over (d)} will converge on π/4 (and the magnitude of {tilde over (V)}_bus will converge on zero).

Likewise, if only the magnitude, but not the phase, of the calculated value of {tilde over (d)} is incorrect, the locations of the peaks of the resultant double-frequency ripple, {tilde over (V)}_bus, will shift in phase as a function of the amount of magnitude error. If the magnitude of {tilde over (d)} is adjusted towards a correct value at which the ripple goes to zero, however, the phase shift in the locations of the peaks of {tilde over (d)} will converge on π/2 (and the magnitude of {tilde over (V)}_bus will converge on zero).

Referring to FIGS. 8C, 8D and 8E, if the signal Q₂(see FIG. 8C) is multiplied by a double-frequency sinusoid (see FIG. 8D) having peaks whose locations are shifted in phase (relative to the zero phase point of the AC grid in FIG. 8A) by π/4, the resultant waveform (FIG. 8E) will have zero average value. Likewise, if the signal Q₁ (FIG. 8B) is multiplied by a double-frequency sinusoid having peaks whose locations are shifted in phase by π/2 (not shown), the resultant waveform will also have a zero average value. Therefore, it can be appreciated that when both the phase and magnitude of {tilde over (d)} are correctly adjusted to produce essentially zero double-frequency ripple, the error signals e₂=Q₂·ĩ_p, and e₁=Q₁·ĩ_pv will each have zero average value.

Referring back to FIG. 7, low-pass filters LPF₁ 162 and LPF₂ 164 (FIG. 7) filter the double-frequency (and higher) ripple components from e₁ and e₂, producing average error values e₁ and e₂, respectively. Proportional-integral (PI) filters PI₁ 166 and PI₂ 168 generate correction terms k and δ from e₁ and e₂, respectively. As the magnitude and phase of {tilde over (d)} diverge from the values required to eliminate the double-frequency ripple, one or the other, or both, of the signals e₁ and e₂ will diverge from zero and the output of the corresponding one (or both) of PI filters PI₁ and PI₂ will change, thereby changing one or the other, or both of the correction terms, k and δ, until the ripple has been controlled to be zero, after which the error values e₁ and e₂ will once again be zero and the values of k and δ will stop changing.

In operation, the quadrature corrector assesses the effectiveness of the calculation of {tilde over (d)} (e.g., the effectiveness of the calculation block 137a in feedforward controller 136a) in attenuating the double-frequency ripple and adaptively alters the calculation (e.g., by adjusting the magnitude and phase of {tilde over (d)}) to improve the effectiveness of attenuation. By “tuning” the magnitude and phase of {tilde over (d)}, quadrature correction may compensate for parametric or measurement tolerances and errors that might otherwise compromise the effectiveness of feedforward compensation alone (FIG. 3).

It should be appreciated that by using quadrature correction one or more features of the input converter controller may be obtained including: elimination of a wideband current loop (e.g., ACM block, FIG. 2) from the input converter controller and the attendant need for wideband current sensing and a wideband current sensor; simplified printed circuit board layout; simplification of control algorithms; ease of implementation in firmware; and more effective control action owing to the controllers ability to automatically adapt to parameter drift and computation tolerances and errors. In inverters in which a measurement of PV cell power is used in performing feedforward correction (e.g., using Equations 19A, 19B), the quadrature corrector will also be effective in compensating for variances between actual inverter circuit efficiency and the value of η used in calculating {tilde over (d)}. Thus, use of quadrature correction may enable effective use of PV cell power, instead of inverter output power, in performing feedforward correction, thereby eliminating the need to pass measurements of AC grid voltage and current to the feedforward calculation block.

Referring now to FIGS. 9-12, an illustrative inverter 200 is shown. The illustrated inverter 200 may be configured to deliver 225 Watts from a PV cell 102 to an AC grid 104 at a grid voltage V_rms=240 Volts, rms. In FIG. 9, an isolated boost switching converter 162 receives power from the unipolar input source 102 at voltage V_s (e.g., V_s=25 Volts) and current i_s. Isolated boost converter 162, comprising input inductor 179 (e.g., L_s=44 microhenries), voltage clamp 199, and transformer 175, is one of several possible current-fed converter topologies that may be used. The voltage clamp 199 clamps the voltage applied to the bridge circuit formed by the switches 171-174. The voltage clamp 199 may be embodied as a passive or active circuit. For example, in embodiments wherein the voltage clamp 199 is a passive circuit, a parallel diode and RC circuit may be used. The illustrative transformer 175, comprising primary winding 176 and secondary winding 178, provides galvanic isolation between the primary side converter circuitry (including input source 102) and the secondary side circuitry (including unipolar bus 118). The turns ratio of the transformer, n, (e.g., n=10) may also provide voltage and current transformation between the input source and the unipolar bus.

The inverter 200 further includes an inverter controller 229 comprising an input converter controller 220 and an output converter controller 240. The switches 171-174 in boost converter 162 are turned on and off, by gate signals q_Ic1 through q_Ic4, delivered from input converter controller 220, at relatively high switching frequency (e.g., at a frequency that is substantially higher than the AC grid frequency). Power is transferred to the unipolar output bus 118 via isolation transformer 175 and rectifiers 181-184. A bus filter capacitor 187 across the unipolar bus provides energy storage and filtering (e.g., C_bus=23.4 microfarads). A PV cell filter capacitor 188 is also provided across PV cell 102 (e.g., C_s=4.7 microfarad).

As illustrated in FIG. 10, the input converter controller 220 includes a maximum power point tracking (MPPT) controller 232; a feedforward active filter (FFAF) 236; and a quadrature corrector 250. PWM control block 138 receives a duty cycle command, d, from feedforward active filter (FFAF) block 236 and generates signals, q_Ic1 through q_Ic4, suitable to operate switches 171-174 at the indicated duty cycle.

The MPPT controller 232 receives measured values of the PV cell 102 voltage, V_s, PV cell current, i_pv, and the unipolar bus voltage V_bus. Low-pass filters 262, 264 (e.g., τ_vs=1/(400π); τ_is=1/(4000π)) remove noise from the signals and deliver filtered signals, {circumflex over (V)}_s and î_s, to MPPT algorithm block 266. The MPPT algorithm adjusts d₀ (using any of many known MPP algorithms) to a duty cycle, d₀, at which the PV cell delivers its maximum power, P_mpp. Multiplier 267 generates the product of the instantaneous values of V_s and i_s, indicating the instantaneous power delivered by PV cell 102; low-pass filter 270 receives the signal output of multiplier 267 generate a filtered signal, P_s=LPF(V_si_s) indicating the instantaneous power being delivered by PV cell 102.

The MPPT controller 232 may also include a limiting function 268 that may, depending on the value of the unipolar bus voltage, V_bus, set an upper limit, d_max, on the value of d₀. For example, as shown in FIG. 10, if V_bus is below a pre-determined value, V_bus—max1 (e.g., 450 V), there may be substantially no limit on the allowable maximum operating value of d₀ (e.g., d_max=0.98). As V_bus rises above V_bus—max1, however, the value of d₀ may be progressively reduced until, at a bus voltage at or above V_bus—max2 (e.g. 500 V) it may be reduced to substantially zero. By this means, power delivered by the input converter may be throttled back if the unipolar bus voltage rises above a defined limit, which might occur, for example, in the event of a rapid change in load or a grid fault.

The FFAF block 236 receives the value of d₀ from the MPPT and also receives signals V_line, V_bus0, and θ=ωt=(2πf)(t), indicative of, respectively, the root-mean-square (rms) value of the AC grid voltage, V_line, the average value of the unipolar bus voltage, V_bus, and the phase of the AC grid. Because, in some applications, it may be desirable to shift the phase of the inverter output current, I_line, relative to the phase, ωt, of the AC grid 104, the FFAF block 236 also receives a power factor angle command, φ, and a signal, î_line (received from output current controller 240 as shown in FIG. 11, and indicative of the peak value of the AC current that the output controller 240 is commanding to be delivered to the AC grid 104) and calculates, in calculation block 260, the corresponding rms value of the line current

$I_{\mathrm{rms}}=\frac{{\hat{i}}_{\mathrm{line}}}{\sqrt{2}\cos \left(\phi \right)}$

that is required to deliver the indicated power, P_s (see FIGS. 10 and 11), at the indicated power factor angle, φ. Using these measured and calculated values, and the phase and gain correction signals, k and δ, delivered to the FFAF block 236 from quadrature corrector 250, computation block 337 calculates a time-varying correction term, {tilde over (d)}, that is added to the nominal duty cycle, d₀, to generate the input converter duty cycle signal, d={tilde over (d)}+d₀, all as previously described with respect to FIGS. 3 and 7. The FFAF block 236 delivers the input converter duty cycle signal, d, to the PWM controller 138, which operates the input converter switches 171-174 at the indicated duty cycle, d.

Quadrature corrector 250, which may operate as described above with respect to FIG. 7, may comprise high pass filter 152 (e.g. ω_hpf=1/(24π) rad/s); phase comparator blocks 354, 356 having, respectively, the transfer functions defined in Equations 21 and 22, above; multipliers 358, 360; low pass filters 362, 364 (e.g., ω_lpf=1/(24π) rad/s); and proportional-integral filters 366, 368 (e.g., K_pk=0.15 and K_ik=27.5; K_pδ=0.25 and K_jδ=5).

Referring back to FIG. 9, an output converter 182 is embodied as a non-isolated full-bridge switching converter, comprising switches 190-193 that are controlled by output converter controller 240. The full-bridge configuration enables the output converter 182 to deliver a bipolar voltage, V_oc, and bipolar current i_line. An output filter 195, may be interposed between the output of the output converter 182 and the AC grid 104, to filter the voltage v_oc as a means of reducing conducted interference and satisfying regulatory requirements. As shown in FIG. 12, the filter 195 may comprise differential-mode inductors, L_OC1 196a and L_OC2 196b, a common-mode inductor L_line1-L_line2 197a, 197b, and line filter capacitor C_T 198.

A block diagram of an embodiment of the output converter controller 240 for use in an inverter according to the present disclosure is shown in FIG. 11. The output converter controller 240 controls the magnitude and phase of the sinusoidal AC current, i_oc, that is delivered by output converter 182 and also controls the average value of the unipolar bus voltage, V_bus0. The controller 240 receives measured values of the unipolar bus voltage V_bus, the converter output current i_oc, the rms value of the AC grid line voltage V_line(rms), and the phase of the AC grid, θ. Controller 240 also receives the commanded power factor angle (I), and the value of PV cell power, P_s, (received from MPPT controller 232 (FIG. 10)).

Low-pass filter 231 (e.g., ω_lpf=1/(20π)) extracts the average value, V_bus0, of the unipolar bus voltage V_bus, and delivers a measured average value of the unipolar bus voltage to the input of PI feedback controller 234 (e.g., K_pvbus=0.00375 A/V; K_ivbus=0.1 A/V·s), where it is compared to the commanded value of the average value of the unipolar bus voltage, V_bus*, by summing junction 235. Differences between the commanded average value and the measured average value of v_bus are reflected as variations in the signal output of the feedback controller, i_adj, which is delivered as an input to summing junction 238. The other input of summing junction 238 is a calculated nominal value for the line current,

$i_{\mathrm{linenom}}=\frac{\sqrt{2}P_s}{V_{\mathrm{line}\left(\mathrm{rms}\right)}},$

delivered by calculator block 237. i_linenom represents the ideal peak value of line current, at zero power factor, that would result in the output power being equal to the input power. Summing junction 238 adds i_adj to i_linenom to produce control signal .

Ignoring, for the moment, the positive signal limiter 239, the signal is received at the input of sinusoidal signal generator 244 as the signal . The sinusoidal signal generator 244 generates the sinusoidal, time-varying output current command i_oc*:

i_oc*=·(cos(ωt)−tan(φ)·sin(ωt))=·cos(ωt+φ)/cos(φ)  (23)

i_oc*=i_linenom·cos(ωt+φ)/cos(φ)+i_adj·cos(ωt+φ)/cos(φ)=iff(t)+ifb(t)  (24)

i_oc* consists of two components, a feedforward component,

$\mathrm{iff}\left(t\right)=i_{\mathrm{linenom}}\frac{\cos \left(\omega t+\phi \right)}{\cos \left(\phi \right)},$

representing the ideal time-varying line current that would result in delivery of Ps watts to the AC grid at the power factor angle φ, and a feedback component,

$\mathrm{ifb}\left(t\right)=i_{\mathrm{adj}}\frac{\cos \left(\omega t+\phi \right)}{\cos \left(\phi \right)},$

that is adjusted by feedback controller 234 to ensure that the inverter output power and input power are balanced, as explained below.

In operation, the power delivered to the AC grid should be equal to the power delivered by the solar cell, less the total of circuit and other losses, else the unipolar bus voltage may go out of control. If too little power is delivered to the grid, the bus voltage will rise; if too much is delivered, the bus voltage will fall. Because the calculated nominal value of line current, i_linenom, is subject to measurement and calculation errors and cannot accurately account for the range of possible variations in circuit losses and other factors that affect power delivery, i_line cannot be controlled by feedforward control alone.

During steady-state operation, variations in power delivered by the output converter may result in a variation in the average value of the unipolar bus voltage. For example, if the power delivered by the output stage is low relative to the power delivered by the input converter, the unipolar bus voltage will tend to increase. This increase will cause the output of feedback controller 234, i_adj, to increase, thereby increasing the magnitudes of ifb(t) and i_oc* (Equation 24) and increasing the power delivered to the AC grid 104. By this feedback process, the power delivered to the AC grid 104 will be adjusted so that power flow from input to output is properly balanced and so that the average value of the unipolar bus voltage is controlled to be at its commanded value, V_bus*.

The output current command, i_oc*, is delivered by sinusoidal signal generator 244 to summing junction 249 in PI controller 243 (e.g., K_pio=0.45 A/V and K_iio=5500). A filtered (by low pass filter 241, e.g., τ_ioc=1/(6000π) measurement of the output converter output current, î_oc, is delivered to the other input of summing junction 249. PI controller 243 delivers a duty cycle command d_io to PWM controller 247. By this means, the PI controller 243 may adjust the duty cycle of output converter 182 so that the value of the output current i_oc is controlled to be at the value commanded by i_oc*.

Referring again to FIG. 11, a bus voltage command calculator block 237 may be provided to adaptively adjust the value of V_bus*, and hence the value of V_bus0, as a function of selected variables. For example, reducing V_bus* in response to a reduction in V_line(rms) may improve overall inverter operating efficiency. One example of a bus voltage command calculator block 237 is shown in FIG. 11, in which the commanded value, V_bus* is a function of V_line and P_s (e.g., K₁=1, K₂=30/225 and K₃=120). Positive signal limiter 239 may be used to ensure that the command signal, , delivered to sinusoidal signal generator 244, cannot be negative; it may also limit the commanded value, , to be no greater than a pre-determined limit, i_line—max (e.g., i_{line max}=2 Amperes).

Simulation waveforms for the inverter of FIGS. 9-12 are illustrated in FIG. 13. The graph of FIG. 13A shows a gain correction term, k. The graph of FIG. 13B shows a phase correction term δ. The graph of FIG. 13C shows error signal e₁ 422 and average error value e₁ 424. The graph of FIG. 13D shows error signal e₂ 426 and average error value e₂ 428. The simulation waveforms are for operation with a circuit value of C_bus set equal to 16.38 microfarads, which is 70% of the value (23.4 microfards) used in performing the calculation of d within computation block 337; PV cell 102 input voltage V_s=25 Volts; PV cell MPP=225 Watts; cell filter capacitor 188, C_s=4.7 microfards; unipolar bus filter capacitor 187; C_bus=16.38 microfarads; input inductor 179; L_s=44 microhenries; transformer 175 turns ratio, n=10; average unipolar bus voltage, V_bus0=400 Volts; in the MPPT 232, τ_vs=τ_is=τ_p=1/(4000π); in the quadrature corrector 250, ω_hpf=ω_lpf=1/(24π) rad/sec, and K_pk=0.15 and K_ik=27.5, K_pδ=0.25 and K_iδ=5; in the output controller 240, ω_vbus=1/(20π) rad/sec, K_pvbus=0.00375 A/V, K_ivbus=0.1 A/V·s, i_line—max=2 Amperes, and K₁=1, K₂=30/225 and K₃=120; AC grid voltage, V_line(rms)=240 Volts rms; AC grid frequency=2π(60) rad/sec; in the output filter 195 (FIG. 12) L_OC1=L_OC2=3 millihenries, C_T=330 nanofarads, L_line1=1.25 millihenries, and L_line2=0.

As shown in FIGS. 13A and 13B, k is set to an initial value of 1 and Bis set to an initial value of 0 radians. In operation, the quadrature corrector 250 increases the value of k from an initial value of 1 to a final value of 1.4, which compensates for the use of a value of C_bus in calculation block 137 that is 1.4 times larger than the value use in the circuit; the quadrature corrector 250 also increases the value of δ from an initial value of 0 radians to a final value of 0.013 radians (too small an amount to be visible in FIG. 13B), which compensates for phase shift in the inverter (e.g., phase shift in the output filter 195). The duration of one cycle of the AC grid 104, T_line= 1/60 sec, is shown FIG. 13B. As shown in FIGS. 13C and 13D, both error signals, and their respective average values, converge rapidly and smoothly toward their final values. Convergence is substantially complete in a time period that is not much longer than two line cycles (i.e., 2T_line).

Referring now to FIG. 14, a flow diagram illustrating a method 501 of controlling an inverter of the kind that delivers power from a unipolar input source to an AC grid, and that comprises an input converter for delivering a pre-determined amount of power from the unipolar input source to a unipolar bus; an energy storage capacitor for supplying energy to and absorbing energy from the unipolar bus; an output converter for delivering power from the unipolar bus to the AC grid; and an inverter controller to control the operation of the input converter and the output converter. As previously discussed, the input converter and the output converter may, respectively, comprise a switching power converter, and the inverter controller may comprise an input converter controller for controlling the current delivered by the input converter and an output converter controller for controlling the power delivered by the output converter to the AC grid is shown.

As shown in FIG. 14, the method 501 begins with block 502 in which the input converter controller may receive a value, P, indicative of a pre-determined amount of power to be delivered from the input source. In block 504, the input converter controller may calculate a duty cycle for the input converter such that: (1) the input converter delivers the pre-determined amount of power, and (2) the magnitude of a ripple signal reflected into the input source may be attenuated toward zero. Additionally, in block 506, the input converter controller may assess the effectiveness of the calculation in attenuating the ripple and adaptively alter the calculation to improve the effectiveness.

Referring to FIG. 15, one embodiment of a method 510 for calculating a duty cycle for the input converter, which may be executed in block 504 of method 501, is shown. The method 510 begins with block 512 in which a nominal duty cycle, d₀, is adjusted to a value that is consistent with withdrawing maximum power (e.g., P=P_mpp) from the input source. In block 514, for an AC grid frequency, ω, and grid phase, θ=ωt, a correction term,

$\tilde{d}=-k\left(1-d_0\right)\frac{V_{\mathrm{rms}}I_{\mathrm{rms}}}{2\omega V_{\mathrm{bus}0}^2C_{\mathrm{bus}}}\sin \left(2\omega t+\delta \right),$

is calculated for attenuating a double-frequency ripple signal. In block 514, the input converter duty cycle is set to d={tilde over (d)}+d₀. Subsequently, in block 516, the effectiveness of the calculation in attenuating the double-frequency ripple and adaptively altering the values of k and δ to improve the effectiveness is assessed.

Referring now to FIG. 16, a method 520 for assessing the effectiveness of the calculation performed in the method of 510 may be used. The method 520 begins with block 522, in which a signal, Q₂, is generated according to:

$Q_2=\{\begin{array}{cc}1& \mathrm{if}\frac{\pi }{4}<\mathrm{mod}\left(\omega t,\pi \right)<\frac{3\pi }{4}\\ -1& \mathrm{otherwise}.\end{array}$

In block 524, the double-frequency ripple signal is multiplied by the signal Q₂ to generate an error signal, e₂. Subsequently, in block 526, the value of δ is controlled to thereby reduce the average value of the error, e₂, towards zero.

Referring now to FIG. 17, a method 530 for assessing the effectiveness of the calculation performed in the method of 510 may also be used. The method 530 begins with block 532 in which a signal, Q₂, is generated according to:

$Q_1=\{\begin{array}{cc}1& \mathrm{if}0<\mathrm{mod}\left(\omega t,\pi \right)<\frac{\pi }{2}\\ -1& \mathrm{otherwise}.\end{array}$

In block 534, the double-frequency ripple signal is multiplied by the signal Q₁ to generate an error signal, e₁. Subsequently, in block 536, the value of k is controlled to reduce the average value of the error, e₁, towards zero.

The inverter, controllers, and methods described herein may be implemented as discrete circuits or in the form of software code and/or logical instructions that are processed by a microprocessor, digital processor, DSP or other means, or any combination thereof. The logical processes may run concurrently or sequentially with respect to each other or with respect to other processes, such as measurement processes and related calculations. Controllers may be implemented in mixed-signal circuitry; in circuitry comprising mixed-signal circuitry comprising a digital processor core; or in circuitry comprising a combination of mixed-signal circuitry and a separate digital signal processor. The controllers may be implemented as an integrated circuit or a hybrid device. There may also be additional logical processes that are not be shown for clarity of description, such as, e.g., safety and protection mechanisms; timing and frequency generation mechanisms; and hardware and processes related to regulatory requirements. Pre-determined values, such as, e.g., the value of used for C_bus in Equation 19, may be stored in read-only or re-programmable non-volatile memory or other storage media. Communication means may also be incorporated into the inverter as a means of downloading commanded values or other operating information to the inverter and/or for uploading inverter operating information to user equipment.

Certain embodiments of the present disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, any of a wide variety of known non-resonant and resonant switching power converter topologies may be used in place of the specific converter embodiments described herein. The unipolar input source may be a fuel cell or another kind of DC source. The inverter controller may comprise elements for regulatory and safety monitoring and control (e.g., circuits or processes for disabling the inverter in the event of AC grid fault or input source fault; anti-islanding protection). Switches in power converters (e.g., switches 171-174, FIG. 9) are shown to be MOSFETs and to comprise diodes across their terminals. It is understood that other types of switches may be used (e.g., bipolar transistors, IGBTs) and that diodes may be intrinsic to the semiconductor switch or may be discrete devices. Switches may also be provided with passive or active snubbers to prevent losses and/or to limit voltage or current stresses.

There is a plurality of advantages of the present disclosure arising from the various features of the apparatuses, circuits, and methods described herein. It will be noted that alternative embodiments of the apparatuses, circuits, and methods of the present disclosure may not include all of the features described yet still benefit from at least some of the advantages of such features. Those of ordinary skill in the art may readily devise their own implementations of the apparatuses, circuits, and methods that incorporate one or more of the features of the present disclosure and fall within the spirit and scope of the present invention as defined by the appended claims.

Claims

1. An apparatus for controlling the delivery of power from a unipolar input source to an alternating-current (AC) grid, the AC grid characterized by a grid voltage, Vrms, a nominal grid frequency ω, and a grid phase θ, the apparatus comprising:

an inverter including (i) an input converter configured to deliver power from the unipolar input source to a unipolar bus, (ii) an energy storage element coupled to the unipolar bus and configured to supply energy to and absorb energy from the unipolar bus, and (iii) an output converter coupled to the unipolar bus and configured to deliver power from the unipolar bus to the AC grid in the form of a substantially sinusoidal current at the grid frequency; and

an input converter controller coupled to the input converter and comprising

(i) a feedforward controller configured to perform a calculation to determine a value for a duty cycle for the input converter such that a magnitude of a ripple signal reflected into the input source is attenuated toward zero and (ii) a quadrature corrector configured to determine the effectiveness of the calculation in attenuating the ripple and to adaptively alter the calculation to improve the effectiveness of the calculation.

2. (canceled)

3. The apparatus of claim 1, wherein the energy storage element is a capacitor.

4-6. (canceled)

7. The apparatus of claim 1, wherein:

the quadrature corrector is configured to deliver a phase correction term, δ, and a gain correction term, k, to the feedforward controller, and

the feedforward controller calculates a duty cycle, d, of the form: d=d0−k·C·, wherein d0 is indicative of the duty cycle that is required to deliver a pre-determined amount of power.

8. The apparatus of claim 7, wherein: C = ( 1 - d 0 )  V rms  I rms 2   ω   V bus   0 2  C bus  sin  ( 2  ω   t ).

the energy storage element is a storage capacitor of value Cbus; and

the feedforward controller is configured to receive (i) measurements indicative of the value of the rms value of the AC grid voltage, Vrms, (ii) the rms value of the substantially sinusoidal current delivered by the output converter, Irms, and (iii) the value of the unipolar bus voltage, Vbus0; and to set

9. The apparatus of claim 7, wherein: C = ( 1 - d 0 )  P out 2   ω   V bus   0 2  C bus  cos  ( φ )  sin  ( 2  ω   t ).

the energy storage element is a storage capacitor of value Cbus, and

the feedforward controller is configured to receive (i) a measurement indicative of the value of the power delivered by the inverter to the AC grid, Pout, and (ii) a value, φ, indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage; and to set

10. The apparatus of claim 7, wherein: C = ( 1 - d 0 )  P s 2   ω   V bus   0 2  C bus  cos  ( φ )  sin  ( 2  ω   t ).

the energy storage element is a storage capacitor of value Cbus, and

the feedforward controller is configured to receive (i) a measurement indicative of the power delivered by the unipolar input source, Ps; (ii) a value, φ, indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage; and (iii) a value indicative of the operating efficiency of the inverter, η; and to set

11. The apparatus of claim 7, wherein: C = ( 1 - d 0 )  V s  I s 2   ω   V bus   0 2  C bus  cos  ( φ )  sin  ( 2  ω   t ).

the energy storage element is a storage capacitor of value Cbus; and

the feedforward controller is configured to receive (i) measurements indicative of the value of the voltage delivered by the unipolar input source, Vs, (ii) measurements indicative of the value of the current delivered by the unipolar input source, Is, (iii) a value, φ, indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage, and (iv) a value indicative of the operating efficiency of the inverter, η; and to set

12. The apparatus of claim 7, wherein the quadrature corrector comprises a first low pass filter, the first low pass filter being configured to receive a measurement indicative of the magnitude of an input current delivered by the unipolar input source, iin, and to deliver a double-frequency signal, ĩin indicative of the magnitude of the component of the input current ripple that is twice the frequency of the AC grid frequency.

13. The apparatus of claim 12, wherein the quadrature corrector further comprises a phase error detector configured to generate a phase error signal based upon a difference between the phase of the double-frequency signal and the grid phase, θ,

wherein the phase error signal has a zero average value when said difference is substantially zero.

14. The apparatus of claim 13, wherein the phase error detector comprises: Q 2 = { 1 if   π 4 < mod  ( θ, π ) < 3  π 4 - 1 otherwise;

a first phase comparator that receives a signal indicative of the grid phase, θ, and delivers a signal, Q2, such that:

a first multiplier that delivers a phase error signal, e2=Q2·ĩin;

a second low pass filter configured to deliver a signal e2 indicative of the average value of e2; and

a first proportional-integral filter configured to receive e2 and deliver the phase correction term, δ.

15. The apparatus of claim 14, wherein the quadrature corrector further comprises a gain error detector that generates a gain error signal based upon the magnitude of the double-frequency signal,

wherein the gain error signal has a zero average value when said magnitude is substantially zero.

16. The apparatus of claim 15, wherein the gain error detector comprises: Q 1 = { 1 if   0 < mod  ( θ, π ) < π 2 - 1 otherwise;

a second phase comparator that receives a signal indicative of the phase of the AC grid and delivers a signal:

a second multiplier that delivers a gain error signal, e1=Q1·ĩin;

a third low pass filter configured to deliver a signal e1 indicative of the average value of e1; and

a second proportional-integral filter configured to receive e1 and deliver the gain correction term, k.

17-30. (canceled)

31. A method for controlling an inverter that is configured to deliver power from a unipolar input source to an alternating-current (“AC”) grid at a grid voltage and grid phase, comprising:

calculating a duty cycle for the an input converter of the inverter such that (a) the input converter delivers a pre-determined amount of power and (b) the magnitude of a ripple signal reflected into the input source is attenuated toward zero, and

determining the effectiveness of the calculation in attenuating the ripple and adaptively altering the calculation to improve the effectiveness of the calculation.

32-33. (canceled)

34. The method of claim 31, d ~ = k  ( 1 - d 0 )  V rms  I rms 2   ω   V bus   0 2  C bus  sin  ( 2  ω   t + δ ), and

further comprising providing to the inverter controller: a value indicative of the size of a bus capacitor, Cbus, a value indicative of the grid frequency, ω, a measurement of the rms grid voltage, Vrms, a measurement of the rms inverter output current, Irms, a measurement of the unipolar bus voltage, Vbus0, a measurement of the grid phase, θ;

wherein calculating the duty cycle for the input converter comprises calculating a duty cycle for the input converter by: adjusting a nominal duty cycle, d0, to a value that is consistent with delivering the pre-determined amount of power, calculating a correction term, {tilde over (d)}, for attenuating a reflected ripple signal, ĩr, at a frequency 2ω:

setting the input converter duty cycle equal to: d={tilde over (d)}+d0; and assessing the effectiveness of the calculation of the correction term in attenuating the said reflected ripple signal and adaptively altering the values of k and δ to improve the effectiveness.

35. The method of claim 31, d ~ = k  ( 1 - d 0 )  P out 2   ω   V bus   0 2  C bus  cos  ( φ )  sin  ( 2  ω   t + δ ), and

further comprising providing to the inverter controller: a value indicative of the size of a bus capacitor, Cbus, a value indicative of the grid frequency, ω, a value, φ, indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage, a measurement of the inverter output power, Pout, a measurement of the unipolar bus voltage, Vbus0, a measurement of the grid phase, θ;

wherein calculating the duty cycle for the input converter comprises calculating a duty cycle for the input converter by: adjusting a nominal duty cycle, d0, to a value that is consistent with delivering the pre-determined amount of power, calculating a correction term, {tilde over (d)}, for attenuating a reflected ripple signal, ĩr, at a frequency 2ω:

setting the input converter duty cycle equal to: d={tilde over (d)}+d0; and assessing the effectiveness of the calculation of the correction term in attenuating the said reflected ripple signal and adaptively altering the values of k and δ to improve the effectiveness.

36. The method of claim 31, d ~ = k  ( 1 - d 0 )  P s 2   ω   V bus   0 2  C bus  cos  ( φ )  sin  ( 2  ω   t + δ ), and

further comprising providing to the inverter controller: a value indicative of the size of a bus capacitor, Cbus, a value indicative of the grid frequency, ω, a value indicative of the operating efficiency of the inverter, η, a value, φ, indicative of a phase difference between the phase of the current delivered to the AC grid and the phase of the AC grid voltage, a measurement of the power delivered by the unipolar input source, Ps, a measurement of the unipolar bus voltage, Vbus0, a measurement of the grid phase, θ; and

wherein calculating the duty cycle for the input converter comprises calculating a duty cycle for the input converter by: adjusting a nominal duty cycle, d0, to a value that is consistent with delivering the pre-determined amount of power, calculating a correction term, {tilde over (d)}, for attenuating a reflected ripple signal, ĩr, at a frequency 2ω:

setting the input converter duty cycle equal to: d={tilde over (d)}+d0; and assessing the effectiveness of the calculation of the correction term in attenuating the said reflected ripple signal and adaptively altering the values of k and δ to improve the effectiveness.

37. The method of claim 31, d ~ = k  ( 1 - d 0 )  V s  I s 2   ω   V bus   0 2  C bus  cos  ( φ )  sin  ( 2  ω   t + δ ), and

further comprising providing to the inverter controller: a value indicative of the size of a bus capacitor, Cbus, a value indicative of the grid frequency, ω, a value indicative of the operating efficiency of the inverter, η, a value, φ, indicative of a phase difference between the phase of the wherein calculating the duty cycle for the input converter comprises current delivered to the AC grid and the phase of the AC grid voltage, a measurement of the voltage delivered by the unipolar input source, Vs, a measurement of current delivered by the unipolar input source, Is, a measurement of the unipolar bus voltage, Vbus0, a measurement of the grid phase, θ; and

calculating a duty cycle for the input converter by: adjusting a nominal duty cycle, d0, to a value that is consistent with delivering the pre-determined amount of power; calculating a correction term, {tilde over (d)}, for attenuating a reflected ripple signal, ĩr, at a frequency 2ω:

setting the input converter duty cycle equal to: d={tilde over (d)}+d0; and assessing the effectiveness of the calculation of the correction term in attenuating the said reflected ripple signal and adaptively altering the values of k and δ to improve the effectiveness.

38. The method of claim 34, wherein assessing the effectiveness comprises: Q 1 = { 1 if   0 < mod  ( θ, π ) < π 2 - 1 otherwise;

generating a signal, Q1:

multiplying Q1 and the reflected ripple signal to generate an error signal, e1=Q1·ĩin; and

controlling the value of k to reduce the average value of e1 towards zero.

39. The method of claim 34, wherein assessing the effectiveness comprises: Q 2 = { 1 if   π 4 < mod  ( θ, π ) < 3  π 4 - 1 otherwise;

generating a signal, Q2:

multiplying Q2 and the reflected ripple signal to generate an error signal, e2=Q2·ĩr; and

controlling the value of δ to reduce the average value of e2 towards zero.